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i.MX6: nitrogen6x: Don't bother setting PLL3(480) PFD1 divisor

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This clock isn't feeding anything under U-Boot, so there's no
point in changing it from power-on default.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
This commit is contained in:
Eric Nelson 2013-08-29 12:37:36 -07:00 • committed by Stefano Babic
parent 3fc4176dc4
commit 67d54c3917
1 changed files with 0 additions and 5 deletions
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5
board/boundary/nitrogen6x/nitrogen6x.c
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@ -622,7 +622,6 @@ int board_video_skip(void)
static void setup_display(void) static void setup_display(void)
{ {
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg; int reg;
@ -633,10 +632,6 @@ static void setup_display(void)
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
writel(reg, &mxc_ccm->CCGR3); writel(reg, &mxc_ccm->CCGR3);
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
/* set LDB0, LDB1 clk select to 011/011 */ /* set LDB0, LDB1 clk select to 011/011 */
reg = readl(&mxc_ccm->cs2cdr); reg = readl(&mxc_ccm->cs2cdr);
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK