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i.MX6: nitrogen6x: Don't bother setting PLL3(480) PFD1 divisor
This clock isn't feeding anything under U-Boot, so there's no point in changing it from power-on default. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
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1 changed files with 0 additions and 5 deletions
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@ -622,7 +622,6 @@ int board_video_skip(void)
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static void setup_display(void)
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static void setup_display(void)
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{
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int reg;
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int reg;
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@ -633,10 +632,6 @@ static void setup_display(void)
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reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
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reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
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writel(reg, &mxc_ccm->CCGR3);
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writel(reg, &mxc_ccm->CCGR3);
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/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
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writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
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writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
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/* set LDB0, LDB1 clk select to 011/011 */
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/* set LDB0, LDB1 clk select to 011/011 */
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reg = readl(&mxc_ccm->cs2cdr);
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reg = readl(&mxc_ccm->cs2cdr);
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reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
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reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
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