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stm32mp: limit size of cacheable DDR in pre-reloc stage
In pre-reloc stage, U-Boot marks cacheable the DDR limited by the new config CONFIG_DDR_CACHEABLE_SIZE. This patch allows to avoid any speculative access to DDR protected by firewall and used by OP-TEE; the "no-map" reserved memory node in DT are assumed after this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. Without security, in basic boot, the value is equal to STM32_DDR_SIZE. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
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3 changed files with 17 additions and 2 deletions
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@ -93,6 +93,19 @@ config SYS_TEXT_BASE
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config NR_DRAM_BANKS
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default 1
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config DDR_CACHEABLE_SIZE
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hex "Size of the DDR marked cacheable in pre-reloc stage"
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default 0x10000000 if TFABOOT
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default 0x40000000
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help
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Define the size of the DDR marked as cacheable in U-Boot
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pre-reloc stage.
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This option can be useful to avoid speculatif access
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to secured area of DDR used by TF-A or OP-TEE before U-Boot
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initialization.
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The areas marked "no-map" in device tree should be located
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before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
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config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
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hex "Partition on MMC2 to use to load U-Boot from"
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depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
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@ -230,7 +230,8 @@ static void early_enable_caches(void)
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round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
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DCACHE_DEFAULT_OPTION);
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else
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mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
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mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
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CONFIG_DDR_CACHEABLE_SIZE,
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DCACHE_DEFAULT_OPTION);
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}
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@ -138,7 +138,8 @@ void board_init_f(ulong dummy)
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* to avoid speculative access and issue in get_ram_size()
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*/
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if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
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mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
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CONFIG_DDR_CACHEABLE_SIZE,
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DCACHE_DEFAULT_OPTION);
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}
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