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ARM: DRA72: DDR3: Add emif settings for 666MHz clock
On DRA72x, EMIF supports DDR3 upto 667MHz. Adding the required settings for DDR3 at 666MHz and enabling it. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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parent
bf88720850
commit
681f785f7c
2 changed files with 96 additions and 3 deletions
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@ -227,6 +227,16 @@ static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
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{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
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{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
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};
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};
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static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
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{111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
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{555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
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};
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static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
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static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
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{266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
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{266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
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@ -286,6 +296,17 @@ struct dplls dra7xx_dplls = {
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.gmac = gmac_dpll_params_2000mhz,
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.gmac = gmac_dpll_params_2000mhz,
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};
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};
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struct dplls dra72x_dplls = {
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.mpu = mpu_dpll_params_1ghz,
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.core = core_dpll_params_2128mhz_dra7xx,
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.per = per_dpll_params_768mhz_dra7xx,
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.abe = abe_dpll_params_sysclk2_361267khz,
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.iva = iva_dpll_params_2330mhz_dra7xx,
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.usb = usb_dpll_params_1920mhz,
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.ddr = ddr_dpll_params_2664mhz,
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.gmac = gmac_dpll_params_2000mhz,
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};
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struct pmic_data palmas = {
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struct pmic_data palmas = {
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.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
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.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
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.step = 10000, /* 10 mV represented in uV */
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.step = 10000, /* 10 mV represented in uV */
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@ -560,6 +581,18 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
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.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
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.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
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};
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};
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const struct ctrl_ioregs ioregs_dra72x_es1 = {
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.ctrl_ddrch = 0x40404040,
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.ctrl_lpddr2ch = 0x40404040,
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.ctrl_ddr3ch = 0x60606080,
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.ctrl_ddrio_0 = 0xA2084210,
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.ctrl_ddrio_1 = 0x84210840,
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.ctrl_ddrio_2 = 0x84210000,
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.ctrl_emif_sdram_config_ext = 0x0001C1A7,
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.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
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.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
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};
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void hw_data_init(void)
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void hw_data_init(void)
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{
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{
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u32 omap_rev = omap_revision();
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u32 omap_rev = omap_revision();
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@ -592,7 +625,7 @@ void hw_data_init(void)
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case DRA722_ES1_0:
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case DRA722_ES1_0:
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*prcm = &dra7xx_prcm;
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*prcm = &dra7xx_prcm;
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*dplls_data = &dra7xx_dplls;
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*dplls_data = &dra72x_dplls;
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*omap_vcores = &dra722_volts;
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*omap_vcores = &dra722_volts;
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*ctrl = &dra7xx_ctrl;
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*ctrl = &dra7xx_ctrl;
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break;
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break;
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@ -619,9 +652,11 @@ void get_ioregs(const struct ctrl_ioregs **regs)
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break;
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break;
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case DRA752_ES1_0:
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case DRA752_ES1_0:
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case DRA752_ES1_1:
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case DRA752_ES1_1:
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case DRA722_ES1_0:
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*regs = &ioregs_dra7xx_es1;
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*regs = &ioregs_dra7xx_es1;
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break;
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break;
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case DRA722_ES1_0:
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*regs = &ioregs_dra72x_es1;
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break;
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default:
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default:
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printf("\n INVALID OMAP REVISION ");
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printf("\n INVALID OMAP REVISION ");
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@ -185,6 +185,30 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
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.emif_rd_wr_exec_thresh = 0x00000305
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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};
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const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
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.sdram_config_init = 0x61851AB2,
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.sdram_config = 0x61851AB2,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x00001035,
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.sdram_tim1 = 0xCCCF36B3,
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.sdram_tim2 = 0x308F7FDA,
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.sdram_tim3 = 0x027F88A8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x0007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400A,
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.emif_ddr_phy_ctlr_1 = 0x0024400A,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
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.emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
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.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
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.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
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const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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@ -267,6 +291,8 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
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}
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}
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break;
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break;
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case DRA722_ES1_0:
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case DRA722_ES1_0:
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*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
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break;
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default:
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default:
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*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
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*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
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}
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}
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@ -450,6 +476,35 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
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0x0
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0x0
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};
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};
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const u32
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dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
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0x00A400A4,
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0x00390039,
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0x00320032,
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0x00320032,
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0x00320032,
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0x00440044,
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0x00550055,
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0x00550055,
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0x00550055,
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0x00550055,
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0x007F007F,
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0x004D004D,
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0x00430043,
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0x00560056,
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0x00540054,
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0x00600060,
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0x0,
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0x00600020,
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0x40010080,
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0x08102040,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0
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};
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const struct lpddr2_mr_regs mr_regs = {
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const struct lpddr2_mr_regs mr_regs = {
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.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
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.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
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.mr2 = 0x6,
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.mr2 = 0x6,
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@ -478,7 +533,6 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
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break;
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break;
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case DRA752_ES1_0:
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case DRA752_ES1_0:
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case DRA752_ES1_1:
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case DRA752_ES1_1:
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case DRA722_ES1_0:
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if (emif_nr == 1) {
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if (emif_nr == 1) {
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*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
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*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
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*size =
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*size =
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@ -489,6 +543,10 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
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ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
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ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
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}
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}
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break;
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break;
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case DRA722_ES1_0:
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*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
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*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
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break;
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default:
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default:
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*regs = ddr3_ext_phy_ctrl_const_base_es2;
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*regs = ddr3_ext_phy_ctrl_const_base_es2;
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*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
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*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
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