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socrates: Update NAND driver to new API.

Browse source 
Also, fix some minor formatting issues, and simplify the handling of
"state" for writes.

Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Scott Wood 2008-08-13 18:24:05 -05:00
parent ba22d10f39
commit 68cf19aae4
1 changed files with 32 additions and 52 deletions
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84
board/socrates/nand.c
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@ -31,22 +31,20 @@
static int state; static int state;
static void nand_write_byte(struct mtd_info *mtd, u_char byte); static void nand_write_byte(struct mtd_info *mtd, u_char byte);
static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
static void nand_write_word(struct mtd_info *mtd, u16 word);
static u_char nand_read_byte(struct mtd_info *mtd); static u_char nand_read_byte(struct mtd_info *mtd);
static u16 nand_read_word(struct mtd_info *mtd); static u16 nand_read_word(struct mtd_info *mtd);
static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len); static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
static int nand_device_ready(struct mtd_info *mtdinfo); static int nand_device_ready(struct mtd_info *mtdinfo);
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd);
#define FPGA_NAND_CMD_MASK (0x7 << 28) #define FPGA_NAND_CMD_MASK (0x7 << 28)
#define FPGA_NAND_CMD_COMMAND (0x0 << 28) #define FPGA_NAND_CMD_COMMAND (0x0 << 28)
#define FPGA_NAND_CMD_ADDR (0x1 << 28) #define FPGA_NAND_CMD_ADDR (0x1 << 28)
#define FPGA_NAND_CMD_READ (0x2 << 28) #define FPGA_NAND_CMD_READ (0x2 << 28)
#define FPGA_NAND_CMD_WRITE (0x3 << 28) #define FPGA_NAND_CMD_WRITE (0x3 << 28)
#define FPGA_NAND_BUSY (0x1 << 15) #define FPGA_NAND_BUSY (0x1 << 15)
#define FPGA_NAND_ENABLE (0x1 << 31) #define FPGA_NAND_ENABLE (0x1 << 31)
#define FPGA_NAND_DATA_SHIFT 16 #define FPGA_NAND_DATA_SHIFT 16
/** /**
* nand_write_byte - write one byte to the chip * nand_write_byte - write one byte to the chip
@ -58,16 +56,6 @@ static void nand_write_byte(struct mtd_info *mtd, u_char byte)
nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte)); nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
} }
/**
* nand_write_word - write one word to the chip
* @mtd: MTD device structure
* @word: data word to write
*/
static void nand_write_word(struct mtd_info *mtd, u16 word)
{
nand_write_buf(mtd, (const uchar *)&word, sizeof(word));
}
/** /**
* nand_write_buf - write buffer to chip * nand_write_buf - write buffer to chip
* @mtd: MTD device structure * @mtd: MTD device structure
@ -78,18 +66,10 @@ static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{ {
int i; int i;
struct nand_chip *this = mtd->priv; struct nand_chip *this = mtd->priv;
long val;
if ((state & FPGA_NAND_CMD_MASK) == FPGA_NAND_CMD_MASK) {
/* Write data */
val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_WRITE;
} else {
/* Write address or command */
val = state;
}
for (i = 0; i < len; i++) { for (i = 0; i < len; i++) {
out_be32(this->IO_ADDR_W, val | (buf[i] << FPGA_NAND_DATA_SHIFT)); out_be32(this->IO_ADDR_W,
state | (buf[i] << FPGA_NAND_DATA_SHIFT));
} }
} }
@ -148,7 +128,7 @@ static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
for (i = 0; i < len; i++) { for (i = 0; i < len; i++) {
if (buf[i] != nand_read_byte(mtd)); if (buf[i] != nand_read_byte(mtd));
return -EFAULT; return -EFAULT;
} }
return 0; return 0;
} }
@ -171,42 +151,42 @@ static int nand_device_ready(struct mtd_info *mtdinfo)
* @mtd: MTD device structure * @mtd: MTD device structure
* @cmd: Command * @cmd: Command
*/ */
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{ {
if (ctrl & NAND_CTRL_CHANGE) {
state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE);
switch(cmd) { switch (ctrl & (NAND_ALE | NAND_CLE)) {
case NAND_CTL_CLRALE: case 0:
state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */ state |= FPGA_NAND_CMD_WRITE;
break; break;
case NAND_CTL_CLRCLE:
state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */ case NAND_ALE:
break; state |= FPGA_NAND_CMD_ADDR;
case NAND_CTL_SETCLE: break;
state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_COMMAND;
break; case NAND_CLE:
case NAND_CTL_SETALE: state |= FPGA_NAND_CMD_COMMAND;
state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_ADDR; break;
break;
case NAND_CTL_SETNCE: default:
state |= FPGA_NAND_ENABLE; printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
break; }
case NAND_CTL_CLRNCE:
state &= ~FPGA_NAND_ENABLE; if (ctrl & NAND_NCE)
break; state |= FPGA_NAND_ENABLE;
default:
printf("%s: unknown cmd %#x\n", __FUNCTION__, cmd);
break;
} }
if (cmd != NAND_CMD_NONE)
nand_write_byte(mtdinfo, cmd);
} }
int board_nand_init(struct nand_chip *nand) int board_nand_init(struct nand_chip *nand)
{ {
nand->hwcontrol = nand_hwcontrol; nand->cmd_ctrl = nand_hwcontrol;
nand->eccmode = NAND_ECC_SOFT; nand->ecc.mode = NAND_ECC_SOFT;
nand->dev_ready = nand_device_ready; nand->dev_ready = nand_device_ready;
nand->write_byte = nand_write_byte;
nand->read_byte = nand_read_byte; nand->read_byte = nand_read_byte;
nand->write_word = nand_write_word;
nand->read_word = nand_read_word; nand->read_word = nand_read_word;
nand->write_buf = nand_write_buf; nand->write_buf = nand_write_buf;
nand->read_buf = nand_read_buf; nand->read_buf = nand_read_buf;