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https://github.com/Fishwaldo/u-boot.git
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socrates: Update NAND driver to new API.
Also, fix some minor formatting issues, and simplify the handling of "state" for writes. Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
parent
ba22d10f39
commit
68cf19aae4
1 changed files with 32 additions and 52 deletions
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@ -31,22 +31,20 @@
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static int state;
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static int state;
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static void nand_write_byte(struct mtd_info *mtd, u_char byte);
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static void nand_write_byte(struct mtd_info *mtd, u_char byte);
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static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
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static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
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static void nand_write_word(struct mtd_info *mtd, u16 word);
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static u_char nand_read_byte(struct mtd_info *mtd);
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static u_char nand_read_byte(struct mtd_info *mtd);
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static u16 nand_read_word(struct mtd_info *mtd);
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static u16 nand_read_word(struct mtd_info *mtd);
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static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
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static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
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static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
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static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
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static int nand_device_ready(struct mtd_info *mtdinfo);
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static int nand_device_ready(struct mtd_info *mtdinfo);
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static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd);
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#define FPGA_NAND_CMD_MASK (0x7 << 28)
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#define FPGA_NAND_CMD_MASK (0x7 << 28)
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#define FPGA_NAND_CMD_COMMAND (0x0 << 28)
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#define FPGA_NAND_CMD_COMMAND (0x0 << 28)
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#define FPGA_NAND_CMD_ADDR (0x1 << 28)
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#define FPGA_NAND_CMD_ADDR (0x1 << 28)
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#define FPGA_NAND_CMD_READ (0x2 << 28)
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#define FPGA_NAND_CMD_READ (0x2 << 28)
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#define FPGA_NAND_CMD_WRITE (0x3 << 28)
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#define FPGA_NAND_CMD_WRITE (0x3 << 28)
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#define FPGA_NAND_BUSY (0x1 << 15)
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#define FPGA_NAND_BUSY (0x1 << 15)
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#define FPGA_NAND_ENABLE (0x1 << 31)
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#define FPGA_NAND_ENABLE (0x1 << 31)
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#define FPGA_NAND_DATA_SHIFT 16
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#define FPGA_NAND_DATA_SHIFT 16
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/**
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/**
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* nand_write_byte - write one byte to the chip
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* nand_write_byte - write one byte to the chip
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@ -58,16 +56,6 @@ static void nand_write_byte(struct mtd_info *mtd, u_char byte)
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nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
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nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
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}
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}
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/**
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* nand_write_word - write one word to the chip
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* @mtd: MTD device structure
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* @word: data word to write
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*/
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static void nand_write_word(struct mtd_info *mtd, u16 word)
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{
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nand_write_buf(mtd, (const uchar *)&word, sizeof(word));
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}
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/**
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/**
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* nand_write_buf - write buffer to chip
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* nand_write_buf - write buffer to chip
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* @mtd: MTD device structure
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* @mtd: MTD device structure
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@ -78,18 +66,10 @@ static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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{
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int i;
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int i;
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struct nand_chip *this = mtd->priv;
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struct nand_chip *this = mtd->priv;
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long val;
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if ((state & FPGA_NAND_CMD_MASK) == FPGA_NAND_CMD_MASK) {
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/* Write data */
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val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_WRITE;
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} else {
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/* Write address or command */
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val = state;
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}
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for (i = 0; i < len; i++) {
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for (i = 0; i < len; i++) {
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out_be32(this->IO_ADDR_W, val | (buf[i] << FPGA_NAND_DATA_SHIFT));
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out_be32(this->IO_ADDR_W,
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state | (buf[i] << FPGA_NAND_DATA_SHIFT));
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}
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}
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}
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}
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@ -148,7 +128,7 @@ static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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for (i = 0; i < len; i++) {
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for (i = 0; i < len; i++) {
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if (buf[i] != nand_read_byte(mtd));
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if (buf[i] != nand_read_byte(mtd));
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return -EFAULT;
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return -EFAULT;
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}
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}
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return 0;
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return 0;
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}
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}
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@ -171,42 +151,42 @@ static int nand_device_ready(struct mtd_info *mtdinfo)
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* @mtd: MTD device structure
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* @mtd: MTD device structure
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* @cmd: Command
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* @cmd: Command
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*/
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*/
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static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
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static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
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{
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{
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if (ctrl & NAND_CTRL_CHANGE) {
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state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE);
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switch(cmd) {
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switch (ctrl & (NAND_ALE | NAND_CLE)) {
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case NAND_CTL_CLRALE:
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case 0:
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state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */
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state |= FPGA_NAND_CMD_WRITE;
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break;
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break;
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case NAND_CTL_CLRCLE:
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state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */
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case NAND_ALE:
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break;
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state |= FPGA_NAND_CMD_ADDR;
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case NAND_CTL_SETCLE:
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break;
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state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_COMMAND;
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break;
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case NAND_CLE:
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case NAND_CTL_SETALE:
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state |= FPGA_NAND_CMD_COMMAND;
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state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_ADDR;
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break;
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break;
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case NAND_CTL_SETNCE:
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default:
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state |= FPGA_NAND_ENABLE;
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printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
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break;
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}
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case NAND_CTL_CLRNCE:
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state &= ~FPGA_NAND_ENABLE;
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if (ctrl & NAND_NCE)
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break;
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state |= FPGA_NAND_ENABLE;
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default:
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printf("%s: unknown cmd %#x\n", __FUNCTION__, cmd);
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break;
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}
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}
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if (cmd != NAND_CMD_NONE)
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nand_write_byte(mtdinfo, cmd);
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}
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}
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int board_nand_init(struct nand_chip *nand)
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int board_nand_init(struct nand_chip *nand)
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{
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{
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nand->hwcontrol = nand_hwcontrol;
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nand->cmd_ctrl = nand_hwcontrol;
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nand->eccmode = NAND_ECC_SOFT;
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->dev_ready = nand_device_ready;
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nand->dev_ready = nand_device_ready;
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nand->write_byte = nand_write_byte;
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nand->read_byte = nand_read_byte;
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nand->read_byte = nand_read_byte;
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nand->write_word = nand_write_word;
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nand->read_word = nand_read_word;
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nand->read_word = nand_read_word;
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nand->write_buf = nand_write_buf;
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nand->write_buf = nand_write_buf;
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nand->read_buf = nand_read_buf;
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nand->read_buf = nand_read_buf;
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