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https://github.com/Fishwaldo/u-boot.git
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Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- SoCFPGA PL310 cleanup + A10 fix, A10 DT cleanup, DW GPIO fix.
This commit is contained in:
commit
696f02d99b
6 changed files with 58 additions and 64 deletions
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@ -16,10 +16,6 @@
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#size-cells = <1>;
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#size-cells = <1>;
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model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
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model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
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chosen {
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cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */
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};
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/* Clock sources */
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/* Clock sources */
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clocks {
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clocks {
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#address-cells = <1>;
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#address-cells = <1>;
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@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void);
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#endif
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#endif
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void do_bridge_reset(int enable, unsigned int mask);
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void do_bridge_reset(int enable, unsigned int mask);
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void socfpga_pl310_clear(void);
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#endif /* _MISC_H_ */
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#endif /* _MISC_H_ */
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@ -70,6 +70,60 @@ void v7_outer_cache_disable(void)
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/* Disable the L2 cache */
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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}
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void socfpga_pl310_clear(void)
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{
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u32 mask = 0xff, ena = 0;
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icache_enable();
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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writel(0x0, &pl310->pl310_tag_latency_ctrl);
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writel(0x10, &pl310->pl310_data_latency_ctrl);
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/* enable BRESP, instruction and data prefetch, full line of zeroes */
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setbits_le32(&pl310->pl310_aux_ctrl,
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L310_AUX_CTRL_DATA_PREFETCH_MASK |
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L310_AUX_CTRL_INST_PREFETCH_MASK |
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L310_SHARED_ATT_OVERRIDE_ENABLE);
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/* Enable the L2 cache */
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ena = readl(&pl310->pl310_ctrl);
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ena |= L2X0_CTRL_EN;
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/*
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* Invalidate the PL310 L2 cache. Keep the invalidation code
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* entirely in L1 I-cache to avoid any bus traffic through
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* the L2.
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*/
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asm volatile(
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".align 5 \n"
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" b 3f \n"
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"1: str %1, [%4] \n"
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" dsb \n"
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" isb \n"
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" str %0, [%2] \n"
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" dsb \n"
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" isb \n"
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"2: ldr %0, [%2] \n"
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" cmp %0, #0 \n"
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" bne 2b \n"
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" str %0, [%3] \n"
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" dsb \n"
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" isb \n"
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" b 4f \n"
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"3: b 1b \n"
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"4: nop \n"
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: "+r"(mask), "+r"(ena)
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: "r"(&pl310->pl310_inv_way),
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"r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
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: "memory", "cc");
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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#endif
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#endif
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#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
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#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
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@ -110,6 +110,7 @@ void board_init_f(ulong dummy)
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socfpga_init_security_policies();
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socfpga_init_security_policies();
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socfpga_sdram_remap_zero();
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socfpga_sdram_remap_zero();
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socfpga_pl310_clear();
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/* Assert reset to all except L4WD0 and L4TIMER0 */
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/* Assert reset to all except L4WD0 and L4TIMER0 */
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socfpga_per_reset_all();
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socfpga_per_reset_all();
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@ -5,7 +5,6 @@
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#include <common.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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#include <asm/u-boot.h>
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#include <asm/u-boot.h>
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#include <asm/utils.h>
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#include <asm/utils.h>
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#include <image.h>
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#include <image.h>
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@ -25,8 +24,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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static struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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static const struct socfpga_system_manager *sysmgr_regs =
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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@ -63,60 +60,6 @@ u32 spl_boot_mode(const u32 boot_device)
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}
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}
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#endif
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#endif
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static void socfpga_pl310_clear(void)
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{
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u32 mask = 0xff, ena = 0;
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icache_enable();
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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writel(0x111, &pl310->pl310_tag_latency_ctrl);
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writel(0x121, &pl310->pl310_data_latency_ctrl);
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/* enable BRESP, instruction and data prefetch, full line of zeroes */
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setbits_le32(&pl310->pl310_aux_ctrl,
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L310_AUX_CTRL_DATA_PREFETCH_MASK |
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L310_AUX_CTRL_INST_PREFETCH_MASK |
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L310_SHARED_ATT_OVERRIDE_ENABLE);
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/* Enable the L2 cache */
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ena = readl(&pl310->pl310_ctrl);
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ena |= L2X0_CTRL_EN;
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/*
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* Invalidate the PL310 L2 cache. Keep the invalidation code
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* entirely in L1 I-cache to avoid any bus traffic through
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* the L2.
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*/
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asm volatile(
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".align 5 \n"
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" b 3f \n"
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"1: str %1, [%4] \n"
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" dsb \n"
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" isb \n"
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" str %0, [%2] \n"
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" dsb \n"
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" isb \n"
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"2: ldr %0, [%2] \n"
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" cmp %0, #0 \n"
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" bne 2b \n"
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" str %0, [%3] \n"
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" dsb \n"
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" isb \n"
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" b 4f \n"
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"3: b 1b \n"
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"4: nop \n"
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: "+r"(mask), "+r"(ena)
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: "r"(&pl310->pl310_inv_way),
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"r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
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: "memory", "cc");
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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void board_init_f(ulong dummy)
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void board_init_f(ulong dummy)
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{
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{
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const struct cm_config *cm_default_cfg = cm_get_default_config();
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const struct cm_config *cm_default_cfg = cm_get_default_config();
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@ -185,12 +185,11 @@ static int gpio_dwapb_bind(struct udevice *dev)
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plat->name = ofnode_get_name(node);
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plat->name = ofnode_get_name(node);
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}
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}
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ret = device_bind(dev, dev->driver, plat->name,
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ret = device_bind_ofnode(dev, dev->driver, plat->name,
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plat, -1, &subdev);
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plat, node, &subdev);
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if (ret)
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if (ret)
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return ret;
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return ret;
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dev->node = node;
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bank++;
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bank++;
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}
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}
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