mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 06:31:31 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-mmc
This commit is contained in:
Tom Rini
commit
6983951a61
5 changed files with 83 additions and 38 deletions
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@ -90,7 +90,8 @@ static void print_mmcinfo(struct mmc *mmc)
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puts("Capacity: ");
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print_size(mmc->capacity, "\n");
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printf("Bus Width: %d-bit\n", mmc->bus_width);
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printf("Bus Width: %d-bit%s\n", mmc->bus_width,
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mmc->ddr_mode ? " DDR" : "");
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}
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static struct mmc *init_mmc_device(int dev, bool force_init)
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{
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@ -318,7 +318,7 @@ static void dwmci_set_ios(struct mmc *mmc)
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dwmci_writel(host, DWMCI_CTYPE, ctype);
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regs = dwmci_readl(host, DWMCI_UHS_REG);
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if (mmc->card_caps & MMC_MODE_DDR_52MHz)
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if (mmc->ddr_mode)
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regs |= DWMCI_DDR_MODE;
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else
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regs &= DWMCI_DDR_MODE;
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@ -101,7 +101,7 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
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host->get_mmc_clk = exynos_dwmci_get_clk;
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/* Add the mmc channel to be registered with mmc core */
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if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
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debug("dwmmc%d registration failed\n", index);
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printf("DWMMC%d registration failed\n", index);
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return -1;
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}
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return 0;
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@ -146,7 +146,7 @@ static int do_dwmci_init(struct dwmci_host *host)
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flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
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err = exynos_pinmux_config(host->dev_id, flag);
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if (err) {
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debug("DWMMC not configure\n");
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printf("DWMMC%d not configure\n", index);
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return err;
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}
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@ -162,21 +162,22 @@ static int exynos_dwmci_get_config(const void *blob, int node,
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/* Extract device id for each mmc channel */
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host->dev_id = pinmux_decode_periph_id(blob, node);
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/* Get the bus width from the device node */
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host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
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if (host->buswidth <= 0) {
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debug("DWMMC: Can't get bus-width\n");
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return -EINVAL;
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}
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host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
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if (host->dev_index == host->dev_id)
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host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
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/* Get the bus width from the device node */
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host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
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if (host->buswidth <= 0) {
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printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
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return -EINVAL;
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}
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/* Set the base address from the device node */
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base = fdtdec_get_addr(blob, node, "reg");
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if (!base) {
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debug("DWMMC: Can't get base address\n");
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printf("DWMMC%d: Can't get base address\n", host->dev_index);
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return -EINVAL;
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}
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host->ioaddr = (void *)base;
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@ -184,7 +185,8 @@ static int exynos_dwmci_get_config(const void *blob, int node,
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/* Extract the timing info from the node */
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err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
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if (err) {
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debug("Can't get sdr-timings for devider\n");
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printf("DWMMC%d: Can't get sdr-timings for devider\n",
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host->dev_index);
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return -EINVAL;
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}
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@ -214,7 +216,7 @@ static int exynos_dwmci_process_node(const void *blob,
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host = &dwmci_host[i];
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err = exynos_dwmci_get_config(blob, node, host);
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if (err) {
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debug("%s: failed to decode dev %d\n", __func__, i);
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printf("%s: failed to decode dev %d\n", __func__, i);
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return err;
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}
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@ -159,7 +159,7 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
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{
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struct mmc_cmd cmd;
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if (mmc->card_caps & MMC_MODE_DDR_52MHz)
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if (mmc->ddr_mode)
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return 0;
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cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
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@ -486,7 +486,7 @@ static int mmc_change_freq(struct mmc *mmc)
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char cardtype;
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int err;
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mmc->card_caps = 0;
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mmc->card_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
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if (mmc_host_is_spi(mmc))
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return 0;
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@ -519,7 +519,7 @@ static int mmc_change_freq(struct mmc *mmc)
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/* High Speed is set, there are two types: 52MHz and 26MHz */
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if (cardtype & EXT_CSD_CARD_TYPE_52) {
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if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
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if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
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mmc->card_caps |= MMC_MODE_DDR_52MHz;
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mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
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} else {
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@ -1001,6 +1001,9 @@ static int mmc_startup(struct mmc *mmc)
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case 6:
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mmc->version = MMC_VERSION_4_5;
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break;
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case 7:
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mmc->version = MMC_VERSION_5_0;
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break;
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}
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/*
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@ -1022,6 +1025,21 @@ static int mmc_startup(struct mmc *mmc)
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mmc->erase_grp_size =
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ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
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MMC_MAX_BLOCK_LEN * 1024;
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/*
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* if high capacity and partition setting completed
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* SEC_COUNT is valid even if it is smaller than 2 GiB
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* JEDEC Standard JESD84-B45, 6.2.4
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*/
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if (mmc->high_capacity &&
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(ext_csd[EXT_CSD_PARTITION_SETTING] &
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EXT_CSD_PARTITION_SETTING_COMPLETED)) {
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capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
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(ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
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(ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
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(ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
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capacity *= MMC_MAX_BLOCK_LEN;
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mmc->capacity_user = capacity;
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}
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} else {
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/* Calculate the group size from the csd value. */
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int erase_gsz, erase_gmul;
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@ -1103,8 +1121,10 @@ static int mmc_startup(struct mmc *mmc)
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/* An array to map CSD bus widths to host cap bits */
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static unsigned ext_to_hostcaps[] = {
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[EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
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[EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
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[EXT_CSD_DDR_BUS_WIDTH_4] =
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MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
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[EXT_CSD_DDR_BUS_WIDTH_8] =
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MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
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[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
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[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
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};
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@ -1116,13 +1136,13 @@ static int mmc_startup(struct mmc *mmc)
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for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
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unsigned int extw = ext_csd_bits[idx];
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unsigned int caps = ext_to_hostcaps[extw];
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/*
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* Check to make sure the controller supports
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* this bus width, if it's more than 1
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* Check to make sure the card and controller support
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* these capabilities
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*/
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if (extw != EXT_CSD_BUS_WIDTH_1 &&
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!(mmc->cfg->host_caps & ext_to_hostcaps[extw]))
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if ((mmc->card_caps & caps) != caps)
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continue;
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err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
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@ -1131,26 +1151,33 @@ static int mmc_startup(struct mmc *mmc)
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if (err)
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continue;
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mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
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mmc_set_bus_width(mmc, widths[idx]);
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err = mmc_send_ext_csd(mmc, test_csd);
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/* Only compare read only fields */
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if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
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== test_csd[EXT_CSD_PARTITIONING_SUPPORT]
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&& ext_csd[EXT_CSD_HC_WP_GRP_SIZE] \
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== test_csd[EXT_CSD_HC_WP_GRP_SIZE] \
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&& ext_csd[EXT_CSD_REV] \
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== test_csd[EXT_CSD_REV]
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&& ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \
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== test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
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&& memcmp(&ext_csd[EXT_CSD_SEC_CNT], \
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&test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
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mmc->card_caps |= ext_to_hostcaps[extw];
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if (err)
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continue;
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/* Only compare read only fields */
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if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
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== test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
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ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
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== test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
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ext_csd[EXT_CSD_REV]
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== test_csd[EXT_CSD_REV] &&
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ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
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== test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
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memcmp(&ext_csd[EXT_CSD_SEC_CNT],
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&test_csd[EXT_CSD_SEC_CNT], 4) == 0)
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break;
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}
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else
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err = SWITCH_ERR;
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}
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if (err)
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return err;
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if (mmc->card_caps & MMC_MODE_HS) {
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if (mmc->card_caps & MMC_MODE_HS_52MHz)
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mmc->tran_speed = 52000000;
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@ -1161,6 +1188,12 @@ static int mmc_startup(struct mmc *mmc)
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mmc_set_clock(mmc, mmc->tran_speed);
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/* Fix the block length for DDR mode */
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if (mmc->ddr_mode) {
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mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
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mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
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}
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/* fill in device description */
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mmc->block_dev.lun = 0;
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mmc->block_dev.type = 0;
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@ -1306,6 +1339,7 @@ int mmc_start_init(struct mmc *mmc)
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if (err)
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return err;
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mmc->ddr_mode = 0;
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mmc_set_bus_width(mmc, 1);
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mmc_set_clock(mmc, 1);
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@ -1408,8 +1442,11 @@ void print_mmc_devices(char separator)
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printf("%s: %d", m->cfg->name, m->block_dev.dev);
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if (entry->next != &mmc_devices)
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printf("%c ", separator);
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if (entry->next != &mmc_devices) {
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printf("%c", separator);
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if (separator != '\n')
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puts (" ");
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}
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}
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printf("\n");
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@ -31,6 +31,7 @@
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#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403)
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#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429)
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#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405)
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#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x500)
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#define MMC_MODE_HS (1 << 0)
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#define MMC_MODE_HS_52MHz (1 << 1)
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@ -147,6 +148,7 @@
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* EXT_CSD fields
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*/
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#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
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#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
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#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
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#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
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#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
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@ -197,6 +199,8 @@
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#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
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#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
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#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
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#define R1_ILLEGAL_COMMAND (1 << 22)
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#define R1_APP_CMD (1 << 5)
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@ -314,6 +318,7 @@ struct mmc {
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char init_in_progress; /* 1 if we have done mmc_start_init() */
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char preinit; /* start init as early as possible */
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uint op_cond_response; /* the response byte from the last op_cond */
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int ddr_mode;
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};
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int mmc_register(struct mmc *mmc);
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