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ARM: dts: stm32: Switch to MCO2 for PHY 50 MHz clock
The LAN8710i PHY currently uses 50 MHz clock direct from PLL4P. To permit PLL4P to run at faster frequency, use MCO2 as a divider. The PLL4P runs at 100 MHz, supplies MCO2 which divides it by 2 to 50MHz, and supplies the PHY with 50 MHz via pin PG2. The feedback clock are fed back in via pin PA1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Change-Id: Ia9bf7119785d49b633a3ae761c3dc4a30b92628a
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parent
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commit
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2 changed files with 21 additions and 7 deletions
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@ -72,8 +72,8 @@
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&pinctrl {
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/* These should bound to FMC2 bus driver, but we do not have one */
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pinctrl-0 = <&fmc_pins_b>;
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pinctrl-1 = <&fmc_sleep_pins_b>;
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pinctrl-0 = <&fmc_pins_b &mco2_pins_a>;
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pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>;
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pinctrl-names = "default", "sleep";
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fmc_pins_b: fmc-0 {
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@ -130,6 +130,21 @@
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<STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
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};
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};
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mco2_pins_a: mco2-0 {
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pins {
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pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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mco2_sleep_pins_a: mco2-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
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};
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};
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};
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&pmic {
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@ -181,7 +196,7 @@
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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CLK_MCO2_PLL4P
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>;
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st,clkdiv = <
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@ -195,7 +210,7 @@
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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1 /*MCO2*/
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>;
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st,pkcs = <
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@ -258,7 +273,7 @@
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pll4: st,pll@3 {
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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cfg = < 1 49 11 11 11 PQR(1,1,1) >;
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cfg = < 1 49 5 11 11 PQR(1,1,1) >;
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u-boot,dm-pre-reloc;
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};
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};
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@ -58,7 +58,6 @@
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phy-mode = "rmii";
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max-speed = <100>;
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phy-handle = <&phy0>;
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st,eth_ref_clk_sel;
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phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
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mdio0 {
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@ -267,7 +266,7 @@
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pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
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<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
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<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
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<STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
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<STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
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<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
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<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
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bias-disable;
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