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board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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@ -22,6 +22,9 @@
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09110024 00100008
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09110028 00100008
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0911002c 00100008
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#slowing down the MDC clock to make it <= 2.5 MHZ
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094fc030 00008148
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094fd030 00008148
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#Flush PBL data
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09138000 00000000
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091380c0 00000000
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