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spi: imx: Define register bits in the driver
The CSPI/ECSPI register bits do not differ between newer SoCs, instead of having multiple copies of the same thing for each iMX SoC, define the bits in the driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
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85b1c11989
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7 changed files with 76 additions and 200 deletions
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@ -269,18 +269,6 @@ struct epit_regs {
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u32 cnr; /* Counter register */
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};
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/* CSPI registers */
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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u32 test;
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};
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#endif
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#define ARCH_MXC
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@ -508,24 +496,6 @@ struct cspi_regs {
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/*
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* CSPI register definitions
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*/
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#define MXC_CSPI
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 4
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#define MXC_SPI_BASE_ADDRESSES \
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IMX_CSPI1_BASE, \
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IMX_CSPI2_BASE, \
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@ -39,17 +39,6 @@ struct clock_control_regs {
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u32 pdr2;
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};
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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u32 test;
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};
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/* IIM control registers */
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struct iim_regs {
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u32 iim_stat;
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@ -889,26 +878,6 @@ struct esdc_regs {
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/*
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* CSPI register definitions
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*/
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#define MXC_CSPI
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_TC (1 << 8)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPICTRL_MAXBITS 0x1f
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 4
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#define MXC_SPI_BASE_ADDRESSES \
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0x43fa4000, \
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0x50010000, \
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@ -170,24 +170,6 @@
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/*
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* CSPI register definitions
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*/
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#define MXC_CSPI
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 4
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#define MXC_SPI_BASE_ADDRESSES \
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0x43fa4000, \
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0x50010000,
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@ -280,18 +262,6 @@ struct gpt_regs {
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u32 counter; /* counter */
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};
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/* CSPI registers */
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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u32 test;
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};
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struct esdc_regs {
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u32 esdctl0;
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u32 esdcfg0;
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@ -204,30 +204,6 @@
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/*
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* CSPI register definitions
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*/
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#define MXC_ECSPI
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
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#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
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#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 32
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/* Bit position inside CTRL register to be associated with SS */
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#define MXC_CSPICTRL_CHAN 18
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/* Bit position inside CON register to be associated with SS */
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#define MXC_CSPICON_PHA 0 /* SCLK phase control */
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#define MXC_CSPICON_POL 4 /* SCLK polarity */
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#define MXC_CSPICON_SSPOL 12 /* SS polarity */
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#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
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#define MXC_SPI_BASE_ADDRESSES \
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CSPI1_BASE_ADDR, \
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CSPI2_BASE_ADDR, \
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@ -476,18 +452,6 @@ struct srtc_regs {
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u32 hpienr; /* 0x38 */
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};
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/* CSPI registers */
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 cfg;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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};
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struct iim_regs {
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u32 stat;
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u32 statm;
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@ -668,46 +668,10 @@ struct gpc {
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#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
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#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
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/* ECSPI registers */
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 cfg;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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};
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/*
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* CSPI register definitions
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*/
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#define MXC_ECSPI
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
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#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
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#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 32
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#define SPI_MAX_NUM 4
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/* Bit position inside CTRL register to be associated with SS */
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#define MXC_CSPICTRL_CHAN 18
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/* Bit position inside CON register to be associated with SS */
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#define MXC_CSPICON_PHA 0 /* SCLK phase control */
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#define MXC_CSPICON_POL 4 /* SCLK polarity */
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#define MXC_CSPICON_SSPOL 12 /* SS polarity */
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#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
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#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
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defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
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#define MXC_SPI_BASE_ADDRESSES \
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@ -842,46 +842,9 @@ struct iomuxc_gpr_base_regs {
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u32 gpr[23]; /* 0x000 */
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};
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/* ECSPI registers */
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 cfg;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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};
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/*
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* CSPI register definitions
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*/
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#define MXC_ECSPI
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
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#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
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#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 32
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/* Bit position inside CTRL register to be associated with SS */
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#define MXC_CSPICTRL_CHAN 18
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/* Bit position inside CON register to be associated with SS */
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#define MXC_CSPICON_PHA 0 /* SCLK phase control */
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#define MXC_CSPICON_POL 4 /* SCLK polarity */
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#define MXC_CSPICON_SSPOL 12 /* SS polarity */
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#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
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#define MXC_SPI_BASE_ADDRESSES \
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ECSPI1_BASE_ADDR, \
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ECSPI2_BASE_ADDR, \
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@ -20,6 +20,82 @@
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DECLARE_GLOBAL_DATA_PTR;
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/* MX35 and older is CSPI */
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#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35)
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#define MXC_CSPI
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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u32 test;
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};
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#define MXC_CSPICTRL_EN BIT(0)
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#define MXC_CSPICTRL_MODE BIT(1)
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#define MXC_CSPICTRL_XCH BIT(2)
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#define MXC_CSPICTRL_SMC BIT(3)
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#define MXC_CSPICTRL_POL BIT(4)
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#define MXC_CSPICTRL_PHA BIT(5)
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#define MXC_CSPICTRL_SSCTL BIT(6)
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#define MXC_CSPICTRL_SSPOL BIT(7)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_RXOVF BIT(6)
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#define MXC_CSPIPERIOD_32KHZ BIT(15)
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#define MAX_SPI_BYTES 4
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#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_TC BIT(7)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#else /* MX31 */
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
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#define MXC_CSPICTRL_TC BIT(8)
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#define MXC_CSPICTRL_MAXBITS 0x1f
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#endif
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#else /* MX51 and newer is ECSPI */
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#define MXC_ECSPI
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 cfg;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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};
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#define MXC_CSPICTRL_EN BIT(0)
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#define MXC_CSPICTRL_MODE BIT(1)
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#define MXC_CSPICTRL_XCH BIT(2)
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#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
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#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
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#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPICTRL_TC BIT(7)
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#define MXC_CSPICTRL_RXOVF BIT(6)
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#define MXC_CSPIPERIOD_32KHZ BIT(15)
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#define MAX_SPI_BYTES 32
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/* Bit position inside CTRL register to be associated with SS */
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#define MXC_CSPICTRL_CHAN 18
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/* Bit position inside CON register to be associated with SS */
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#define MXC_CSPICON_PHA 0 /* SCLK phase control */
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#define MXC_CSPICON_POL 4 /* SCLK polarity */
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#define MXC_CSPICON_SSPOL 12 /* SS polarity */
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#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
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#endif
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#ifdef CONFIG_MX27
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/* i.MX27 has a completely wrong register layout and register definitions in the
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* datasheet, the correct one is in the Freescale's Linux driver */
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