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starfive: Add JH7100 support

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This patch adds StarFive JH7100 main support, including Starlight and EVB
support, ported from StarFive HiFive_U-Boot REPO.

    The original authors are
    Bo Li <bo.li@starfivetech.com>
    JieQin Chen <Jessica.Chen@starfivetech.com>
    Huan Feng <huan.feng@starfivetech.com>
    Jack Zhu <jack.zhu@starfivetech.com>
    Jianlong Huang <jianlong.huang@starfivetech.com>
    Ke Zhu <ke.zhu@starfivetech.com>
    Micheal Zhu <michael.zhu@starfivetech.com>
    Samin Guo <samin.guo@starfivetech.com>
    Yanhong Wang <yanhong.wang@starfivetech.com>
    Yiming Li <yiming.li@starfivetech.com>

Note:
    1, disable BTRFS(will trigger a link error with *some* RV64 GCC)
    But RV64 GCC on Fedora works well with enabling BTRFS.

    BTRFS will select ZSTD which will trigger a link error with
    *some* RV64 GCC:
    ---
    riscv64-unknown-linux-gnu-ld.bfd: /usr/lib/gcc/riscv64-unknown-linux-gnu/11.2.0/libgcc.a(_clzsi2.o): can't link double-float modules with soft-float modules
    riscv64-unknown-linux-gnu-ld.bfd: failed to merge target specific data of file /usr/lib/gcc/riscv64-unknown-linux-gnu/11.2.0/libgcc.a(_clzsi2.o)
    riscv64-unknown-linux-gnu-ld.bfd: /usr/lib/gcc/riscv64-unknown-linux-gnu/11.2.0/libgcc.a(_clz.o): can't link double-float modules with soft-float modules
    riscv64-unknown-linux-gnu-ld.bfd: failed to merge target specific data of file /usr/lib/gcc/riscv64-unknown-linux-gnu/11.2.0/libgcc.a(_clz.o)
    make: *** [Makefile:1787: u-boot] Error 1
    ---

    2, enable OF_SEPARATE:
    This is required so that openSBI can add itself to /reserved-memory, and
    let EFI know about it.

    By Andreas Schwab <schwab@suse.de>

    3, Set default fdtfile name

    By Andreas Schwab <schwab@suse.de>
This commit is contained in:
Micheal Zhu 2021-08-16 20:20:01 +08:00 • committed by Tekkaman Ninja
parent 4954df51e4
commit 6d3fbb8c00
16 changed files with 2354 additions and 0 deletions

22
arch/riscv/Kconfig
View file

@ -24,6 +24,10 @@ config TARGET_SIFIVE_UNMATCHED
bool "Support SiFive Unmatched Board"
select SYS_CACHE_SHIFT_6
config TARGET_STARFIVE_JH7100
bool "Support StarFive development Boards based on JH7100 Soc"
select SYS_CACHE_SHIFT_6
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
select SYS_CACHE_SHIFT_6
@ -33,6 +37,23 @@ config TARGET_OPENPITON_RISCV64
endchoice
choice
prompt "JH7100 Soc development Board variants"
default JH_STARLIGHT
depends on TARGET_STARFIVE_JH7100
optional
config JH_VISIONFIVE_V1
bool "Support JH7100 VisionFive-V1."
config JH_STARLIGHT
bool "Support JH7100 Starlight Board."
config JH_EVB_V1
bool "Support JH7100 EVB-V1."
endchoice
config SYS_ICACHE_OFF
bool "Do not enable icache"
help
@ -63,6 +84,7 @@ source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
source "board/starfive/jh7100/Kconfig"
source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"

4
arch/riscv/dts/Makefile
View file

@ -7,6 +7,10 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
ifeq ($(CONFIG_TARGET_STARFIVE_JH7100),y)
dtb-$(CONFIG_JH_EVB_V1) += starfive_jh7100_evb.dtb
dtb-$(CONFIG_JH_STARLIGHT) += starfive_jh7100_starlight.dtb
endif
include $(srctree)/scripts/Makefile.dts

108
arch/riscv/dts/adv7513_1080p.dtsi Executable file
View file

@ -0,0 +1,108 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
#include <dt-bindings/starfive_fb.h>
&sfivefb {
adv_7513_1080p {
compatible = "starfive,display-dev";
panel_name = "adv_7513_1080p";
panel_lcd_id = <22>; /*1080p*/
interface_info = "mipi_interface";
refresh_en = <1>;
bits-per-pixel = <16>;
physical-width = <62>;
physical-height = <114>;
panel-width = <1920>;
panel-height = <1080>;
pixel-clock = <78000000>;
/*dyn_fps;*/ /*dynamic frame rate support*/
/*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/
/*gamma-command-monolithic;*/
/*ce-command-monolithic;*/
/*resume-with-gamma;*/
/*resume-with-ce;*/
/*mipi info*/
mipi-byte-clock = <78000>;
mipi-escape-clock = <13000>;
lane-no = <4>;
display_mode = "video_mode"; /*video_mode, command_mode*/
/*
auto_stop_clklane_en;
im_pin_val;*/
color_bits = <COLOR_CODE_24BIT>;
/*is_18bit_loosely;*/
/*video mode info*/
h-pulse-width = <40>;
h-back-porch = <220>;
h-front-porch = <110>;
v-pulse-width = <5>;
v-back-porch = <20>;
v-front-porch = <5>;
status = "okay";
sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/
lp_cmd_en;
/*lp_hfp_en;*/
/*lp_hbp_en;*/
/*lp_vact_en;*/
lp_vfp_en;
lp_vbp_en;
lp_vsa_en;
traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/
/*phy info*/
data_tprepare = /bits/ 8 <0>;
data_hs_zero = /bits/ 8 <0>;
data_hs_exit = /bits/ 8 <0>;
data_hs_trail = /bits/ 8 <0>;
/*te info*/
te_source = "external_pin"; /*external_pin, dsi_te_trigger*/
te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/
te_enable = <0>;
cm_te_effect_sync_enable = <0>; /*used in command mode*/
te_count_per_sec = <64>; /*used in esd*/
/*ext info*/
/*
crc_rx_en;
ecc_rx_en;
eotp_rx_en;
*/
eotp_tx_en;
dev_read_time = <0x7FFF>;
/*type cmd return_count return_code*/
/*id_read_cmd_info = [];*/
/*pre_id_cmd = [];*/
/*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/
/*pre_esd_cmd = [];*/
/*panel-on-command = [];*/
/*panel-off-command = [];*/
/*reset-sequence = <1 5>, <0 10>, <1 30>;*/
/*
panel-gamma-warm-command = [
];
panel-gamma-nature-command = [
];
panel-gamma-cool-command = [
];
panel-ce-std-command = [
];
panel-ce-vivid-command = [
];
*/
};
};

122
arch/riscv/dts/seeed5inch.dtsi Executable file
View file

@ -0,0 +1,122 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
#include <dt-bindings/starfive_fb.h>
&sfivefb {
seeed_5_inch {
compatible = "starfive,display-dev";
panel_name = "seeed_5_inch";
panel_lcd_id = <22>; /*480p*/
interface_info = "mipi_interface";
refresh_en = <1>;
bits-per-pixel = <24>;
physical-width = <62>;
physical-height = <114>;
panel-width = <800>;
panel-height = <480>;
pixel-clock = <27500000>;
/*dyn_fps;*/ /*dynamic frame rate support*/
fps = <50>;
/*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/
/*gamma-command-monolithic;*/
/*ce-command-monolithic;*/
/*resume-with-gamma;*/
/*resume-with-ce;*/
/*mipi info*/
mipi-byte-clock = <78000>;
mipi-escape-clock = <13000>;
lane-no = <1>;
display_mode = "video_mode"; /*video_mode, command_mode*/
/*
auto_stop_clklane_en;
im_pin_val;
*/
color_bits = <COLOR_CODE_24BIT>;
/*is_18bit_loosely;*/
/*video mode info*/
h-pulse-width = <10>;
h-back-porch = <20>;
h-front-porch = <50>;
v-pulse-width = <5>;
v-back-porch = <5>;
v-front-porch = <135>;
/*seeed panel mode info*/
dphy_bps = <700000000>;
dsi_burst_mode = <0>;
dsi_sync_pulse = <1>;
// bytes
dsi_hsa = <30>;
dsi_hbp = <211>;
dsi_hfp = <159>;
// lines
dsi_vsa = <5>;
dsi_vbp = <5>;
dsi_vfp = <134>;
status = "okay";
sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/
lp_cmd_en;
/*lp_hfp_en;*/
/*lp_hbp_en;*/
/*lp_vact_en;*/
lp_vfp_en;
lp_vbp_en;
lp_vsa_en;
traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/
/*phy info*/
data_tprepare = /bits/ 8 <0>;
data_hs_zero = /bits/ 8 <0>;
data_hs_exit = /bits/ 8 <0>;
data_hs_trail = /bits/ 8 <0>;
/*te info*/
te_source = "external_pin"; /*external_pin, dsi_te_trigger*/
te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/
te_enable = <0>;
cm_te_effect_sync_enable = <0>; /*used in command mode*/
te_count_per_sec = <64>; /*used in esd*/
/*ext info*/
/*
crc_rx_en;
ecc_rx_en;
eotp_rx_en;
*/
eotp_tx_en;
dev_read_time = <0x7FFF>;
/*type cmd return_count return_code*/
/*id_read_cmd_info = [];*/
/*pre_id_cmd = [];*/
/*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/
/*pre_esd_cmd = [];*/
/*panel-on-command = [];*/
/*panel-off-command = [];*/
/*reset-sequence = <1 5>, <0 10>, <1 30>;*/
/*
panel-gamma-warm-command = [
];
panel-gamma-nature-command = [
];
panel-gamma-cool-command = [
];
panel-ce-std-command = [
];
panel-ce-vivid-command = [
];
*/
};
};

112
arch/riscv/dts/starfive_jh7100_clk.dtsi Normal file
View file

@ -0,0 +1,112 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
/ {
hfclk: hfclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "hfclk";
};
rtcclk: rtcclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <6250000>;
clock-output-names = "rtcclk";
};
i2c0clk: i2c0clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <49500000>;
clock-output-names = "i2c0clk";
};
i2c2clk: i2c2clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "i2c2clk";
};
axiclk: axiclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <500000000>;
clock-output-names = "axiclk";
};
ahb0clk: ahb0clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <250000000>;
};
ahb2clk: ahb2clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
};
apb1clk: apb1clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
};
apb2clk: apb2clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
};
jpuclk: jpuclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <333333333>;
};
vpuclk: vpuclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <400000000>;
};
gmacclk: gmacclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
qspi_clk: qspi-clk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
uartclk: uartclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
hs_uartclk: hs_uartclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <74250000>;
};
dwmmc_biuclk: dwmmc_biuclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
/*
dwmmc_ciuclk: dwmmc_ciuclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
*/
spiclk: spiclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
pwmclk: pwmclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
};
};

609
arch/riscv/dts/starfive_jh7100_evb.dts Normal file
View file

@ -0,0 +1,609 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
/dts-v1/;
#include "starfive_jh7100_clk.dtsi"
#include <dt-bindings/starfive_fb.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "sifive,freedom-u74-arty";
model = "sifive,freedom-u74-arty";
chosen {
linux,initrd-start = <0x0 0x86100000>;
linux,initrd-end = <0x0 0x8c000000>;
stdout-path = "/soc/serial@12440000:115200";
#bootargs = "debug console=ttyS0 rootwait";
};
aliases {
spi0="/soc/qspi@11860000";
mshc0="/soc/sdio0@10000000";
usb0="/soc/usb@104c0000";
};
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <6250000>;
compatible = "starfive,fu74-g000";
cpu@0 {
clock-frequency = <0>;
compatible = "starfive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
reg = <0>;
riscv,isa = "rv64imafdc";
starfive,itim = <&itim0>;
status = "okay";
tlb-split;
cpu0intctrl: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@1 {
clock-frequency = <0>;
compatible = "starfive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
reg = <1>;
riscv,isa = "rv64imafdc";
starfive,itim = <&itim1>;
status = "okay";
tlb-split;
cpu1intctrl: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x2 0x0>;
};
memory@3000000000 {
device_type = "memory";
reg = <0x30 0x0 0x0 0x0>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x28000000>;
alignment = <0x0 0x1000>;
alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
linux,cma-default;
};
jpu_reserved: framebuffer@c9000000 {
reg = <0x0 0xc9000000 0x0 0x2000000>;
};
nne_reserved: nne@cb000000 {
reg = <0x0 0xcb000000 0x0 0x5000000>;
};
nvdla_reserved:framebuffer@d0000000{
reg = <0x0 0xd0000000 0x0 0x28000000>;
};
vin_reserved: framebuffer@f9000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0xf9000000 0x0 0x1000000>;
};
sffb_reserved: framebuffer@fb000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0xfb000000 0x0 0x2000000>;
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
#clock-cells = <1>;
compatible = "starfive,freedom-u74-arty", "simple-bus";
ranges;
cachectrl: cache-controller@2010000 {
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <2097152>;
cache-unified;
compatible = "sifive,fu740-c000-ccache", "starfive,ccache0", "cache";
interrupt-parent = <&plic>;
interrupts = <128 131 129 130>;
/*next-level-cache = <&L40 &L36>;*/
reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
reg-names = "control", "sideband";
};
dtim: dtim@1000000 {
compatible = "starfive,dtim0";
reg = <0x0 0x1000000 0x0 0x2000>;
reg-names = "mem";
};
itim0: itim@1808000 {
compatible = "starfive,itim0";
reg = <0x0 0x1808000 0x0 0x8000>;
reg-names = "mem";
};
itim1: itim@1820000 {
compatible = "starfive,itim0";
reg = <0x0 0x1820000 0x0 0x8000>;
reg-names = "mem";
};
clint: clint@2000000 {
#interrupt-cells = <1>;
compatible = "riscv,clint0";
interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7 >;
reg = <0x0 0x2000000 0x0 0x10000>;
reg-names = "control";
};
plic: plic@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9 &cpu1intctrl 11 &cpu1intctrl 9 >;
reg = <0x0 0xc000000 0x0 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <127>;
};
uart3: serial@12440000 {
compatible = "snps,dw-apb-uart", "starfive,uart0";
interrupt-parent = <&plic>;
interrupts = <73>;
reg = <0x0 0x12440000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&uartclk>, <&apb2clk>;
clock-names = "baudclk", "apb_pclk";
current-clock = <100000000>;
current-speed = <115200>;
status = "okay";
};
uart2: serial@12430000 {
compatible = "snps,dw-apb-uart";
interrupt-parent = <&plic>;
interrupts = <72>;
reg = <0x0 0x12430000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&uartclk>, <&apb2clk>;
clock-names = "baudclk", "apb_pclk";
current-clock = <100000000>;
current-speed = <115200>;
status = "disabled";
};
uart1: hs_serial@11880000 {
compatible = "snps,dw-apb-uart";
interrupt-parent = <&plic>;
interrupts = <93>;
reg = <0x0 0x11880000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&hs_uartclk>, <&apb1clk>;
clock-names = "baudclk","apb_pclk";
current-clock = <74250000>;
current-speed = <115200>;
status = "okay";
};
uart0: hs_serial@11870000 {
compatible = "snps,dw-apb-uart";
interrupt-parent = <&plic>;
interrupts = <92>;
reg = <0x0 0x11870000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&hs_uartclk>, <&apb1clk>;
clock-names = "baudclk", "apb_pclk";
current-clock = <74250000>;
current-speed = <115200>;
status = "okay";
};
dma2p: sgdma2p@100b0000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x0 0x100b0000 0x0 0x10000>;
clocks = <&axiclk>,<&ahb0clk>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&plic>;
interrupts = <2>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <4>;
snps,block-size = <4096 4096 4096 4096>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <128>;
status = "okay";
};
dma1p: sgdma1p@10500000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x0 0x10500000 0x0 0x10000>;
clocks = <&axiclk>,<&ahb0clk>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&plic>;
interrupts = <1>;
dma-channels = <16>;
snps,dma-masters = <1>;
snps,data-width = <3>;
snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
snps,axi-max-burst-len = <64>;
status = "okay";
};
USB30: usb@104c0000 {
compatible = "cdns,usb3";
reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
<0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
<0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
reg-names = "otg", "xhci", "dev";
interrupt-parent = <&plic>;
interrupts = <43>, <44>, <52>;
interrupt-names = "otg",
"host",
"peripheral";
phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
status = "okay";
};
gpio: gpio@11910000 {
compatible = "starfive,gpio0";
interrupt-parent = <&plic>;
interrupts = <32>;
reg = <0x0 0x11910000 0x0 0x10000>;
reg-names = "control";
interrupt-controller;
#gpio-cells = <2>;
};
i2c0: i2c@118b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x118b0000 0x0 0x10000>;
interrupt-parent = <&plic>;
interrupts = <96>;
clocks = <49500000>;
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <500>;
i2c-scl-falling-time-ns = <500>;
auto_calc_scl_lhcnt;
scl-gpio = <&gpio 16 0>;
sda-gpio = <&gpio 17 0>;
ov5640: ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
mclk = <24000000>;
mclk_source = <0>;
};
sc2235@30 {
compatible = "sc2235";
reg = <0x30>;
};
};
i2c1: i2c@118c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x118c0000 0x0 0x10000>;
interrupt-parent = <&plic>;
interrupts = <97>;
clocks = <49500000>;
clock-frequency = <400000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <500>;
i2c-scl-falling-time-ns = <500>;
auto_calc_scl_lhcnt;
scl-gpio = <&gpio 18 0>;
sda-gpio = <&gpio 19 0>;
adv7513@39 {
compatible = "adv7513";
reg = <0x39>;
def-width = <1920>;
};
};
trng: trng@118d0000 {
compatible = "starfive,jh-rng";
reg = <0x0 0x118d0000 0x0 0x10000>;
interrupt-parent = <&plic>;
interrupts = <98>;
clocks = <&hfclk>;
};
crypto: crypto@100d0000 {
compatible = "starfive,jh-sec";
reg = <0x0 0x100d0000 0x0 0x20000>,
<0x0 0x11800234 0x0 0xc>;
reg-names = "secmem","secclk";
interrupt-parent = <&plic>;
interrupts = <31>;
clocks = <&hfclk>;
};
/*gmac device configuration*/
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
snps,blen = <256 128 64 32 0 0 0>;
};
gmac:gmac@10020000{
compatible = "snps,dwmac";
reg = <0x0 0x10020000 0x0 0x10000>;
interrupt-parent = <&plic>;
interrupts = <6 7>;
interrupt-names = "macirq","eth_wake_irq";
max-frame-size = <9000>;
phy-mode = "rgmii-txid";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
rx-fifo-depth = <32768>;
tx-fifo-depth = <16384>;
clocks = <&gmacclk>;
clock-names = "stmmaceth";
snps,fixed-burst = <1>;
snps,no-pbl-x8 = <1>;
/*snps,force_sf_dma_mode;*/
snps,force_thresh_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
};
nbdla: nvdla@0x11940000 {
compatible = "nvidia,nvdla_os_initial";
interrupt-parent = <&plic>;
interrupts = <22>;
memory-region = <&nvdla_reserved>;
reg = <0x0 0x11940000 0x0 0x40000>;
status = "okay";
};
jpu:coadj12@11900000 {
compatible = "cm,codaj12-jpu-1";
reg = <0x0 0x11900000 0x0 0x300>;
memory-region = <&jpu_reserved>;
interrupt-parent = <&plic>;
interrupts = <24>;
clocks = <&jpuclk>;
clock-names = "jpege";
reg-names = "control";
status = "okay";
};
vpu_dec:vpu_dec@118F0000 {
compatible = "c&m,cm511-vpu";
reg = <0 0x118F0000 0 0x10000>;
//memory-region = <&vpu_reserved>;
interrupt-parent = <&plic>;
interrupts = <23>;
clocks = <&vpuclk>;
clock-names = "vcodec";
status = "okay";
};
vpu_enc:vpu_enc@118E0000 {
compatible = "cm,cm521-vpu";
reg = <0x0 0x118E0000 0x0 0x4000>;
interrupt-parent = <&plic>;
interrupts = <26>;
clocks = <&vpuclk>;
clock-names = "vcodec";
reg-names = "control";
};
ptc: pwm@12490000 {
compatible = "sifive,pwm0";
reg = <0x0 0x12490000 0x0 0x10000>;
reg-names = "control";
sifive,approx-period = <100000000>;
#pwm-cells=<3>;
sifive,npwm = <8>;
};
qspi:qspi@11860000 {
compatible = "cadence,qspi","cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x11860000 0x0 0x10000 0x0 0x20000000 0x0 0x20000000 >;
interrupts = <3>;
interrupt-parent = <&plic>;
clocks = <&qspi_clk>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
status = "okay";
spi-max-frequency = <250000000>;
nor_flash:nor-flash@0 {
compatible = "spi-flash";
reg=<0>;
spi-max-frequency = <31250000>;
page-size = <256>;
block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <1>;
cdns,tsd2d-ns = <1>;
cdns,tchsh-ns = <1>;
cdns,tslch-ns = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
nand_flash:nand-flash@1 {
compatible = "spi-flash-nand";
reg=<1>;
spi-max-frequency = <31250000>;
page-size = <2048>;
block-size = <17>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <1>;
cdns,tsd2d-ns = <1>;
cdns,tchsh-ns = <1>;
cdns,tslch-ns = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
spi2:spi2@12410000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <70>;
reg = <0x0 0x12410000 0x0 0x10000>;
clocks = <&spiclk>;
/*num-cs = <1>;
cs-gpios = <&gpio 0 0>;*/
spi_dev0: spi@0 {
compatible = "rohm,dh2228fv";
spi-max-frequency = <10000000>;
reg = <0>;
status = "okay";
};
};
xrp@0 {
compatible = "cdns,xrp";
reg = <0x0 0xf0000000 0x0 0x01ffffff
0x10 0x72000000 0x0 0x00001000
0x10 0x72001000 0x0 0x00fff000
0x0 0x124b0000 0x0 0x00010000>;
clocks = <&hfclk>;
interrupt-parent = <&plic>;
firmware-name = "vp6_elf";
dsp-irq = <19 20>;
dsp-irq-src = <0x20 0x21>;
intc-irq-mode = <1>;
intc-irq = <0 1>;
interrupts = <27 28>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x40000000 0x0 0x40000000 0x01000000
0xb0000000 0x10 0x70000000 0x3000000>;
dsp@0 {
};
};
sdio0:sdio0@10000000{
compatible = "snps,dw-mshc";
reg = <0x0 0x10000000 0x0 0x10000>;
interrupts = <4>;
interrupt-parent = <&plic>;
clocks = <&dwmmc_biuclk>;
clock-names = "biu";
clock-frequency = <100000000>;
max-frequency = <10000000>;
fifo-depth = <32>;
card-detect-delay = <300>;
fifo-watermark-aligned;
data-addr = <0>;
bus-width = <4>;
cap-sd-highspeed;
broken-cd;
no-sdio;
post-power-on-delay-ms = <200>;
};
nne@0 {
compatible = "starfive,nne_50";
reg = <0x0 0x19600000 0x0 0x00200000
0x0 0x10800000 0x0 0x00001000
0x10 0x4b000000 0x0 0x5000000>;
clocks = <&hfclk>;
memory-region = <&nne_reserved>;
interrupt-parent = <&plic>;
interrupts = <69>;
intc-irq-mode = <1>;
};
sfivefb:sfivefb@12000000 {
compatible = "starfive,vpp-lcdc";
interrupt-parent = <&plic>;
interrupts = <101>, <103>;
interrupt-names = "lcdc_irq", "vpp1_irq";
reg = <0x0 0x12000000 0x0 0x10000>,
<0x0 0x12040000 0x0 0x10000>,
<0x0 0x12080000 0x0 0x10000>,
<0x0 0x120c0000 0x0 0x10000>,
<0x0 0x12240000 0x0 0x10000>,
<0x0 0x12250000 0x0 0x10000>,
<0x0 0x12260000 0x0 0x10000>;
reg-names = "lcdc", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
memory-region = <&sffb_reserved>;
clocks = <&uartclk>, <&apb2clk>;
clock-names = "baudclk", "apb_pclk";
status = "okay";
pp1 {
pp-id = <1>;
fifo-out;
src-format = <COLOR_RGB565>;
src-width = <1920>;
src-height = <1080>;
dst-format = <COLOR_RGB888_ARGB>;
dst-width = <1920>;
dst-height = <1080>;
};
};
vin_sysctl:vin_sysctl@19800000 {
compatible = "starfive,stf-vin";
reg = <0x0 0x19800000 0x0 0x4ffff>;
interrupt-parent = <&plic>;
interrupts = <119 109>;
memory-region = <&vin_reserved>;
};
sfc_tmp:tmpsensor@124A0000 {
compatible = "sfc,tempsensor";
reg = <0x0 0x124A0000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <122>;
status = "okay";
};
};
};
#include "adv7513_1080p.dtsi"

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arch/riscv/dts/starfive_jh7100_starlight.dts Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
/dts-v1/;
#include "starfive_jh7100_clk.dtsi"
#include <dt-bindings/starfive_fb.h>
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "sifive,freedom-u74-arty";
model = "sifive,freedom-u74-arty";
chosen {
linux,initrd-start = <0x0 0x86100000>;
linux,initrd-end = <0x0 0x8c000000>;
stdout-path = "/soc/serial@12440000:115200";
#bootargs = "debug console=ttyS0 rootwait";
};
aliases {
spi0="/soc/qspi@11860000";
mshc0="/soc/sdio0@10000000";
mshc1="/soc/sdio1@10010000";
usb0="/soc/usb@104c0000";
};
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <6250000>;
compatible = "starfive,fu74-g000";
cpu@0 {
clock-frequency = <0>;
compatible = "starfive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
reg = <0>;
riscv,isa = "rv64imafdc";
starfive,itim = <&itim0>;
status = "okay";
tlb-split;
cpu0intctrl: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@1 {
clock-frequency = <0>;
compatible = "starfive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
reg = <1>;
riscv,isa = "rv64imafdc";
starfive,itim = <&itim1>;
status = "okay";
tlb-split;
cpu1intctrl: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x2 0x0>;
};
memory@3000000000 {
device_type = "memory";
reg = <0x30 0x0 0x0 0x0>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x28000000>;
alignment = <0x0 0x1000>;
alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
linux,cma-default;
};
jpu_reserved: framebuffer@c9000000 {
reg = <0x0 0xc9000000 0x0 0x4000000>;
};
nvdla_reserved:framebuffer@d0000000{
reg = <0x0 0xd0000000 0x0 0x28000000>;
};
vin_reserved: framebuffer@f9000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0xf9000000 0x0 0x1000000>;
};
sffb_reserved: framebuffer@fb000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0xfb000000 0x0 0x2000000>;
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
#clock-cells = <1>;
compatible = "starfive,freedom-u74-arty", "simple-bus";
ranges;
cachectrl: cache-controller@2010000 {
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <2097152>;
cache-unified;
compatible = "sifive,fu740-c000-ccache", "starfive,ccache0", "cache";
interrupt-parent = <&plic>;
interrupts = <128 131 129 130>;
/*next-level-cache = <&L40 &L36>;*/
reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
reg-names = "control", "sideband";
};
dtim: dtim@1000000 {
compatible = "starfive,dtim0";
reg = <0x0 0x1000000 0x0 0x2000>;
reg-names = "mem";
};
itim0: itim@1808000 {
compatible = "starfive,itim0";
reg = <0x0 0x1808000 0x0 0x8000>;
reg-names = "mem";
};
itim1: itim@1820000 {
compatible = "starfive,itim0";
reg = <0x0 0x1820000 0x0 0x8000>;
reg-names = "mem";
};
clint: clint@2000000 {
#interrupt-cells = <1>;
compatible = "riscv,clint0";
interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7 >;
reg = <0x0 0x2000000 0x0 0x10000>;
reg-names = "control";
};
plic: plic@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9 &cpu1intctrl 11 &cpu1intctrl 9 >;
reg = <0x0 0xc000000 0x0 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <127>;
};
uart3: serial@12440000 {
compatible = "snps,dw-apb-uart", "starfive,uart0";
interrupt-parent = <&plic>;
interrupts = <73>;
reg = <0x0 0x12440000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&uartclk>, <&apb2clk>;
clock-names = "baudclk", "apb_pclk";
current-clock = <100000000>;
current-speed = <115200>;
status = "okay";
};
uart2: serial@12430000 {
compatible = "snps,dw-apb-uart";
interrupt-parent = <&plic>;
interrupts = <72>;
reg = <0x0 0x12430000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&uartclk>, <&apb2clk>;
clock-names = "baudclk", "apb_pclk";
current-clock = <100000000>;
current-speed = <115200>;
status = "disabled";
};
uart1: hs_serial@11880000 {
compatible = "snps,dw-apb-uart";
interrupt-parent = <&plic>;
interrupts = <93>;
reg = <0x0 0x11880000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&hs_uartclk>, <&apb1clk>;
clock-names = "baudclk","apb_pclk";
current-clock = <74250000>;
current-speed = <115200>;
status = "disabled";
};
uart0: hs_serial@11870000 {
compatible = "snps,dw-apb-uart";
interrupt-parent = <&plic>;
interrupts = <92>;
reg = <0x0 0x11870000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&hs_uartclk>, <&apb1clk>;
clock-names = "baudclk", "apb_pclk";
current-clock = <74250000>;
current-speed = <115200>;
status = "okay";
};
dma2p: sgdma2p@100b0000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x0 0x100b0000 0x0 0x10000>;
clocks = <&axiclk>,<&ahb0clk>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&plic>;
interrupts = <2>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <4>;
snps,block-size = <4096 4096 4096 4096>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <128>;
status = "okay";
};
dma1p: sgdma1p@10500000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x0 0x10500000 0x0 0x10000>;
clocks = <&axiclk>,<&ahb0clk>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&plic>;
interrupts = <1>;
dma-channels = <16>;
snps,dma-masters = <1>;
snps,data-width = <3>;
snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
snps,axi-max-burst-len = <64>;
status = "okay";
};
USB30: usb@104c0000 {
compatible = "cdns,usb3";
reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
<0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
<0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
reg-names = "otg", "xhci", "dev";
interrupt-parent = <&plic>;
interrupts = <43>, <44>, <52>;
interrupt-names = "otg",
"host",
"peripheral";
phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
status = "okay";
};
gpio: gpio@11910000 {
compatible = "starfive,gpio0";
interrupt-parent = <&plic>;
interrupts = <32>;
reg = <0x0 0x11910000 0x0 0x10000>;
reg-names = "control";
interrupt-controller;
#gpio-cells = <2>;
};
i2c0: i2c@118b0000 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x118b0000 0x0 0x10000>;
interrupt-parent = <&plic>;
interrupts = <96>;
clocks = <49500000>;
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <500>;
i2c-scl-falling-time-ns = <500>;
scl-gpio = <&gpio 62 0>;
sda-gpio = <&gpio 61 0>;
tda998x@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
};
imx219@10 {
compatible = "imx219";
reg = <0x10>;
reset-gpio = <&gpio 58 0>;
};
};
i2c1: i2c@118c0000 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x118c0000 0x0 0x10000>;
interrupt-parent = <&plic>;
interrupts = <97>;
clocks = <49500000>;
clock-frequency = <400000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <100>;
i2c-scl-falling-time-ns = <100>;
scl-gpio = <&gpio 47 0>;
sda-gpio = <&gpio 48 0>;
};
i2c2: i2c@12450000 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x12450000 0x0 0x10000>;
interrupt-parent = <&plic>;
interrupts = <74>;
clocks = <50000000>;
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <500>;
i2c-scl-falling-time-ns = <500>;
scl-gpio = <&gpio 60 0>;
sda-gpio = <&gpio 59 0>;
seeed_plane_i2c@45 {
compatible = "seeed_panel";
reg = <0x45>;
};
};
trng: trng@118d0000 {
compatible = "starfive,jh-rng";
reg = <0x0 0x118d0000 0x0 0x10000>;
interrupt-parent = <&plic>;
interrupts = <98>;
clocks = <&hfclk>;
};
crypto: crypto@100d0000 {
compatible = "starfive,jh-sec";
reg = <0x0 0x100d0000 0x0 0x20000>,
<0x0 0x11800234 0x0 0xc>;
reg-names = "secmem","secclk";
interrupt-parent = <&plic>;
interrupts = <31>;
clocks = <&hfclk>;
};
/*gmac device configuration*/
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
snps,blen = <256 128 64 32 0 0 0>;
};
gmac:gmac@10020000{
compatible = "snps,dwmac";
reg = <0x0 0x10020000 0x0 0x10000>;
interrupt-parent = <&plic>;
interrupts = <6 7>;
interrupt-names = "macirq","eth_wake_irq";
max-frame-size = <9000>;
phy-mode = "rgmii-txid";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
rx-fifo-depth = <32768>;
tx-fifo-depth = <16384>;
clocks = <&gmacclk>;
clock-names = "stmmaceth";
snps,fixed-burst = <1>;
snps,no-pbl-x8 = <1>;
/*snps,force_sf_dma_mode;*/
snps,force_thresh_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
};
nbdla: nvdla@0x11940000 {
compatible = "nvidia,nvdla_os_initial";
interrupt-parent = <&plic>;
interrupts = <22>;
memory-region = <&nvdla_reserved>;
reg = <0x0 0x11940000 0x0 0x40000>;
status = "okay";
};
jpu:coadj12@11900000 {
compatible = "cm,codaj12-jpu-1";
reg = <0x0 0x11900000 0x0 0x300>;
memory-region = <&jpu_reserved>;
interrupt-parent = <&plic>;
interrupts = <24>;
clocks = <&jpuclk>;
clock-names = "jpege";
reg-names = "control";
status = "okay";
};
vpu_dec:vpu_dec@118F0000 {
compatible = "c&m,cm511-vpu";
reg = <0 0x118F0000 0 0x10000>;
//memory-region = <&vpu_reserved>;
interrupt-parent = <&plic>;
interrupts = <23>;
clocks = <&vpuclk>;
clock-names = "vcodec";
status = "okay";
};
vpu_enc:vpu_enc@118E0000 {
compatible = "cm,cm521-vpu";
reg = <0x0 0x118E0000 0x0 0x4000>;
interrupt-parent = <&plic>;
interrupts = <26>;
clocks = <&vpuclk>;
clock-names = "vcodec";
reg-names = "control";
};
ptc: pwm@12490000 {
compatible = "starfive,pwm0";
reg = <0x0 0x12490000 0x0 0x10000>;
reg-names = "control";
sifive,approx-period = <100000000>;
clocks = <&pwmclk>;
#pwm-cells=<3>;
sifive,npwm = <8>;
};
qspi:qspi@11860000 {
compatible = "cadence,qspi","cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x11860000 0x0 0x10000 0x0 0x20000000 0x0 0x20000000 >;
interrupts = <3>;
interrupt-parent = <&plic>;
clocks = <&qspi_clk>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
status = "okay";
spi-max-frequency = <250000000>;
nor_flash:nor-flash@0 {
compatible = "spi-flash";
reg=<0>;
spi-max-frequency = <31250000>;
page-size = <256>;
block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <1>;
cdns,tsd2d-ns = <1>;
cdns,tchsh-ns = <1>;
cdns,tslch-ns = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
nand_flash:nand-flash@1 {
compatible = "spi-flash-nand";
reg=<1>;
spi-max-frequency = <31250000>;
page-size = <2048>;
block-size = <17>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <1>;
cdns,tsd2d-ns = <1>;
cdns,tchsh-ns = <1>;
cdns,tslch-ns = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
spi2:spi2@12410000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <70>;
reg = <0x0 0x12410000 0x0 0x10000>;
clocks = <&spiclk>;
/*num-cs = <1>;
cs-gpios = <&gpio 0 0>;*/
spi_dev0: spi@0 {
compatible = "rohm,dh2228fv";
spi-max-frequency = <10000000>;
reg = <0>;
status = "okay";
};
};
xrp@0 {
compatible = "cdns,xrp";
reg = <0x0 0xf0000000 0x0 0x01ffffff
0x10 0x72000000 0x0 0x00001000
0x10 0x72001000 0x0 0x00fff000
0x0 0x124b0000 0x0 0x00010000>;
clocks = <&hfclk>;
interrupt-parent = <&plic>;
firmware-name = "vp6_elf";
dsp-irq = <19 20>;
dsp-irq-src = <0x20 0x21>;
intc-irq-mode = <1>;
intc-irq = <0 1>;
interrupts = <27 28>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x40000000 0x0 0x40000000 0x01000000
0xb0000000 0x10 0x70000000 0x3000000>;
dsp@0 {
};
};
sdio0:sdio0@10000000{
compatible = "snps,dw-mshc";
reg = <0x0 0x10000000 0x0 0x10000>;
interrupts = <4>;
interrupt-parent = <&plic>;
clocks = <&dwmmc_biuclk>;
clock-names = "biu";
clock-frequency = <100000000>;
max-frequency = <10000000>;
fifo-depth = <32>;
card-detect-delay = <300>;
fifo-watermark-aligned;
data-addr = <0>;
bus-width = <4>;
cap-sd-highspeed;
broken-cd;
no-sdio;
post-power-on-delay-ms = <200>;
};
sdio1:sdio1@10010000{
compatible = "snps,dw-mshc";
reg = <0x0 0x10010000 0x0 0x10000>;
interrupts = <5>;
interrupt-parent = <&plic>;
clocks = <&dwmmc_biuclk>;
clock-names = "biu";
clock-frequency = <100000000>;
max-frequency = <50000000>;
fifo-depth = <32>;
card-detect-delay = <300>;
fifo-watermark-aligned;
data-addr = <0>;
bus-width = <4>;
cap-sd-highspeed;
/*broken-cd;*/
cap-sdio-irq;
cap-mmc-hw-reset;
non-removable;
enable-sdio-wakeup;
keep-power-in-suspend;
/*cap-power-off-card;*/
cap-mmc-highspeed;
/*fixed-emmc-driver-type;*/
post-power-on-delay-ms = <200>;
/*
bcmdhd_wlan: bcmdhd_wlan@1 {
compatible = "android,bcmdhd_wlan";
gpios = <&gpio 26 0>;
};
*/
};
sfivefb:sfivefb@12000000 {
compatible = "starfive,vpp-lcdc";
interrupt-parent = <&plic>;
interrupts = <101>, <103>;
interrupt-names = "lcdc_irq", "vpp1_irq";
reg = <0x0 0x12000000 0x0 0x10000>,
<0x0 0x12100000 0x0 0x10000>,
<0x0 0x12040000 0x0 0x10000>,
<0x0 0x12080000 0x0 0x10000>,
<0x0 0x120c0000 0x0 0x10000>,
<0x0 0x12240000 0x0 0x10000>,
<0x0 0x12250000 0x0 0x10000>,
<0x0 0x12260000 0x0 0x10000>;
reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
memory-region = <&sffb_reserved>;
clocks = <&uartclk>, <&apb2clk>;
clock-names = "baudclk", "apb_pclk";
status = "okay";
ddr-format = <WIN_FMT_RGB565>;/*LCDC win_format*/
/*pp1 {
pp-id = <1>;
fifo-out;
src-format = <COLOR_YUV420_NV21>;
src-width = <800>;
src-height = <480>;
dst-format = <COLOR_RGB888_ARGB>;
dst-width = <800>;
dst-height = <480>;
};*/
};
vin_sysctl:vin_sysctl@19800000 {
compatible = "starfive,stf-vin";
reg = <0x0 0x19800000 0x0 0x10000>,
<0x0 0x19810000 0x0 0x10000>,
<0x0 0x19820000 0x0 0x10000>,
<0x0 0x19830000 0x0 0x10000>,
<0x0 0x19840000 0x0 0x10000>,
<0x0 0x19870000 0x0 0x30000>,
<0x0 0x198a0000 0x0 0x30000>,
<0x0 0x11800000 0x0 0x10000>,
<0x0 0x11840000 0x0 0x10000>,
<0x0 0x11858000 0x0 0x10000>;
reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", "isp0", "isp1", "tclk", "trst", "iopad"; interrupt-parent = <&plic>;
interrupts = <119 109>;
memory-region = <&vin_reserved>;
/*defaule config for imx219 vin&isp*/
format = <SRC_CSI2RX_VIN_ISP>;
frame-width = <800>;
frame-height =<480>;
isp0_enable;
csi-lane = <2>;
csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>;
csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>;
csi-clane-swap = /bits/ 8 <0>;
csi-clane-pn-swap = /bits/ 8 <0>;
csi-mipiID = <0>;
csi-width = <1920>;
csi-height = <1080>;
csi-dt = <0x2b>;
};
sfc_tmp:tmpsensor@124A0000 {
compatible = "sfc,tempsensor";
reg = <0x0 0x124A0000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <122>;
status = "okay";
};
otp:otp@11810000{
compatible = "starfive,fu740-otp";
reg = <0x0 0x11810000 0x0 0x10000>;
fuse-count = <0x200>;
};
};
};
#include "tda998x_1080p.dtsi"
#include "seeed5inch.dtsi"

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/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
#include <dt-bindings/starfive_fb.h>
&sfivefb {
tda_998x_1080p {
compatible = "starfive,display-dev";
panel_name = "tda_998x_1080p";
panel_lcd_id = <22>; /*1080p*/
interface_info = "rgb_interface";
refresh_en = <1>;
bits-per-pixel = <16>;
physical-width = <62>;
physical-height = <114>;
panel-width = <1920>;
panel-height = <1080>;
pixel-clock = <78000000>;
/*dyn_fps;*/ /*dynamic frame rate support*/
/*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/
/*gamma-command-monolithic;*/
/*ce-command-monolithic;*/
/*resume-with-gamma;*/
/*resume-with-ce;*/
/*mipi info*/
mipi-byte-clock = <78000>;
mipi-escape-clock = <13000>;
lane-no = <4>;
display_mode = "video_mode"; /*video_mode, command_mode*/
/*
auto_stop_clklane_en;
im_pin_val;*/
color_bits = <COLOR_CODE_24BIT>;
/*is_18bit_loosely;*/
/*video mode info*/
h-pulse-width = <44>;
h-back-porch = <148>;
h-front-porch = <88>;
v-pulse-width = <5>;
v-back-porch = <36>;
v-front-porch = <4>;
status = "okay";
sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/
lp_cmd_en;
/*lp_hfp_en;*/
/*lp_hbp_en;*/
/*lp_vact_en;*/
lp_vfp_en;
lp_vbp_en;
lp_vsa_en;
traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/
/*phy info*/
data_tprepare = /bits/ 8 <0>;
data_hs_zero = /bits/ 8 <0>;
data_hs_exit = /bits/ 8 <0>;
data_hs_trail = /bits/ 8 <0>;
/*te info*/
te_source = "external_pin"; /*external_pin, dsi_te_trigger*/
te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/
te_enable = <0>;
cm_te_effect_sync_enable = <0>; /*used in command mode*/
te_count_per_sec = <64>; /*used in esd*/
/*ext info*/
/*
crc_rx_en;
ecc_rx_en;
eotp_rx_en;
*/
eotp_tx_en;
dev_read_time = <0x7FFF>;
/*type cmd return_count return_code*/
/*id_read_cmd_info = [];*/
/*pre_id_cmd = [];*/
/*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/
/*pre_esd_cmd = [];*/
/*panel-on-command = [];*/
/*panel-off-command = [];*/
/*reset-sequence = <1 5>, <0 10>, <1 30>;*/
/*
panel-gamma-warm-command = [
];
panel-gamma-nature-command = [
];
panel-gamma-cool-command = [
];
panel-ce-std-command = [
];
panel-ce-vivid-command = [
];
*/
};
};

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2020-2021 SiFive Inc
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#ifndef __CLK_SIFIVE_H
#define __CLK_SIFIVE_H
/* Note: This is a placeholder header for driver compilation. */
#endif

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/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
#ifndef __STARFIVE_FB_H
#define __STARFIVE_FB_H
/*color code*/
#define COLOR_CODE_16BIT_CONFIG1 0 //PACKET RGB565
#define COLOR_CODE_16BIT_CONFIG2 1 //UNPACKET RGB565
#define COLOR_CODE_16BIT_CONFIG3 2 //UNPACKET RGB565
#define COLOR_CODE_18BIT_CONFIG1 3 //PACKET RGB666
#define COLOR_CODE_18BIT_CONFIG2 4 //UNPACKET RGB666
#define COLOR_CODE_24BIT 5 //PACKET RGB888
#define COLOR_CODE_MAX 6
/*command code*/
#define DCS_CMD 02
#define GEN_CMD 03
#define SW_PACK0 04
#define SW_PACK1 05
#define SW_PACK2 06
#define LW_PACK 07
#define SHUTDOWN_SW_PACK 08
/*color format, need match to enum COLOR_FORMAT in starfive_vpp.h*/
#define COLOR_YUV422_UYVY 0
#define COLOR_YUV422_VYUY 1
#define COLOR_YUV422_YUYV 2
#define COLOR_YUV422_YVYU 3
#define COLOR_YUV420P 4
#define COLOR_YUV420_NV21 5
#define COLOR_YUV420_NV12 6
#define COLOR_RGB888_ARGB 7
#define COLOR_RGB888_ABGR 8
#define COLOR_RGB888_RGBA 9
#define COLOR_RGB888_BGRA 10
#define COLOR_RGB565 11
#define SRC_COLORBAR_VIN_ISP 0
#define SRC_DVP_SENSOR_VIN 1
#define SRC_DVP_SENSOR_VIN_ISP 2
#define SRC_CSI2RX_VIN_ISP 3
#define SRC_DVP_SENSOR_VIN_OV5640 4
#define WIN_FMT_RGB565 4
#define WIN_FMT_xRGB1555 5
#define WIN_FMT_xRGB4444 6
#define WIN_FMT_xRGB8888 7
#endif

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if TARGET_STARFIVE_JH7100
config SYS_CPU
default "fu740"
config SYS_BOARD
default "jh7100"
config SYS_VENDOR
default "starfive"
config SYS_SOC
default "jh7100"
config SYS_CONFIG_NAME
default "starfive-jh7100"
config ENV_SIZE
default 0x2000 if ENV_IS_IN_SPI_FLASH
config ENV_OFFSET
default 0xf00000 if ENV_IS_IN_SPI_FLASH
config SYS_TEXT_BASE
default 0x80200000 if SPL
default 0x80000000 if !RISCV_SMODE
default 0x80200000 if RISCV_SMODE
config SPL_TEXT_BASE
default 0x08000000
config SPL_OPENSBI_LOAD_ADDR
default 0x80000000
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SIFIVE_FU740
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
imply CMD_FAT
imply CMD_FS_GENERIC
imply CMD_GPT
imply PARTITION_TYPE_GUID
imply CMD_NET
imply CMD_PING
imply CMD_SF
imply DOS_PARTITION
imply EFI_PARTITION
imply IP_DYN
imply ISO_PARTITION
imply PHY_LIB
imply PHY_MSCC
imply SPI_FLASH
imply SPI_FLASH_ISSI
imply SYSRESET
imply SYSRESET_GPIO
imply CMD_DHCP
endif

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STARFIVE JH7100 SOC
M: startfive
S: Maintained
F: board/starfive/jh7100/
F: include/configs/starfive-jh7100.h
F: configs/starfive_jh7100_starlight_smode_defconfig

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# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2021 Shanghai StarFive Technology Co., Ltd.
# Micheal Zhu <michael.zhu@starfivetech.com>
obj-y += jh7100.o

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 Shanghai StarFive Technology Co., Ltd.
* Micheal Zhu <michael.zhu@starfivetech.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <env.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <dm.h>
#include <misc.h>
#include <inttypes.h>
#include <netdev.h>
#include <phy_interface.h>
#include <flash.h>
#include <asm/arch/cache.h>
DECLARE_GLOBAL_DATA_PTR;
struct sifive_gpio_regs
{
volatile uint32_t INPUT_VAL; /* 0x0000 */
volatile uint32_t INPUT_EN; /* 0x0004 */
volatile uint32_t OUTPUT_VAL; /* 0x0008 */
volatile uint32_t OUTPUT_EN; /* 0x000C */
volatile uint32_t PUE; /* 0x0010 */
volatile uint32_t DS; /* 0x0014 */
volatile uint32_t RISE_IE; /* 0x0018 */
volatile uint32_t RISE_IP; /* 0x001C */
volatile uint32_t FALL_IE; /* 0x0020 */
volatile uint32_t FALL_IP; /* 0x0024 */
volatile uint32_t HIGH_IE; /* 0x0028 */
volatile uint32_t HIGH_IP; /* 0x002C */
volatile uint32_t LOW_IE; /* 0x0030 */
volatile uint32_t LOW_IP; /* 0x0034 */
volatile uint32_t reserved0; /* 0x0038 */
volatile uint32_t reserved1; /* 0x003C */
volatile uint32_t OUT_XOR; /* 0x0040 */
};
#define SIFIVE_BASE_GPIO 0x10060000
struct sifive_gpio_regs *g_aloe_gpio = (struct sifive_gpio_regs *) SIFIVE_BASE_GPIO;
/*
* Init includes toggling the reset line which is connected to GPIO 0 pin 12.
* This is the only pin I can see on the 16 GPIO which is currently set as an.
* output. We will hard code the setup here to avoid having to have a GPIO
* driver as well...
*
* The Aloe board is strapped for unmanaged mode and needs two pulses of the
* reset line to configure the device properly.
*
* The RX_CLK, TX_CLK and RXD7 pins are strapped high and the remainder low.
* This selects GMII mode with auto 10/100/1000 and 125MHz clkout.
*/
void reset_phy(void)
{
g_aloe_gpio->OUTPUT_EN |= 0x00001000ul; /* Configure pin 12 as an output */
#define PHY_RST_LOOPS 2
for (int i = 0; i < PHY_RST_LOOPS; i++) {
g_aloe_gpio->OUTPUT_VAL &= 0x0000EFFFul; /* Clear pin 12 to reset PHY */
udelay(1000);
g_aloe_gpio->OUTPUT_VAL |= 0x00001000ul; /* Take PHY^ out of reset */
udelay(1000);
}
/* Need at least 15mS delay before accessing PHY after reset... */
udelay(15000);
}
/* This define is a value used for error/unknown serial. If we really care about distinguishing errors and 0 is valid, we'll need a different one. */
#define ERROR_READING_SERIAL_NUMBER 0
#if CONFIG_IS_ENABLED(MISC_INIT_R)
#if CONFIG_IS_ENABLED(STARFIVE_OTP)
static u32 otp_read_mac(struct udevice *dev, unsigned char *buf)
{
u32 serial[2] = {0};
int ret = misc_read(dev, STARFIVE_OTP_MAC_OFFSET,
serial, sizeof(serial));
if (ret != sizeof(serial)) {
printf("%s: error reading mac from OTP\n", __func__);
return ERROR_READING_SERIAL_NUMBER;
}
buf[3] = (serial[0] >> 24) & 0xff;
buf[2] = (serial[0] >> 16) & 0xff;
buf[1] = (serial[0] >> 8) & 0xff;
buf[0] = serial[0] & 0xff;
buf[5] = (serial[1] >> 8) & 0xff;
buf[4] = serial[1] & 0xff;
return ret;
}
static u32 otp_read_serialnum(struct udevice *dev)
{
u32 serial[2] = {0};
int ret = misc_read(dev, STARFIVE_OTP_MAC_OFFSET-8,
serial, sizeof(serial));
if (ret != sizeof(serial)) {
printf("%s: error reading serial from OTP\n", __func__);
return ERROR_READING_SERIAL_NUMBER;
}
if (serial[0] == ~serial[1])
return serial[0];
return ERROR_READING_SERIAL_NUMBER;
}
#endif
static u32 jh_read_serialnum(void)
{
u32 serial = ERROR_READING_SERIAL_NUMBER;
#if CONFIG_IS_ENABLED(STARFIVE_OTP)
struct udevice *dev;
char buf[9] = {0};
if (uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(starfive_otp), &dev)) {
debug("%s: could not find otp device\n", __func__);
return ERROR_READING_SERIAL_NUMBER;
}
// read serial from OTP and set env var
serial = otp_read_serialnum(dev);
snprintf(buf, sizeof(buf), "%08x", serial);
env_set("serial#", buf);
#endif
return serial;
}
static void jh_setup_macaddr(u32 serialnum)
{
#if CONFIG_IS_ENABLED(STARFIVE_OTP)
struct udevice *dev;
unsigned char mac[6]={0};
// init OTP
if (uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(starfive_otp), &dev)) {
debug("%s: could not find otp device\n", __func__);
return;
}
otp_read_mac(dev, mac);
#else
unsigned char mac[6] = {0x66, 0x34, 0xb0, 0x6c, 0xde, 0xad};
mac[5] |= (serialnum >> 0) & 0xff;
mac[4] |= (serialnum >> 8) & 0xff;
mac[3] |= (serialnum >> 16) & 0xff;
#endif
eth_env_set_enetaddr("ethaddr", mac);
}
int misc_init_r(void)
{
if (!env_get("serial#")) {
u32 serialnum = jh_read_serialnum();
jh_setup_macaddr(serialnum);
}
return 0;
}
#endif
#if CONFIG_IS_ENABLED(CMD_NET)
int board_eth_init(struct bd_info *bis)
{
int ret = 0;
#if CONFIG_IS_ENABLED(ETH_DESIGNWARE)
#define SIFIVE_BASE_ETHERNET 0x10020000 //GMAC
u32 interface = PHY_INTERFACE_MODE_RGMII_TXID;
if (designware_initialize(SIFIVE_BASE_ETHERNET, interface) >= 0)
ret++;
#endif
return ret;
}
#endif
/*
* Miscellaneous platform dependent initializations
*/
int board_init(void)
{
int ret = 0;
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
/* enable all cache ways */
enable_caches();
return ret;
}

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CONFIG_RISCV=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x200000000
CONFIG_ENV_SIZE=0x1f000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_MALLOC_LEN=0x800000
# CONFIG_DM_GPIO is not set
CONFIG_DEFAULT_DEVICE_TREE="starfive_jh7100_starlight"
CONFIG_IDENT_STRING="StarFive"
CONFIG_SYS_CLK_FREQ=1000000000
CONFIG_TARGET_STARFIVE_JH7100=y
CONFIG_JH_STARLIGHT=y
CONFIG_SIFIVE_CCACHE_WAYENABLE_OPT=y
CONFIG_SIFIVE_CCACHE_WAYENABLE_NUM=16
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_SHOW_REGS=y
CONFIG_LOCALVERSION="-Starlight"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BOOT_GET_KBD=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_CHROMEOS=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_SPI_BOOT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_DELAY_STR="f"
CONFIG_AUTOBOOT_STOP_STR="v"
CONFIG_AUTOBOOT_KEYED_CTRLC=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run mmcbootenv"
CONFIG_DEFAULT_FDT_FILE="starfive/jh7100-beaglev-starlight.dtb"
CONFIG_CONSOLE_RECORD=y
CONFIG_LOG_MAX_LEVEL=5
CONFIG_LOG_ERROR_RETURN=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="Starlight #"
CONFIG_CMD_CONFIG=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_SBI=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTM_OPENRTOS=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_ENV_CALLBACK=y
CONFIG_CMD_ENV_FLAGS=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_NVEDIT_INFO=y
CONFIG_CMD_NVEDIT_LOAD=y
CONFIG_CMD_NVEDIT_SELECT=y
CONFIG_CMD_BINOP=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_MD5SUM=y
CONFIG_MD5SUM_VERIFY=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEM_SEARCH=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_SHA1SUM=y
CONFIG_SHA1SUM_VERIFY=y
CONFIG_CMD_STRINGS=y
CONFIG_CMD_CLK=y
# CONFIG_CMD_GPIO is not set
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_I2C=y
CONFIG_CMD_LSBLK=y
CONFIG_CMD_MBR=y
CONFIG_CMD_MISC=y
CONFIG_CMD_BKOPS_ENABLE=y
CONFIG_CMD_MMC_SWRITE=y
CONFIG_CMD_CLONE=y
CONFIG_CMD_READ=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SETEXPR_FMT=y
CONFIG_BOOTP_DNS2=y
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_BOOTP_NTPSERVER=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_RARP=y
# CONFIG_CMD_MII is not set
CONFIG_CMD_MDIO=y
CONFIG_CMD_DNS=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_UUID=y
CONFIG_CMD_AES=y
CONFIG_CMD_HASH=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_CBFS=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_FS_UUID=y
CONFIG_CMD_DIAG=y
CONFIG_CMD_LOG=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SECT_SIZE_AUTO=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_TSIZE=y
CONFIG_SERVERIP_FROM_PROXYDHCP=y
# CONFIG_CLK is not set
CONFIG_SYS_I2C_DW=y
# CONFIG_SYS_I2C_OCORES is not set
# CONFIG_SIFIVE_OTP is not set
# CONFIG_MMC_BROKEN_CD is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_QUIRKS is not set
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_DW=y
# CONFIG_MTD is not set
CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_GIGADEVICE=y
# CONFIG_SPI_FLASH_ISSI is not set
CONFIG_MTD_UBI=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=7
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
# CONFIG_PHY_MSCC is not set
# CONFIG_DM_ETH is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
# CONFIG_MII is not set
# CONFIG_DM_PWM is not set
# CONFIG_RAM_SIFIVE is not set
CONFIG_SPECIFY_CONSOLE_INDEX=y
# CONFIG_SIFIVE_SERIAL is not set
CONFIG_CADENCE_QSPI=y
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SYSRESET is not set
CONFIG_FS_CBFS=y
# CONFIG_FAT_WRITE is not set
CONFIG_FS_CRAMFS=y
# CONFIG_ASYMMETRIC_KEY_TYPE is not set
CONFIG_ERRNO_STR=y
# CONFIG_GENERATE_SMBIOS_TABLE is not set
CONFIG_UNIT_TEST=y

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include/configs/starfive-jh7100.h Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 Shanghai StarFive Technology Co., Ltd.
* Micheal Zhu <michael.zhu@starfivetech.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <version.h>
#include <linux/sizes.h>
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64MB */
/*
* Print Buffer Size
*/
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/*
* Boot Argument Buffer Size
*/
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* max number of command args
*/
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* Init Stack Pointer */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
#define CONFIG_STANDALONE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
/*mac addr offset in otp*/
#define STARFIVE_OTP_MAC_OFFSET 0x28
/*
* Ethernet
*/
#if CONFIG_IS_ENABLED(CMD_NET)
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_ARP_TIMEOUT 0x5000
#endif
/* HACK these should have '#if defined (stuff) around them like zynqp*/
#define BOOT_TARGET_DEVICES(func) func(DHCP, dhcp, na) \
func(MMC, mmc, 0)
#include <config_distro_bootcmd.h>
#include <environment/distro/sf.h>
#define STARLIGHT_FEDORA_BOOTENV \
"bootdir=/boot\0" \
"bootenv=uEnv.txt\0" \
"mmcdev=0\0" \
"mmcpart=3\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
STARLIGHT_FEDORA_BOOTENV \
"loadaddr=0xa0000000\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \
"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
"mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \
"mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"run loadbootenv && run importbootenv; " \
"run ext4bootenv && run importbootenv; " \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...; " \
"run uenvcmd; " \
"fi; " \
"fi\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV \
BOOTENV_SF
#define CONFIG_SYS_MAX_FLASH_SECT 0
#define CONFIG_SYS_MAX_FLASH_BANKS 0
#define __io
/*
* QSPI support
*/
#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
#define CONFIG_CQSPI_REF_CLK (250000000)
#endif
#endif /* __CONFIG_H */