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powerpc/p3060: Add SoC related support for P3060 platform
Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Shengzhou Liu
Kumar Gala
parent
6b3a8d0086
commit
6d7b061af1
10 changed files with 403 additions and 1 deletions
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@ -67,6 +67,7 @@ COBJS-$(CONFIG_P2020) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P2040) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P3060) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
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@ -81,6 +82,7 @@ COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
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COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
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COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
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COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
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COBJS-$(CONFIG_PPC_P3060) += p3060_ids.o
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COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
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COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
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@ -114,6 +116,7 @@ COBJS-$(CONFIG_P2020) += p2020_serdes.o
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COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
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COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
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COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
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COBJS-$(CONFIG_PPC_P3060) += p3060_serdes.o
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COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
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COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
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@ -482,6 +482,13 @@ static void wait_for_rstdone(unsigned int bank)
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printf("SERDES: timeout resetting bank %u\n", bank + 1);
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}
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void __soc_serdes_init(void)
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{
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/* Allow for SoC-specific initialization in <SOC>_serdes.c */
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};
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void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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@ -570,6 +577,8 @@ void fsl_serdes_init(void)
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}
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}
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soc_serdes_init();
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
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/*
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* Bank two uses the clock from bank three, so if bank two is enabled,
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113
arch/powerpc/cpu/mpc85xx/p3060_ids.c
Normal file
113
arch/powerpc/cpu/mpc85xx/p3060_ids.c
Normal file
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@ -0,0 +1,113 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#ifdef CONFIG_SYS_DPAA_QBMAN
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struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
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/* dqrr liodn, frame data liodn, liodn off, sdest */
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SET_QP_INFO( 1, 2, 1, 0),
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SET_QP_INFO( 3, 4, 2, 1),
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SET_QP_INFO( 5, 6, 3, 2),
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SET_QP_INFO( 7, 8, 4, 3),
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SET_QP_INFO( 9, 10, 5, 4),
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SET_QP_INFO(11, 12, 6, 5),
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SET_QP_INFO(13, 14, 7, 6),
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SET_QP_INFO(15, 16, 8, 7),
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SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */
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SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
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};
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#endif
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struct liodn_id_table liodn_tbl[] = {
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SET_USB_LIODN(1, "fsl-usb2-mph", 127),
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SET_USB_LIODN(2, "fsl-usb2-dr", 157),
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SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
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SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
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SET_DMA_LIODN(1, 196),
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SET_DMA_LIODN(2, 197),
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SET_GUTS_LIODN("fsl,rapidio-delta", 198, rio1liodnr, 0),
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SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0),
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SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0),
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#ifdef CONFIG_SYS_DPAA_QBMAN
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SET_QMAN_LIODN(31),
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SET_BMAN_LIODN(32),
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#endif
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SET_PME_LIODN(128),
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};
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int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
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#ifdef CONFIG_SYS_DPAA_FMAN
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struct liodn_id_table fman1_liodn_tbl[] = {
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SET_FMAN_RX_1G_LIODN(1, 0, 11),
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SET_FMAN_RX_1G_LIODN(1, 1, 12),
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SET_FMAN_RX_1G_LIODN(1, 2, 13),
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SET_FMAN_RX_1G_LIODN(1, 3, 14),
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};
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int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
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#if (CONFIG_SYS_NUM_FMAN == 2)
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struct liodn_id_table fman2_liodn_tbl[] = {
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SET_FMAN_RX_1G_LIODN(2, 0, 16),
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SET_FMAN_RX_1G_LIODN(2, 1, 17),
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SET_FMAN_RX_1G_LIODN(2, 2, 18),
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SET_FMAN_RX_1G_LIODN(2, 3, 19),
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};
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int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
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#endif
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#endif
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struct liodn_id_table sec_liodn_tbl[] = {
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SET_SEC_JR_LIODN_ENTRY(0, 146, 154),
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SET_SEC_JR_LIODN_ENTRY(1, 147, 155),
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SET_SEC_JR_LIODN_ENTRY(2, 178, 186),
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SET_SEC_JR_LIODN_ENTRY(3, 179, 187),
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SET_SEC_RTIC_LIODN_ENTRY(a, 144),
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SET_SEC_RTIC_LIODN_ENTRY(b, 145),
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SET_SEC_RTIC_LIODN_ENTRY(c, 176),
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SET_SEC_RTIC_LIODN_ENTRY(d, 177),
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SET_SEC_DECO_LIODN_ENTRY(0, 129, 161),
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SET_SEC_DECO_LIODN_ENTRY(1, 130, 162),
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SET_SEC_DECO_LIODN_ENTRY(2, 131, 163),
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SET_SEC_DECO_LIODN_ENTRY(3, 132, 164),
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SET_SEC_DECO_LIODN_ENTRY(4, 133, 165),
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};
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int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
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struct liodn_id_table liodn_bases[] = {
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[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106),
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#ifdef CONFIG_SYS_DPAA_FMAN
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[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
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#if (CONFIG_SYS_NUM_FMAN == 2)
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[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64),
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#endif
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#endif
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#ifdef CONFIG_SYS_DPAA_PME
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[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(116, 133),
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#endif
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};
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138
arch/powerpc/cpu/mpc85xx/p3060_serdes.c
Normal file
138
arch/powerpc/cpu/mpc85xx/p3060_serdes.c
Normal file
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@ -0,0 +1,138 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "fsl_corenet_serdes.h"
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static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
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[0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
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SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC1,
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SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2,
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NONE, NONE, AURORA, AURORA},
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[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SGMII_FM2_DTSEC3,
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SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4,
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SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM1_DTSEC2, NONE, NONE, AURORA, AURORA},
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[0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
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SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
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SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
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[0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, PCIE2, PCIE2, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
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SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
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[0x1c] = {NONE, NONE, SRIO1, SRIO2, NONE, NONE, NONE, NONE,
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AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
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SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
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SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
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};
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enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
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{
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if (!serdes_lane_enabled(lane))
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return NONE;
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return serdes_cfg_tbl[cfg][lane];
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}
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int is_serdes_prtcl_valid(u32 prtcl)
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{
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int i;
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if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_cfg_tbl[prtcl][i] != NONE)
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return 1;
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}
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return 0;
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}
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void soc_serdes_init(void)
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{
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/*
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* On the P3060 the devdisr2 register does not correctly reflect
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* the state of the MACs based on the RCW fields. So disable the MACs
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* based on the srds_prtcl and ec1, ec2, ec3 fields
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*/
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr2 = in_be32(&gur->devdisr2);
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u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
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u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
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u32 ec1_ext, ec2_ext;
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/* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */
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if (!is_serdes_configured(SGMII_FM1_DTSEC3))
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devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_3;
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if (!is_serdes_configured(SGMII_FM1_DTSEC4))
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devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_4;
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if (!is_serdes_configured(SGMII_FM2_DTSEC1))
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devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_1;
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if (!is_serdes_configured(SGMII_FM2_DTSEC2))
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devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_2;
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if (!is_serdes_configured(SGMII_FM2_DTSEC3))
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devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_3;
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if (!is_serdes_configured(SGMII_FM2_DTSEC4))
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devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_4;
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if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
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FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) {
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devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_2;
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}
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if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
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FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1) {
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devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_1;
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}
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ec1_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT;
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if (ec1_ext) {
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if ((ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII) ||
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(ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII))
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devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_4;
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}
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ec2_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT;
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if (ec2_ext) {
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if ((ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII) ||
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(ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII))
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devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4;
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}
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if ((rcwsr13 & FSL_CORENET_RCWSR13_EC3) ==
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FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII)
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devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4;
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out_be32(&gur->devdisr2, devdisr2);
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}
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@ -103,6 +103,8 @@ struct cpu_type cpu_type_list [] = {
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CPU_TYPE_ENTRY(P2041, P2041_E, 4),
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CPU_TYPE_ENTRY(P3041, P3041, 4),
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CPU_TYPE_ENTRY(P3041, P3041_E, 4),
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CPU_TYPE_ENTRY_MASK(P3060, P3060, 6, 0xf3),
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CPU_TYPE_ENTRY_MASK(P3060, P3060_E, 6, 0xf3),
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CPU_TYPE_ENTRY(P4040, P4040, 4),
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CPU_TYPE_ENTRY(P4040, P4040_E, 4),
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CPU_TYPE_ENTRY(P4080, P4080, 8),
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@ -349,6 +349,21 @@
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#elif defined(CONFIG_PPC_P3060)
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#define CONFIG_MAX_CPUS 8
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 2
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#define CONFIG_SYS_NUM_FM1_DTSEC 4
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#define CONFIG_SYS_NUM_FM2_DTSEC 4
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
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#elif defined(CONFIG_PPC_P4040)
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
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@ -1700,7 +1700,7 @@ typedef struct ccsr_gur {
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#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
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#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
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#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
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#if defined(CONFIG_PPC_P4080)
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#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060)
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||||
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
|
||||
#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
|
||||
|
|
@ -1708,6 +1708,16 @@ typedef struct ccsr_gur {
|
|||
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
|
||||
#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_P3060)
|
||||
#define FSL_CORENET_RCWSR13_EC1_EXT 0x1c000000
|
||||
#define FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII 0x04000000
|
||||
#define FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII 0x08000000
|
||||
#define FSL_CORENET_RCWSR13_EC2_EXT 0x01c00000
|
||||
#define FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII 0x00400000
|
||||
#define FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII 0x00800000
|
||||
#define FSL_CORENET_RCWSR13_EC3 0x00380000
|
||||
#define FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII 0x00100000
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \
|
||||
|| defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
|
||||
|
|
|
|||
|
|
@ -1115,6 +1115,8 @@
|
|||
#define SVR_P2041_E 0x821801
|
||||
#define SVR_P3041 0x821103
|
||||
#define SVR_P3041_E 0x821903
|
||||
#define SVR_P3060 0x820002
|
||||
#define SVR_P3060_E 0x820802
|
||||
#define SVR_P4040 0x820100
|
||||
#define SVR_P4040_E 0x820900
|
||||
#define SVR_P4080 0x820000
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@ COBJS-$(CONFIG_P1023) += p1023.o
|
|||
COBJS-$(CONFIG_PPC_P2040) += p5020.o
|
||||
COBJS-$(CONFIG_PPC_P2041) += p5020.o
|
||||
COBJS-$(CONFIG_PPC_P3041) += p5020.o
|
||||
COBJS-$(CONFIG_PPC_P3060) += p3060.o
|
||||
COBJS-$(CONFIG_PPC_P4080) += p4080.o
|
||||
COBJS-$(CONFIG_PPC_P5020) += p5020.o
|
||||
endif
|
||||
|
|
|
|||
109
drivers/net/fm/p3060.c
Normal file
109
drivers/net/fm/p3060.c
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <phy.h>
|
||||
#include <fm_eth.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
|
||||
u32 port_to_devdisr[] = {
|
||||
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
|
||||
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
|
||||
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
|
||||
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
|
||||
[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
|
||||
[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
|
||||
[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
|
||||
[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
|
||||
};
|
||||
|
||||
static int is_device_disabled(enum fm_port port)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 devdisr2 = in_be32(&gur->devdisr2);
|
||||
|
||||
return port_to_devdisr[port] & devdisr2;
|
||||
}
|
||||
|
||||
void fman_disable_port(enum fm_port port)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
|
||||
}
|
||||
|
||||
phy_interface_t fman_port_enet_if(enum fm_port port)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
|
||||
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
|
||||
|
||||
if (is_device_disabled(port))
|
||||
return PHY_INTERFACE_MODE_NONE;
|
||||
|
||||
/* handle RGMII/MII first */
|
||||
if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
|
||||
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
|
||||
return PHY_INTERFACE_MODE_RGMII;
|
||||
|
||||
if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
|
||||
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
|
||||
return PHY_INTERFACE_MODE_RGMII;
|
||||
|
||||
if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
|
||||
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
|
||||
return PHY_INTERFACE_MODE_RGMII;
|
||||
|
||||
if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT) ==
|
||||
FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII))
|
||||
return PHY_INTERFACE_MODE_RGMII;
|
||||
|
||||
if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT) ==
|
||||
FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII))
|
||||
return PHY_INTERFACE_MODE_MII;
|
||||
|
||||
if ((port == FM2_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT) ==
|
||||
FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII))
|
||||
return PHY_INTERFACE_MODE_RGMII;
|
||||
|
||||
if ((port == FM2_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT) ==
|
||||
FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII))
|
||||
return PHY_INTERFACE_MODE_MII;
|
||||
|
||||
switch (port) {
|
||||
case FM1_DTSEC1:
|
||||
case FM1_DTSEC2:
|
||||
case FM1_DTSEC3:
|
||||
case FM1_DTSEC4:
|
||||
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
|
||||
return PHY_INTERFACE_MODE_SGMII;
|
||||
break;
|
||||
case FM2_DTSEC1:
|
||||
case FM2_DTSEC2:
|
||||
case FM2_DTSEC3:
|
||||
case FM2_DTSEC4:
|
||||
if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
|
||||
return PHY_INTERFACE_MODE_SGMII;
|
||||
break;
|
||||
default:
|
||||
return PHY_INTERFACE_MODE_NONE;
|
||||
}
|
||||
|
||||
return PHY_INTERFACE_MODE_NONE;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue