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Blackfin: bfin_mac: cleanup pointer/casts for aliasing issues
Redo how pointers are managed to get rid of ugly casts and strict pointer aliasing issues that are highlighted by gcc 4.3. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Ben Warren <biggerbadderben@gmail.com>
This commit is contained in:
Mike Frysinger
parent
092d2487ba
commit
6d7d4803c7
2 changed files with 34 additions and 46 deletions
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@ -39,34 +39,27 @@
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#define TOUT_LOOP 1000000
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ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
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ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
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static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
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static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
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static u16 txIdx; /* index of the current RX buffer */
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static u16 rxIdx; /* index of the current TX buffer */
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/* DMAx_CONFIG values at DMA Restart */
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const ADI_DMA_CONFIG_REG rxdmacfg = {
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.b_DMA_EN = 1, /* enabled */
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.b_WNR = 1, /* write to memory */
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.b_WDSIZE = 2, /* wordsize is 32 bits */
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.b_DMA2D = 0,
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.b_RESTART = 0,
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.b_DI_SEL = 0,
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.b_DI_EN = 0, /* no interrupt */
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.b_NDSIZE = 5, /* 5 half words is desc size */
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.b_FLOW = 7 /* large desc flow */
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};
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const ADI_DMA_CONFIG_REG txdmacfg = {
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.b_DMA_EN = 1, /* enabled */
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.b_WNR = 0, /* read from memory */
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.b_WDSIZE = 2, /* wordsize is 32 bits */
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.b_DMA2D = 0,
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.b_RESTART = 0,
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.b_DI_SEL = 0,
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.b_DI_EN = 0, /* no interrupt */
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.b_NDSIZE = 5, /* 5 half words is desc size */
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.b_FLOW = 7 /* large desc flow */
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static const union {
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u16 data;
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ADI_DMA_CONFIG_REG reg;
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} txdmacfg = {
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.reg = {
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.b_DMA_EN = 1, /* enabled */
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.b_WNR = 0, /* read from memory */
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.b_WDSIZE = 2, /* wordsize is 32 bits */
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.b_DMA2D = 0,
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.b_RESTART = 0,
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.b_DI_SEL = 0,
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.b_DI_EN = 0, /* no interrupt */
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.b_NDSIZE = 5, /* 5 half words is desc size */
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.b_FLOW = 7 /* large desc flow */
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},
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};
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static int bfin_miiphy_wait(void)
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@ -150,8 +143,8 @@ static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
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txbuf[txIdx]->FrmData->NoBytes = length;
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memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
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txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
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*pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
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*pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
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*pDMA2_NEXT_DESC_PTR = txbuf[txIdx]->Dma;
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*pDMA2_CONFIG = txdmacfg.data;
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*pEMAC_OPMODE |= TE;
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for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
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@ -328,27 +321,23 @@ static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
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for (i = 0; i < PKTBUFSRX; i++) {
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rxbuf[i] = SetupRxBuffer(i);
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if (i > 0) {
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rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
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&(rxbuf[i]->Dma[0]);
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rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
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if (i == (PKTBUFSRX - 1))
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rxbuf[i]->Dma[1].NEXT_DESC_PTR =
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&(rxbuf[0]->Dma[0]);
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rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
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}
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}
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for (i = 0; i < TX_BUF_CNT; i++) {
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txbuf[i] = SetupTxBuffer(i);
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if (i > 0) {
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txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
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&(txbuf[i]->Dma[0]);
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txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
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if (i == (TX_BUF_CNT - 1))
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txbuf[i]->Dma[1].NEXT_DESC_PTR =
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&(txbuf[0]->Dma[0]);
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txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
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}
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}
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/* Set RX DMA */
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*pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
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*pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
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*pDMA1_NEXT_DESC_PTR = rxbuf[0]->Dma;
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*pDMA1_CONFIG = rxbuf[0]->Dma[0].CONFIG_DATA;
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/* Wait MII done */
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bfin_miiphy_wait();
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@ -403,10 +392,8 @@ ADI_ETHER_BUFFER *SetupRxBuffer(int no)
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int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
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int total_size = nobytes_buffer + RECV_BUFSIZE;
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buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
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frmbuf =
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(ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
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nobytes_buffer);
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buf = (void *) (RXBUF_BASE_ADDR + no * total_size);
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frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
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memset(buf, 0x00, nobytes_buffer);
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buf->FrmData = frmbuf;
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@ -422,7 +409,7 @@ ADI_ETHER_BUFFER *SetupRxBuffer(int no)
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buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
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/* set up second desc to point to status word */
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buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
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buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
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buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
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buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
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buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
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@ -441,10 +428,8 @@ ADI_ETHER_BUFFER *SetupTxBuffer(int no)
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int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
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int total_size = nobytes_buffer + RECV_BUFSIZE;
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buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
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frmbuf =
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(ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
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nobytes_buffer);
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buf = (void *) (TXBUF_BASE_ADDR + no * total_size);
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frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
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memset(buf, 0x00, nobytes_buffer);
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buf->FrmData = frmbuf;
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@ -35,7 +35,10 @@ typedef struct adi_ether_frame_buffer {
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typedef struct dma_descriptor {
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struct dma_descriptor *NEXT_DESC_PTR;
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u32 START_ADDR;
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ADI_DMA_CONFIG_REG CONFIG;
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union {
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u16 CONFIG_DATA;
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ADI_DMA_CONFIG_REG CONFIG;
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};
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} DMA_DESCRIPTOR;
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/* 10 bytes/struct in 12 bytes */
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