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ppc/85xx/pci: fsl_pci_init: pcie agent mode support
Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
parent
273a28ad9e
commit
70ed869ea5
6 changed files with 28 additions and 13 deletions
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@ -199,7 +199,7 @@ void pci_init_board(void)
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pcie_ep ? "End Point" : "Root Complex",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie3_hose, first_free_busno);
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&pcie3_hose, first_free_busno, pcie_ep);
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/*
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/*
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* Activate ULI1575 legacy chip by performing a fake
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* Activate ULI1575 legacy chip by performing a fake
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* memory access. Needed to make ULI RTC work.
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* memory access. Needed to make ULI RTC work.
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@ -231,7 +231,7 @@ void pci_init_board(void)
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pcie_ep ? "End Point" : "Root Complex",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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&pcie2_hose, first_free_busno, pcie_ep);
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} else {
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} else {
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printf (" PCIE2: disabled\n");
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printf (" PCIE2: disabled\n");
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}
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}
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@ -251,7 +251,7 @@ void pci_init_board(void)
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pcie_ep ? "End Point" : "Root Complex",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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&pcie1_hose, first_free_busno, pcie_ep);
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} else {
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} else {
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printf (" PCIE1: disabled\n");
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printf (" PCIE1: disabled\n");
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}
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}
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@ -71,7 +71,7 @@ void pci_init_board(void)
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pcie_ep ? "End Point" : "Root Complex",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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&pcie2_hose, first_free_busno, pcie_ep);
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} else {
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} else {
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printf (" PCIE2: disabled\n");
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printf (" PCIE2: disabled\n");
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}
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}
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@ -90,7 +90,7 @@ void pci_init_board(void)
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pcie_ep ? "End Point" : "Root Complex",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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&pcie1_hose, first_free_busno, pcie_ep);
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} else {
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} else {
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printf (" PCIE1: disabled\n");
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printf (" PCIE1: disabled\n");
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}
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}
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@ -227,7 +227,7 @@ void pci_init_board(void)
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pcie_ep ? "End Point" : "Root Complex",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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&pcie2_hose, first_free_busno, pcie_ep);
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/*
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/*
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* The workaround doesn't work on p2020 because the location
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* The workaround doesn't work on p2020 because the location
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@ -267,7 +267,7 @@ void pci_init_board(void)
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pcie_ep ? "End Point" : "Root Complex",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie3_hose, first_free_busno);
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&pcie3_hose, first_free_busno, pcie_ep);
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} else {
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} else {
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printf(" PCIE3: disabled\n");
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printf(" PCIE3: disabled\n");
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}
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}
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@ -286,7 +286,7 @@ void pci_init_board(void)
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pcie_ep ? "End Point" : "Root Complex",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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&pcie1_hose, first_free_busno, pcie_ep);
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} else {
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} else {
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printf(" PCIE1: disabled\n");
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printf(" PCIE1: disabled\n");
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}
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}
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@ -359,7 +359,7 @@ pci_init_board(void)
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SET_STD_PCI_INFO(pci_info[num], 1);
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SET_STD_PCI_INFO(pci_info[num], 1);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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&pci1_hose, first_free_busno, 0);
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} else {
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} else {
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printf (" PCI: disabled\n");
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printf (" PCI: disabled\n");
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}
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}
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@ -378,7 +378,7 @@ pci_init_board(void)
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SET_STD_PCIE_INFO(pci_info[num], 1);
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SET_STD_PCIE_INFO(pci_info[num], 1);
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printf (" PCIE at base address %lx\n", pci_info[num].regs);
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printf (" PCIE at base address %lx\n", pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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&pcie1_hose, first_free_busno, 0);
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} else {
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} else {
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printf (" PCIE: disabled\n");
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printf (" PCIE: disabled\n");
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}
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}
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright 2007 Freescale Semiconductor, Inc.
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* Copyright 2007-2009 Freescale Semiconductor, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* modify it under the terms of the GNU General Public License
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@ -413,13 +413,27 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
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}
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}
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int fsl_pci_init_port(struct fsl_pci_info *pci_info,
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int fsl_pci_init_port(struct fsl_pci_info *pci_info,
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struct pci_controller *hose, int busno)
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struct pci_controller *hose, int busno, int pcie_ep)
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{
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{
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volatile ccsr_fsl_pci_t *pci;
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volatile ccsr_fsl_pci_t *pci;
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struct pci_region *r;
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struct pci_region *r;
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pci = (ccsr_fsl_pci_t *) pci_info->regs;
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pci = (ccsr_fsl_pci_t *) pci_info->regs;
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if (pcie_ep) {
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volatile pit_t *pi = &pci->pit[2];
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pci_setup_indirect(hose, (u32)&pci->cfg_addr,
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(u32)&pci->cfg_data);
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out_be32(&pi->pitar, 0);
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out_be32(&pi->piwbar, 0);
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out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_IWS_4K);
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fsl_pci_config_unlock(hose);
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return 0;
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}
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/* on non-PCIe controllers we don't have pme_msg_det so this code
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/* on non-PCIe controllers we don't have pme_msg_det so this code
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* should do nothing since the read will return 0
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* should do nothing since the read will return 0
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*/
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*/
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@ -62,6 +62,7 @@ typedef struct pci_inbound_window {
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#define PIWAR_LOCAL 0x00f00000
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#define PIWAR_LOCAL 0x00f00000
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#define PIWAR_READ_SNOOP 0x00050000
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#define PIWAR_READ_SNOOP 0x00050000
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#define PIWAR_WRITE_SNOOP 0x00005000
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#define PIWAR_WRITE_SNOOP 0x00005000
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#define PIWAR_IWS_4K 0x0000000b
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u32 res2[3];
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u32 res2[3];
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} pit_t;
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} pit_t;
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@ -171,7 +172,7 @@ struct fsl_pci_info {
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};
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};
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int fsl_pci_init_port(struct fsl_pci_info *pci_info,
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int fsl_pci_init_port(struct fsl_pci_info *pci_info,
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struct pci_controller *hose, int busno);
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struct pci_controller *hose, int busno, int pcie_ep);
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#define SET_STD_PCI_INFO(x, num) \
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#define SET_STD_PCI_INFO(x, num) \
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{ \
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{ \
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