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https://github.com/Fishwaldo/u-boot.git
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imx8: Update SCFW API to version 1.5
Sync the latest SCFW API with below commit
6dcd0242ae7a53ac ("SCF-105: Revert accidental change") to add
interfaces for PM resource reset and read/write SNVS security
violation and tamper DGO registers.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li
Stefano Babic
parent
f959594db2
commit
73d769d8af
5 changed files with 126 additions and 21 deletions
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@ -8,6 +8,11 @@
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#define SC_RPC_H
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/* Note: Check SCFW API Released DOC before you want to modify something */
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/* Defines */
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#define SCFW_API_VERSION_MAJOR 1U
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#define SCFW_API_VERSION_MINOR 15U
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#define SC_RPC_VERSION 1U
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#define SC_RPC_MAX_MSG 8U
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@ -17,9 +22,13 @@
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#define RPC_SVC(MSG) ((MSG)->svc)
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#define RPC_FUNC(MSG) ((MSG)->func)
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#define RPC_R8(MSG) ((MSG)->func)
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#define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
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(s64)(RPC_U32((MSG), (IDX) + 4U))
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#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U])
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#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U])
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#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)])
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#define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
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(u64)(RPC_U32((MSG), (IDX) + 4U))
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#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U])
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#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U])
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#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)])
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@ -76,6 +85,8 @@ struct sc_rpc_msg_s {
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#define PM_FUNC_REBOOT 9U
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#define PM_FUNC_REBOOT_PARTITION 12U
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#define PM_FUNC_CPU_START 11U
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#define PM_FUNC_CPU_RESET 23U
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#define PM_FUNC_RESOURCE_RESET 29U
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#define PM_FUNC_IS_PARTITION_STARTED 24U
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/* MISC RPC */
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@ -160,26 +171,59 @@ struct sc_rpc_msg_s {
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#define RM_FUNC_DUMP 27U
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/* SECO RPC */
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#define SECO_FUNC_UNKNOWN 0
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#define SECO_FUNC_IMAGE_LOAD 1U
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#define SECO_FUNC_AUTHENTICATE 2U
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#define SECO_FUNC_FORWARD_LIFECYCLE 3U
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#define SECO_FUNC_RETURN_LIFECYCLE 4U
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#define SECO_FUNC_COMMIT 5U
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#define SECO_FUNC_ATTEST_MODE 6U
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#define SECO_FUNC_ATTEST 7U
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#define SECO_FUNC_GET_ATTEST_PKEY 8U
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#define SECO_FUNC_GET_ATTEST_SIGN 9U
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#define SECO_FUNC_ATTEST_VERIFY 10U
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#define SECO_FUNC_GEN_KEY_BLOB 11U
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#define SECO_FUNC_LOAD_KEY 12U
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#define SECO_FUNC_GET_MP_KEY 13U
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#define SECO_FUNC_UPDATE_MPMR 14U
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#define SECO_FUNC_GET_MP_SIGN 15U
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#define SECO_FUNC_BUILD_INFO 16U
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#define SECO_FUNC_CHIP_INFO 17U
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#define SECO_FUNC_ENABLE_DEBUG 18U
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#define SECO_FUNC_GET_EVENT 19U
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#define SECO_FUNC_FUSE_WRITE 20U
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#define SECO_FUNC_UNKNOWN 0 /* Unknown function */
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#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */
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#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */
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#define SECO_FUNC_ENH_AUTHENTICATE 24U /* Index for sc_seco_enh_authenticate() RPC call */
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#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */
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#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */
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#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */
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#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */
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#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */
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#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */
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#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */
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#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */
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#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */
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#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */
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#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */
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#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
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#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
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#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
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#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
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#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
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#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
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#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */
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#define SECO_FUNC_PATCH 21U /* Index for sc_seco_patch() RPC call */
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#define SECO_FUNC_START_RNG 22U /* Index for sc_seco_start_rng() RPC call */
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#define SECO_FUNC_SAB_MSG 23U /* Index for sc_seco_sab_msg() RPC call */
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#define SECO_FUNC_SECVIO_ENABLE 25U /* Index for sc_seco_secvio_enable() RPC call */
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#define SECO_FUNC_SECVIO_CONFIG 26U /* Index for sc_seco_secvio_config() RPC call */
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#define SECO_FUNC_SECVIO_DGO_CONFIG 27U /* Index for sc_seco_secvio_dgo_config() RPC call */
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/* IRQ RPC */
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#define IRQ_FUNC_UNKNOWN 0 /* Unknown function */
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#define IRQ_FUNC_ENABLE 1U /* Index for sc_irq_enable() RPC call */
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#define IRQ_FUNC_STATUS 2U /* Index for sc_irq_status() RPC call */
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/* TIMER RPC */
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#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
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#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */
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#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */
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#define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */
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#define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */
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#define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */
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#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for sc_timer_get_wdog_status() RPC call */
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#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for sc_timer_pt_get_wdog_status() RPC call */
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#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for sc_timer_set_wdog_action() RPC call */
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#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for sc_timer_set_rtc_time() RPC call */
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#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for sc_timer_get_rtc_time() RPC call */
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#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for sc_timer_get_rtc_sec1970() RPC call */
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#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for sc_timer_set_rtc_alarm() RPC call */
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#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for sc_timer_set_rtc_periodic_alarm() RPC call */
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#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for sc_timer_cancel_rtc_alarm() RPC call */
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#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for sc_timer_set_rtc_calb() RPC call */
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#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for sc_timer_set_sysctr_alarm() RPC call */
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#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */
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#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */
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#endif /* SC_RPC_H */
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@ -72,6 +72,7 @@ int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
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int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
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sc_faddr_t address);
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sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
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int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource);
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/* MISC API */
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int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
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@ -126,5 +127,6 @@ int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size);
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int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock);
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int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
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u16 msg_size, sc_faddr_t dst_addr, u16 dst_size);
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int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data);
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#endif
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@ -6,6 +6,9 @@
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#ifndef SC_PAD_API_H
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#define SC_PAD_API_H
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/* Defines for type widths */
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#define SC_PAD_MUX_W 3U /* Width of mux parameter */
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/* Defines for sc_pad_config_t */
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#define SC_PAD_CONFIG_NORMAL 0U /* Normal */
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#define SC_PAD_CONFIG_OD 1U /* Open Drain */
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@ -32,6 +32,7 @@ typedef u64 sc_ipc_t;
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#define SC_83MHZ 83333333U /* 83MHz */
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#define SC_84MHZ 84375000U /* 84.37MHz */
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#define SC_100MHZ 100000000U /* 100MHz */
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#define SC_114MHZ 114000000U /* 114MHz */
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#define SC_125MHZ 125000000U /* 125MHz */
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#define SC_133MHZ 133333333U /* 133MHz */
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#define SC_135MHZ 135000000U /* 135MHz */
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@ -52,6 +53,7 @@ typedef u64 sc_ipc_t;
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#define SC_372MHZ 372000000U /* 372MHz */
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#define SC_375MHZ 375000000U /* 375MHz */
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#define SC_400MHZ 400000000U /* 400MHz */
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#define SC_465MHZ 465000000U /* 465MHz */
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#define SC_500MHZ 500000000U /* 500MHz */
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#define SC_594MHZ 594000000U /* 594MHz */
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#define SC_625MHZ 625000000U /* 625MHz */
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@ -75,6 +77,7 @@ typedef u64 sc_ipc_t;
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#define SC_1500MHZ 1500000000U /* 1.5GHz */
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#define SC_1600MHZ 1600000000U /* 1.6GHz */
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#define SC_1800MHZ 1800000000U /* 1.8GHz */
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#define SC_1860MHZ 1860000000U /* 1.86GHz */
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#define SC_2000MHZ 2000000000U /* 2.0GHz */
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#define SC_2112MHZ 2112000000U /* 2.12GHz */
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@ -89,6 +92,7 @@ typedef u64 sc_ipc_t;
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#define SC_144MHZ 144000000U /* 144MHz */
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#define SC_192MHZ 192000000U /* 192MHz */
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#define SC_211MHZ 211200000U /* 211.2MHz */
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#define SC_228MHZ 228000000U /* 233MHz */
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#define SC_240MHZ 240000000U /* 240MHz */
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#define SC_264MHZ 264000000U /* 264MHz */
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#define SC_352MHZ 352000000U /* 352MHz */
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@ -96,11 +100,13 @@ typedef u64 sc_ipc_t;
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#define SC_384MHZ 384000000U /* 384MHz */
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#define SC_396MHZ 396000000U /* 396MHz */
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#define SC_432MHZ 432000000U /* 432MHz */
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#define SC_456MHZ 456000000U /* 466MHz */
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#define SC_480MHZ 480000000U /* 480MHz */
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#define SC_600MHZ 600000000U /* 600MHz */
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#define SC_744MHZ 744000000U /* 744MHz */
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#define SC_792MHZ 792000000U /* 792MHz */
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#define SC_864MHZ 864000000U /* 864MHz */
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#define SC_912MHZ 912000000U /* 912MHz */
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#define SC_960MHZ 960000000U /* 960MHz */
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#define SC_1056MHZ 1056000000U /* 1056MHz */
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#define SC_1104MHZ 1104000000U /* 1104MHz */
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@ -174,6 +174,28 @@ sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt)
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return !!result;
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}
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int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource)
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{
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struct udevice *dev = gd->arch.scu_dev;
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int size = sizeof(struct sc_rpc_msg_s);
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struct sc_rpc_msg_s msg;
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int ret;
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RPC_VER(&msg) = SC_RPC_VERSION;
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RPC_SIZE(&msg) = 2U;
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RPC_SVC(&msg) = (u8)(SC_RPC_SVC_PM);
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RPC_FUNC(&msg) = (u8)(PM_FUNC_RESOURCE_RESET);
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RPC_U16(&msg, 0U) = (u16)(resource);
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ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
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if (ret)
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printf("%s: resource:%d res:%d\n",
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__func__, resource, RPC_R8(&msg));
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return ret;
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}
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/* PAD */
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int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val)
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{
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@ -1028,3 +1050,31 @@ int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
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return ret;
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}
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int sc_seco_secvio_dgo_config(sc_ipc_t ipc, uint8_t id, uint8_t access,
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u32 *data)
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{
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struct udevice *dev = gd->arch.scu_dev;
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struct sc_rpc_msg_s msg;
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int size = sizeof(struct sc_rpc_msg_s);
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int ret;
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RPC_VER(&msg) = SC_RPC_VERSION;
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RPC_SIZE(&msg) = 3U;
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RPC_SVC(&msg) = (u8)(SC_RPC_SVC_SECO);
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RPC_FUNC(&msg) = (u8)(SECO_FUNC_SECVIO_DGO_CONFIG);
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RPC_U32(&msg, 0U) = (u32)(*data);
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RPC_U8(&msg, 4U) = (u8)(id);
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RPC_U8(&msg, 5U) = (u8)(access);
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ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
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if (ret)
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printf("%s, id:0x%x, access:%x, res:%d\n",
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__func__, id, access, RPC_R8(&msg));
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if (data)
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*data = RPC_U32(&msg, 0U);
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return ret;
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}
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