mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 14:41:31 +00:00
Merge branch 'inka4x0-ng' of /home/m8/git/u-boot/
This commit is contained in:
Wolfgang Denk
commit
74ac5facb9
9 changed files with 133 additions and 476 deletions
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o flash.o
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COBJS := $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -1,432 +0,0 @@
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/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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||||||
*
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||||||
* (C) Copyright 2004
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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||||||
* You should have received a copy of the GNU General Public License
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||||||
* along with this program; if not, write to the Free Software
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||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*
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* CPU to flash interface is 8-bit, so make declaration accordingly
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*/
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typedef unsigned char FLASH_PORT_WIDTH;
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typedef volatile unsigned char FLASH_PORT_WIDTHV;
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define FLASH_CYCLE1 0x0555
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#define FLASH_CYCLE2 0x02aa
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size(FPWV *addr, flash_info_t *info);
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static void flash_reset(flash_info_t *info);
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static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
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static flash_info_t *flash_get_info(ulong base);
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/*-----------------------------------------------------------------------
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* flash_init()
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*
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* sets up flash_info and returns size of FLASH (bytes)
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*/
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unsigned long flash_init (void)
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{
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unsigned long size = 0;
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extern void flash_preinit(void);
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ulong flashbase = CFG_FLASH_BASE;
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flash_preinit();
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/* Init: no FLASHes known */
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memset(&flash_info[0], 0, sizeof(flash_info_t));
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flash_info[0].size =
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flash_get_size((FPW *)flashbase, &flash_info[0]);
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size = flash_info[0].size;
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CFG_MONITOR_BASE,
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CFG_MONITOR_BASE+monitor_flash_len-1,
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flash_get_info(CFG_MONITOR_BASE));
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#endif
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#ifdef CFG_ENV_IS_IN_FLASH
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/* ENV protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR+CFG_ENV_SIZE-1,
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flash_get_info(CFG_ENV_ADDR));
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#endif
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return size ? size : 1;
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_reset(flash_info_t *info)
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{
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FPWV *base = (FPWV *)(info->start[0]);
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/* Put FLASH back in read mode */
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
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*base = (FPW)0x00FF00FF; /* Intel Read Mode */
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else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
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*base = (FPW)0x00F000F0; /* AMD Read Mode */
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}
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/*-----------------------------------------------------------------------
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*/
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static flash_info_t *flash_get_info(ulong base)
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{
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int i;
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flash_info_t * info;
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
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info = & flash_info[i];
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if (info->size && info->start[0] <= base &&
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base <= info->start[0] + info->size - 1)
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break;
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}
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return i == CFG_MAX_FLASH_BANKS ? 0 : info;
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
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case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
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case FLASH_MAN_SST: printf ("SST "); break;
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case FLASH_MAN_STM: printf ("STM "); break;
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case FLASH_MAN_INTEL: printf ("INTEL "); break;
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default: printf ("Unknown Vendor "); break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM116DB:
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printf ("AM29LV116DB (16Mbit, bottom boot sect)\n");
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break;
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case FLASH_AMLV128U:
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printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
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break;
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case FLASH_AM160B:
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printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
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break;
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default:
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printf ("Unknown Chip Type\n");
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||||||
break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20,
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info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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if ((i % 5) == 0) {
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printf ("\n ");
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}
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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return;
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}
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/*-----------------------------------------------------------------------
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*/
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/*
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* The following code cannot be run from FLASH!
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*/
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ulong flash_get_size (FPWV *addr, flash_info_t *info)
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{
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int i;
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ulong base = (ulong)addr;
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/* Write auto select command: read Manufacturer ID */
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/* Write auto select command sequence and test FLASH answer */
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addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
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addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
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addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
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/* The manufacturer codes are only 1 byte, so just use 1 byte.
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* This works for any bus width and any FLASH device width.
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*/
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udelay(100);
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switch (addr[0] & 0xff) {
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case (uchar)AMD_MANUFACT:
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debug ("Manufacturer: AMD (Spansion)\n");
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info->flash_id = FLASH_MAN_AMD;
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break;
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case (uchar)INTEL_MANUFACT:
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debug ("Manufacturer: Intel (not supported yet)\n");
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info->flash_id = FLASH_MAN_INTEL;
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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||||||
info->size = 0;
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break;
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||||||
}
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|
||||||
|
|
||||||
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
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if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
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||||||
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||||||
case (uchar)AMD_ID_LV116DB:
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||||||
debug ("Chip: AM29LV116DB\n");
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info->flash_id += FLASH_AM116DB;
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info->sector_count = 35;
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info->size = 0x00200000;
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/*
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* The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
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||||||
* the other ones are 64 kB
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||||||
*/
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||||||
info->start[0] = base + 0x00000000;
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||||||
info->start[1] = base + 0x00004000;
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|
||||||
info->start[2] = base + 0x00006000;
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|
||||||
info->start[3] = base + 0x00008000;
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|
||||||
for( i = 4; i < info->sector_count; i++ )
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|
||||||
info->start[i] =
|
|
||||||
base + (i * (64 << 10)) - 0x00030000;
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|
||||||
break; /* => 2 MB */
|
|
||||||
|
|
||||||
case (FPW)AMD_ID_LV160B:
|
|
||||||
debug ("Chip: AM29LV160MB\n");
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|
||||||
info->flash_id += FLASH_AM160B;
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|
||||||
info->sector_count = 35;
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|
||||||
info->size = 0x00400000;
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|
||||||
/*
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|
||||||
* The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
|
|
||||||
* the other ones are 64 kB
|
|
||||||
*/
|
|
||||||
info->start[0] = base + 0x00000000;
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|
||||||
info->start[1] = base + 0x00008000;
|
|
||||||
info->start[2] = base + 0x0000C000;
|
|
||||||
info->start[3] = base + 0x00010000;
|
|
||||||
for( i = 4; i < info->sector_count; i++ )
|
|
||||||
info->start[i] =
|
|
||||||
base + (i * 2 * (64 << 10)) - 0x00060000;
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|
||||||
break; /* => 4 MB */
|
|
||||||
|
|
||||||
default:
|
|
||||||
info->flash_id = FLASH_UNKNOWN;
|
|
||||||
info->sector_count = 0;
|
|
||||||
info->size = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Put FLASH back in read mode */
|
|
||||||
flash_reset(info);
|
|
||||||
|
|
||||||
return (info->size);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
|
||||||
{
|
|
||||||
FPWV *addr = (FPWV*)(info->start[0]);
|
|
||||||
int flag, prot, sect, l_sect;
|
|
||||||
ulong start, now, last;
|
|
||||||
|
|
||||||
debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
|
|
||||||
|
|
||||||
if ((s_first < 0) || (s_first > s_last)) {
|
|
||||||
if (info->flash_id == FLASH_UNKNOWN) {
|
|
||||||
printf ("- missing\n");
|
|
||||||
} else {
|
|
||||||
printf ("- no sectors to erase\n");
|
|
||||||
}
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
if ((info->flash_id == FLASH_UNKNOWN) ||
|
|
||||||
(info->flash_id > FLASH_AMD_COMP)) {
|
|
||||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
|
||||||
info->flash_id);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
prot = 0;
|
|
||||||
for (sect=s_first; sect<=s_last; ++sect) {
|
|
||||||
if (info->protect[sect]) {
|
|
||||||
prot++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (prot) {
|
|
||||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
|
||||||
prot);
|
|
||||||
} else {
|
|
||||||
printf ("\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
l_sect = -1;
|
|
||||||
|
|
||||||
/* Disable interrupts which might cause a timeout here */
|
|
||||||
flag = disable_interrupts();
|
|
||||||
|
|
||||||
addr[0x0555] = (FPW)0x00AA00AA;
|
|
||||||
addr[0x02AA] = (FPW)0x00550055;
|
|
||||||
addr[0x0555] = (FPW)0x00800080;
|
|
||||||
addr[0x0555] = (FPW)0x00AA00AA;
|
|
||||||
addr[0x02AA] = (FPW)0x00550055;
|
|
||||||
|
|
||||||
/* Start erase on unprotected sectors */
|
|
||||||
for (sect = s_first; sect<=s_last; sect++) {
|
|
||||||
if (info->protect[sect] == 0) { /* not protected */
|
|
||||||
addr = (FPWV*)(info->start[sect]);
|
|
||||||
addr[0] = (FPW)0x00300030;
|
|
||||||
l_sect = sect;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* re-enable interrupts if necessary */
|
|
||||||
if (flag)
|
|
||||||
enable_interrupts();
|
|
||||||
|
|
||||||
/* wait at least 80us - let's wait 1 ms */
|
|
||||||
udelay (1000);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* We wait for the last triggered sector
|
|
||||||
*/
|
|
||||||
if (l_sect < 0)
|
|
||||||
goto DONE;
|
|
||||||
|
|
||||||
start = get_timer (0);
|
|
||||||
last = start;
|
|
||||||
addr = (FPWV*)(info->start[l_sect]);
|
|
||||||
while ((addr[0] & (FPW)0x00800080) != (FPW)0x00800080) {
|
|
||||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
|
||||||
printf ("Timeout\n");
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
/* show that we're waiting */
|
|
||||||
if ((now - last) > 1000) { /* every second */
|
|
||||||
putc ('.');
|
|
||||||
last = now;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
DONE:
|
|
||||||
/* reset to read mode */
|
|
||||||
addr = (FPWV*)info->start[0];
|
|
||||||
addr[0] = (FPW)0x00F000F0; /* reset bank */
|
|
||||||
|
|
||||||
printf (" done\n");
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Copy memory to flash, returns:
|
|
||||||
* 0 - OK
|
|
||||||
* 1 - write timeout
|
|
||||||
* 2 - Flash not erased
|
|
||||||
*/
|
|
||||||
|
|
||||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
|
||||||
{
|
|
||||||
int i, rc = 0;
|
|
||||||
|
|
||||||
for (i = 0; i < cnt; i++)
|
|
||||||
if ((rc = write_word_amd(info, (FPW *)(addr+i), src[i])) != 0) {
|
|
||||||
return (rc);
|
|
||||||
}
|
|
||||||
|
|
||||||
return rc;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Write a word to Flash for AMD FLASH
|
|
||||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank
|
|
||||||
* (not an individual chip) is.
|
|
||||||
*
|
|
||||||
* returns:
|
|
||||||
* 0 - OK
|
|
||||||
* 1 - write timeout
|
|
||||||
* 2 - Flash not erased
|
|
||||||
*/
|
|
||||||
static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
|
|
||||||
{
|
|
||||||
ulong start;
|
|
||||||
int flag;
|
|
||||||
FPWV *base; /* first address in flash bank */
|
|
||||||
|
|
||||||
/* Check if Flash is (sufficiently) erased */
|
|
||||||
if ((*dest & data) != data) {
|
|
||||||
return (2);
|
|
||||||
}
|
|
||||||
|
|
||||||
base = (FPWV *)(info->start[0]);
|
|
||||||
|
|
||||||
/* Disable interrupts which might cause a timeout here */
|
|
||||||
flag = disable_interrupts();
|
|
||||||
|
|
||||||
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
|
|
||||||
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
|
|
||||||
base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
|
|
||||||
|
|
||||||
*dest = data; /* start programming the data */
|
|
||||||
|
|
||||||
/* re-enable interrupts if necessary */
|
|
||||||
if (flag)
|
|
||||||
enable_interrupts();
|
|
||||||
|
|
||||||
start = get_timer (0);
|
|
||||||
|
|
||||||
/* data polling for D7 */
|
|
||||||
while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
|
|
||||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
|
||||||
*dest = (FPW)0x00F000F0; /* reset bank */
|
|
||||||
return (1);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
32
board/inka4x0/hyb25d512160bf-5.h
Normal file
32
board/inka4x0/hyb25d512160bf-5.h
Normal file
|
|
@ -0,0 +1,32 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007 Semihalf
|
||||||
|
* Written by Marian Balakowicz <m8@semihalf.com>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDRAM_DDR 1 /* is DDR */
|
||||||
|
|
||||||
|
/* Settings for XLB = 132 MHz */
|
||||||
|
#define SDRAM_MODE 0x018D0000
|
||||||
|
#define SDRAM_EMODE 0x40090000
|
||||||
|
#define SDRAM_CONTROL 0x714F0F00
|
||||||
|
#define SDRAM_CONFIG1 0x73711930
|
||||||
|
#define SDRAM_CONFIG2 0x46770000
|
||||||
|
#define SDRAM_TAPDELAY 0x10000000
|
||||||
|
|
@ -31,10 +31,18 @@
|
||||||
#include <mpc5xxx.h>
|
#include <mpc5xxx.h>
|
||||||
#include <pci.h>
|
#include <pci.h>
|
||||||
|
|
||||||
#if defined(CONFIG_MPC5200_DDR)
|
#if defined(CONFIG_DDR_MT46V16M16)
|
||||||
#include "mt46v16m16-75.h"
|
#include "mt46v16m16-75.h"
|
||||||
#else
|
#elif defined(CONFIG_SDR_MT48LC16M16A2)
|
||||||
#include "mt48lc16m16a2-75.h"
|
#include "mt48lc16m16a2-75.h"
|
||||||
|
#elif defined(CONFIG_DDR_MT46V32M16)
|
||||||
|
#include "mt46v32m16.h"
|
||||||
|
#elif defined(CONFIG_DDR_HYB25D512160BF)
|
||||||
|
#include "hyb25d512160bf.h"
|
||||||
|
#elif defined(CONFIG_DDR_K4H511638C)
|
||||||
|
#include "k4h511638c.h"
|
||||||
|
#else
|
||||||
|
#error "INKA4x0 SDRAM: invalid chip type specified!"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef CFG_RAMBOOT
|
#ifndef CFG_RAMBOOT
|
||||||
|
|
@ -88,7 +96,7 @@ long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
ulong dramsize = 0;
|
ulong dramsize = 0;
|
||||||
#ifndef CFG_RAMBOOT
|
#ifndef CFG_RAMBOOT
|
||||||
ulong test1, test2;
|
long test1, test2;
|
||||||
|
|
||||||
/* setup SDRAM chip selects */
|
/* setup SDRAM chip selects */
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
|
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
|
||||||
|
|
@ -108,9 +116,9 @@ long int initdram (int board_type)
|
||||||
|
|
||||||
/* find RAM size using SDRAM CS0 only */
|
/* find RAM size using SDRAM CS0 only */
|
||||||
sdram_start(0);
|
sdram_start(0);
|
||||||
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
|
test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
|
||||||
sdram_start(1);
|
sdram_start(1);
|
||||||
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
|
test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
|
||||||
if (test1 > test2) {
|
if (test1 > test2) {
|
||||||
sdram_start(0);
|
sdram_start(0);
|
||||||
dramsize = test1;
|
dramsize = test1;
|
||||||
|
|
@ -175,7 +183,7 @@ void flash_preinit(void)
|
||||||
|
|
||||||
int misc_init_f (void)
|
int misc_init_f (void)
|
||||||
{
|
{
|
||||||
uchar tmp[10];
|
char tmp[10];
|
||||||
int i, br;
|
int i, br;
|
||||||
|
|
||||||
i = getenv_r("brightness", tmp, sizeof(tmp));
|
i = getenv_r("brightness", tmp, sizeof(tmp));
|
||||||
|
|
|
||||||
32
board/inka4x0/k4h511638c.h
Normal file
32
board/inka4x0/k4h511638c.h
Normal file
|
|
@ -0,0 +1,32 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007 Semihalf
|
||||||
|
* Written by Marian Balakowicz <m8@semihalf.com>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDRAM_DDR 1 /* is DDR */
|
||||||
|
|
||||||
|
/* Settings for XLB = 132 MHz */
|
||||||
|
#define SDRAM_MODE 0x018D0000
|
||||||
|
#define SDRAM_EMODE 0x40090000
|
||||||
|
#define SDRAM_CONTROL 0x714F0F00
|
||||||
|
#define SDRAM_CONFIG1 0x73722930
|
||||||
|
#define SDRAM_CONFIG2 0x46770000
|
||||||
|
#define SDRAM_TAPDELAY 0x10000000
|
||||||
|
|
@ -23,15 +23,10 @@
|
||||||
|
|
||||||
#define SDRAM_DDR 1 /* is DDR */
|
#define SDRAM_DDR 1 /* is DDR */
|
||||||
|
|
||||||
#if defined(CONFIG_MPC5200)
|
|
||||||
/* Settings for XLB = 132 MHz */
|
/* Settings for XLB = 132 MHz */
|
||||||
#define SDRAM_MODE 0x018D0000
|
#define SDRAM_MODE 0x018D0000
|
||||||
#define SDRAM_EMODE 0x40090000
|
#define SDRAM_EMODE 0x40090000
|
||||||
#define SDRAM_CONTROL 0x714f0f00
|
#define SDRAM_CONTROL 0x714F0F00
|
||||||
#define SDRAM_CONFIG1 0x73722930
|
#define SDRAM_CONFIG1 0x73722930
|
||||||
#define SDRAM_CONFIG2 0x47770000
|
#define SDRAM_CONFIG2 0x47770000
|
||||||
#define SDRAM_TAPDELAY 0x10000000
|
#define SDRAM_TAPDELAY 0x10000000
|
||||||
|
|
||||||
#else
|
|
||||||
#error CONFIG_MPC5200 not defined
|
|
||||||
#endif
|
|
||||||
|
|
|
||||||
32
board/inka4x0/mt46v32m16-75.h
Normal file
32
board/inka4x0/mt46v32m16-75.h
Normal file
|
|
@ -0,0 +1,32 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007 Semihalf
|
||||||
|
* Written by Marian Balakowicz <m8@semihalf.com>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDRAM_DDR 1 /* is DDR */
|
||||||
|
|
||||||
|
/* Settings for XLB = 132 MHz */
|
||||||
|
#define SDRAM_MODE 0x018D0000
|
||||||
|
#define SDRAM_EMODE 0x40090000
|
||||||
|
#define SDRAM_CONTROL 0x714F0F00
|
||||||
|
#define SDRAM_CONFIG1 0x73711930
|
||||||
|
#define SDRAM_CONFIG2 0x46770000
|
||||||
|
#define SDRAM_TAPDELAY 0x10000000
|
||||||
|
|
@ -21,27 +21,10 @@
|
||||||
* MA 02111-1307 USA
|
* MA 02111-1307 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define SDRAM_DDR 1 /* is SDR */
|
#define SDRAM_DDR 0 /* is SDR */
|
||||||
|
|
||||||
#if defined(CONFIG_MPC5200)
|
|
||||||
/* Settings for XLB = 132 MHz */
|
/* Settings for XLB = 132 MHz */
|
||||||
#define SDRAM_MODE 0x00CD0000
|
#define SDRAM_MODE 0x00CD0000
|
||||||
/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
|
|
||||||
#define SDRAM_CONTROL 0x504F0000
|
#define SDRAM_CONTROL 0x504F0000
|
||||||
#define SDRAM_CONFIG1 0xD2322800
|
#define SDRAM_CONFIG1 0xD2322800
|
||||||
/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */
|
|
||||||
/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
|
|
||||||
#define SDRAM_CONFIG2 0x8AD70000
|
#define SDRAM_CONFIG2 0x8AD70000
|
||||||
/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
|
|
||||||
|
|
||||||
#elif defined(CONFIG_MGT5100)
|
|
||||||
/* Settings for XLB = 66 MHz */
|
|
||||||
#define SDRAM_MODE 0x008D0000
|
|
||||||
#define SDRAM_CONTROL 0x504F0000
|
|
||||||
#define SDRAM_CONFIG1 0xC2222600
|
|
||||||
#define SDRAM_CONFIG2 0x88B70004
|
|
||||||
#define SDRAM_ADDRSEL 0x02000000
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
|
|
||||||
#endif
|
|
||||||
|
|
|
||||||
|
|
@ -142,7 +142,7 @@
|
||||||
"cp.l 100000 f0000b28 1\0" \
|
"cp.l 100000 f0000b28 1\0" \
|
||||||
"ideargs=setenv bootargs root=/dev/hda1 rw\0" \
|
"ideargs=setenv bootargs root=/dev/hda1 rw\0" \
|
||||||
"ide_boot=ext2load ide 0:1 200000 uImage;" \
|
"ide_boot=ext2load ide 0:1 200000 uImage;" \
|
||||||
"run ideargs addip addcons enable_disp;bootm" \
|
"run ideargs addip addcons enable_disp;bootm\0" \
|
||||||
"brightness=255\0" \
|
"brightness=255\0" \
|
||||||
""
|
""
|
||||||
|
|
||||||
|
|
@ -156,24 +156,24 @@
|
||||||
/*
|
/*
|
||||||
* Flash configuration
|
* Flash configuration
|
||||||
*/
|
*/
|
||||||
#define CFG_FLASH_BASE 0xFFE00000
|
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
|
||||||
|
#define CFG_FLASH_CFI_DRIVER 1
|
||||||
#define CFG_FLASH_SIZE 0x00200000 /* 2 MByte */
|
#define CFG_FLASH_BASE 0xffe00000
|
||||||
#define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */
|
#define CFG_FLASH_SIZE 0x00200000
|
||||||
|
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
|
||||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) /* second sector */
|
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
|
||||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
|
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
|
||||||
(= chip selects) */
|
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
|
||||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Environment settings
|
* Environment settings
|
||||||
*/
|
*/
|
||||||
#define CFG_ENV_IS_IN_FLASH 1
|
#define CFG_ENV_IS_IN_FLASH 1
|
||||||
|
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
|
||||||
#define CFG_ENV_SIZE 0x2000
|
#define CFG_ENV_SIZE 0x2000
|
||||||
#define CFG_ENV_SECT_SIZE 0x2000
|
#define CFG_ENV_SECT_SIZE 0x2000
|
||||||
#define CONFIG_ENV_OVERWRITE 1
|
#define CONFIG_ENV_OVERWRITE 1
|
||||||
|
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Memory map
|
* Memory map
|
||||||
|
|
@ -182,7 +182,14 @@
|
||||||
#define CFG_SDRAM_BASE 0x00000000
|
#define CFG_SDRAM_BASE 0x00000000
|
||||||
#define CFG_DEFAULT_MBAR 0x80000000
|
#define CFG_DEFAULT_MBAR 0x80000000
|
||||||
|
|
||||||
#define CONFIG_MPC5200_DDR
|
/*
|
||||||
|
* SDRAM controller configuration
|
||||||
|
*/
|
||||||
|
#undef CONFIG_SDR_MT48LC16M16A2
|
||||||
|
#undef CONFIG_DDR_MT46V16M16
|
||||||
|
#undef CONFIG_DDR_MT46V32M16
|
||||||
|
#undef CONFIG_DDR_HYB25D512160BF
|
||||||
|
#define CONFIG_DDR_K4H511638C
|
||||||
|
|
||||||
/* Use ON-Chip SRAM until RAM will be available */
|
/* Use ON-Chip SRAM until RAM will be available */
|
||||||
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
|
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||||
|
|
@ -203,7 +210,7 @@
|
||||||
# define CFG_RAMBOOT 1
|
# define CFG_RAMBOOT 1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue