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ddr: marvell: axp: fix array types have different bounds warning
The arrays `pbs_dq_mapping`, `div_ratio1to1` and `div_ratio2to1` have different bounds declared in header files where these variables are also defined from the ones declared in source files. This causes the compiler to complain (when building with LTO): ddr3_sdram.c:24:12: warning: type of ‘pbs_dq_mapping’ does not match original declaration [-Wlto-type-mismatch] ddr3_patterns_64bit.h:911:5: note: array types have different bounds ddr3_patterns_64bit.h:911:5: note: ‘pbs_dq_mapping’ was previously declared here ddr3_dfs.c:45:11: warning: type of ‘div_ratio1to1’ does not match original declaration [-Wlto-type-mismatch] ddr3_axp_vars.h:167:4: note: array types have different bounds ddr3_axp_vars.h:167:4: note: ‘div_ratio1to1’ was previously declared here ddr3_dfs.c:46:11: warning: type of ‘div_ratio2to1’ does not match original declaration [-Wlto-type-mismatch] ddr3_axp_vars.h:196:4: note: array types have different bounds ddr3_axp_vars.h:196:4: note: ‘div_ratio2to1’ was previously declared here CI managed to trigger this as an error when compiling with LTO for AXP. Fix this by using values from the header files, which seem to be the correct ones. Signed-off-by: Marek Behún <marek.behun@nic.cz>
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2 changed files with 3 additions and 3 deletions
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@ -42,8 +42,8 @@ extern u8 div_ratio[CLK_VCO][CLK_DDR];
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extern void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
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#else
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extern u16 odt_dynamic[ODT_OPT][MAX_CS];
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extern u8 div_ratio1to1[CLK_CPU][CLK_DDR];
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extern u8 div_ratio2to1[CLK_CPU][CLK_DDR];
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extern u8 div_ratio1to1[CLK_VCO][CLK_DDR];
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extern u8 div_ratio2to1[CLK_VCO][CLK_DDR];
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#endif
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extern u16 odt_static[ODT_OPT][MAX_CS];
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@ -21,7 +21,7 @@ extern u32 pbs_pattern_32b[2][LEN_PBS_PATTERN];
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#if defined(MV88F78X60)
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extern u32 pbs_pattern_64b[2][LEN_PBS_PATTERN];
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#endif
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extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM];
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extern u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM];
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#if defined(MV88F78X60) || defined(MV88F672X)
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/* PBS locked dq (per pup) */
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