Merge branch 'master' of git://git.denx.de/u-boot-mmc

arch/arm/mach-rmobile/include/mach/sh_sdhi.h

@@ -1,9 +1,9 @@
 /*
  * drivers/mmc/sh-sdhi.h
  *
- * SD/MMC driver for Reneas rmobile ARM SoCs
+ * SD/MMC driver for Renesas rmobile ARM SoCs
  *
- * Copyright (C) 2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2013-2017 Renesas Electronics Corporation
  * Copyright (C) 2008-2009 Renesas Solutions Corp.
  *
  * SPDX-License-Identifier:	GPL-2.0
@@ -50,8 +50,10 @@
 /* SDHI CMD VALUE */
 #define CMD_MASK			0x0000ffff
 #define SDHI_APP			0x0040
+#define SDHI_MMC_SEND_OP_COND		0x0701
 #define SDHI_SD_APP_SEND_SCR		0x0073
 #define SDHI_SD_SWITCH			0x1C06
+#define SDHI_MMC_SEND_EXT_CSD		0x1C08
 
 /* SDHI_PORTSEL */
 #define USE_1PORT			(1 << 8) /* 1 port */
@@ -120,7 +122,10 @@
 #define CLK_ENABLE			(1 << 8)
 
 /* SDHI_OPTION */
-#define OPT_BUS_WIDTH_1			(1 << 15)	/* bus width = 1 bit */
+#define OPT_BUS_WIDTH_M			(5 << 13)	/* 101b (15-13bit) */
+#define OPT_BUS_WIDTH_1			(4 << 13)	/* bus width = 1 bit */
+#define OPT_BUS_WIDTH_4			(0 << 13)	/* bus width = 4 bit */
+#define OPT_BUS_WIDTH_8			(1 << 13)	/* bus width = 8 bit */
 
 /* SDHI_ERR_STS1 */
 #define ERR_STS1_CRC_ERROR		((1 << 11) | (1 << 10) | (1 << 9) | \
@@ -162,7 +167,9 @@
 #define	CLKDEV_INIT			400000		/* 100 - 400 KHz */
 
 /* For quirk */
-#define SH_SDHI_QUIRK_16BIT_BUF		(1)
+#define SH_SDHI_QUIRK_16BIT_BUF		BIT(0)
+#define SH_SDHI_QUIRK_64BIT_BUF		BIT(1)
+
 int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks);
 
 #endif /* _SH_SDHI_H */

board/ti/am43xx/board.c

@@ -422,6 +422,13 @@ void scale_vcores_generic(u32 m)
 		printf("%s failure\n", __func__);
 		return;
 	}
+
+	/* Set DCDC3 (DDR) voltage */
+	if (tps65218_voltage_update(TPS65218_DCDC3,
+	    TPS65218_DCDC3_VOLT_SEL_1350MV)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
 }
 
 void scale_vcores_idk(u32 m)

common/env_mmc.c

@@ -121,7 +121,12 @@ static const char *init_mmc_for_env(struct mmc *mmc)
 	if (!mmc)
 		return "!No MMC card found";
 
-#ifndef CONFIG_BLK
+#ifdef CONFIG_BLK
+	struct udevice *dev;
+
+	if (blk_get_from_parent(mmc->dev, &dev))
+		return "!No block device";
+#else
 	if (mmc_init(mmc))
 		return "!MMC init failed";
 #endif

drivers/block/blk-uclass.c

@@ -453,6 +453,32 @@ int blk_prepare_device(struct udevice *dev)
 	return 0;
 }
 
+int blk_get_from_parent(struct udevice *parent, struct udevice **devp)
+{
+	struct udevice *dev;
+	enum uclass_id id;
+	int ret;
+
+	device_find_first_child(parent, &dev);
+	if (!dev) {
+		debug("%s: No block device found for parent '%s'\n", __func__,
+		      parent->name);
+		return -ENODEV;
+	}
+	id = device_get_uclass_id(dev);
+	if (id != UCLASS_BLK) {
+		debug("%s: Incorrect uclass %s for block device '%s'\n",
+		      __func__, uclass_get_name(id), dev->name);
+		return -ENOTBLK;
+	}
+	ret = device_probe(dev);
+	if (ret)
+		return ret;
+	*devp = dev;
+
+	return 0;
+}
+
 int blk_find_max_devnum(enum if_type if_type)
 {
 	struct udevice *dev;

drivers/mmc/Kconfig

@@ -156,7 +156,7 @@ config MMC_OMAP36XX_PINS
 
 config SH_SDHI
 	bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
-	depends on RMOBILE
+	depends on ARCH_RMOBILE
 	help
 	  Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform
 

drivers/mmc/mmc-uclass.c

@@ -97,7 +97,7 @@ struct mmc *find_mmc_device(int dev_num)
 	struct udevice *dev, *mmc_dev;
 	int ret;
 
-	ret = blk_get_device(IF_TYPE_MMC, dev_num, &dev);
+	ret = blk_find_device(IF_TYPE_MMC, dev_num, &dev);
 
 	if (ret) {
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
@@ -108,7 +108,9 @@ struct mmc *find_mmc_device(int dev_num)
 
 	mmc_dev = dev_get_parent(dev);
 
-	return mmc_get_mmc_dev(mmc_dev);
+	struct mmc *mmc = mmc_get_mmc_dev(mmc_dev);
+
+	return mmc;
 }
 
 int get_mmc_num(void)

drivers/mmc/sh_sdhi.c

@@ -3,7 +3,7 @@
  *
  * SD/MMC driver for Renesas rmobile ARM SoCs.
  *
- * Copyright (C) 2011,2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2011,2013-2017 Renesas Electronics Corporation
  * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  * Copyright (C) 2008-2009 Renesas Solutions Corp.
  *
@@ -29,6 +29,17 @@ struct sh_sdhi_host {
 	unsigned char sd_error;
 	unsigned char detect_waiting;
 };
+
+static inline void sh_sdhi_writeq(struct sh_sdhi_host *host, int reg, u64 val)
+{
+	writeq(val, host->addr + (reg << host->bus_shift));
+}
+
+static inline u64 sh_sdhi_readq(struct sh_sdhi_host *host, int reg)
+{
+	return readq(host->addr + (reg << host->bus_shift));
+}
+
 static inline void sh_sdhi_writew(struct sh_sdhi_host *host, int reg, u16 val)
 {
 	writew(val, host->addr + (reg << host->bus_shift));
@@ -261,6 +272,7 @@ static int sh_sdhi_single_read(struct sh_sdhi_host *host, struct mmc_data *data)
 	long time;
 	unsigned short blocksize, i;
 	unsigned short *p = (unsigned short *)data->dest;
+	u64 *q = (u64 *)data->dest;
 
 	if ((unsigned long)p & 0x00000001) {
 		debug(DRIVER_NAME": %s: The data pointer is unaligned.",
@@ -281,8 +293,12 @@ static int sh_sdhi_single_read(struct sh_sdhi_host *host, struct mmc_data *data)
 
 	host->wait_int = 0;
 	blocksize = sh_sdhi_readw(host, SDHI_SIZE);
-	for (i = 0; i < blocksize / 2; i++)
+	if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
-		*p++ = sh_sdhi_readw(host, SDHI_BUF0);
+		for (i = 0; i < blocksize / 8; i++)
+			*q++ = sh_sdhi_readq(host, SDHI_BUF0);
+	else
+		for (i = 0; i < blocksize / 2; i++)
+			*p++ = sh_sdhi_readw(host, SDHI_BUF0);
 
 	time = sh_sdhi_wait_interrupt_flag(host);
 	if (time == 0 || host->sd_error != 0)
@@ -297,6 +313,7 @@ static int sh_sdhi_multi_read(struct sh_sdhi_host *host, struct mmc_data *data)
 	long time;
 	unsigned short blocksize, i, sec;
 	unsigned short *p = (unsigned short *)data->dest;
+	u64 *q = (u64 *)data->dest;
 
 	if ((unsigned long)p & 0x00000001) {
 		debug(DRIVER_NAME": %s: The data pointer is unaligned.",
@@ -319,8 +336,12 @@ static int sh_sdhi_multi_read(struct sh_sdhi_host *host, struct mmc_data *data)
 
 		host->wait_int = 0;
 		blocksize = sh_sdhi_readw(host, SDHI_SIZE);
-		for (i = 0; i < blocksize / 2; i++)
+		if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
-			*p++ = sh_sdhi_readw(host, SDHI_BUF0);
+			for (i = 0; i < blocksize / 8; i++)
+				*q++ = sh_sdhi_readq(host, SDHI_BUF0);
+		else
+			for (i = 0; i < blocksize / 2; i++)
+				*p++ = sh_sdhi_readw(host, SDHI_BUF0);
 	}
 
 	return 0;
@@ -332,6 +353,7 @@ static int sh_sdhi_single_write(struct sh_sdhi_host *host,
 	long time;
 	unsigned short blocksize, i;
 	const unsigned short *p = (const unsigned short *)data->src;
+	const u64 *q = (const u64 *)data->src;
 
 	if ((unsigned long)p & 0x00000001) {
 		debug(DRIVER_NAME": %s: The data pointer is unaligned.",
@@ -356,8 +378,12 @@ static int sh_sdhi_single_write(struct sh_sdhi_host *host,
 
 	host->wait_int = 0;
 	blocksize = sh_sdhi_readw(host, SDHI_SIZE);
-	for (i = 0; i < blocksize / 2; i++)
+	if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
-		sh_sdhi_writew(host, SDHI_BUF0, *p++);
+		for (i = 0; i < blocksize / 8; i++)
+			sh_sdhi_writeq(host, SDHI_BUF0, *q++);
+	else
+		for (i = 0; i < blocksize / 2; i++)
+			sh_sdhi_writew(host, SDHI_BUF0, *p++);
 
 	time = sh_sdhi_wait_interrupt_flag(host);
 	if (time == 0 || host->sd_error != 0)
@@ -372,6 +398,7 @@ static int sh_sdhi_multi_write(struct sh_sdhi_host *host, struct mmc_data *data)
 	long time;
 	unsigned short i, sec, blocksize;
 	const unsigned short *p = (const unsigned short *)data->src;
+	const u64 *q = (const u64 *)data->src;
 
 	debug("%s: blocks = %d, blocksize = %d\n",
 	      __func__, data->blocks, data->blocksize);
@@ -388,8 +415,12 @@ static int sh_sdhi_multi_write(struct sh_sdhi_host *host, struct mmc_data *data)
 
 		host->wait_int = 0;
 		blocksize = sh_sdhi_readw(host, SDHI_SIZE);
-		for (i = 0; i < blocksize / 2; i++)
+		if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
-			sh_sdhi_writew(host, SDHI_BUF0, *p++);
+			for (i = 0; i < blocksize / 8; i++)
+				sh_sdhi_writeq(host, SDHI_BUF0, *q++);
+		else
+			for (i = 0; i < blocksize / 2; i++)
+				sh_sdhi_writew(host, SDHI_BUF0, *p++);
 	}
 
 	return 0;
@@ -458,6 +489,13 @@ static unsigned short sh_sdhi_set_cmd(struct sh_sdhi_host *host,
 		else /* SD_SWITCH */
 			opc = SDHI_SD_SWITCH;
 		break;
+	case MMC_CMD_SEND_OP_COND:
+		opc = SDHI_MMC_SEND_OP_COND;
+		break;
+	case MMC_CMD_SEND_EXT_CSD:
+		if (data)
+			opc = SDHI_MMC_SEND_EXT_CSD;
+		break;
 	default:
 		break;
 	}
@@ -482,6 +520,7 @@ static unsigned short sh_sdhi_data_trans(struct sh_sdhi_host *host,
 	case MMC_CMD_READ_SINGLE_BLOCK:
 	case SDHI_SD_APP_SEND_SCR:
 	case SDHI_SD_SWITCH: /* SD_SWITCH */
+	case SDHI_MMC_SEND_EXT_CSD:
 		ret = sh_sdhi_single_read(host, data);
 		break;
 	default:
@@ -546,8 +585,6 @@ static int sh_sdhi_start_cmd(struct sh_sdhi_host *host,
 			break;
 	}
 
-	sh_sdhi_writew(host, SDHI_CMD, (unsigned short)(opc & CMD_MASK));
-
 	host->wait_int = 0;
 	sh_sdhi_writew(host, SDHI_INFO1_MASK,
 		       ~INFO1M_RESP_END & sh_sdhi_readw(host, SDHI_INFO1_MASK));
@@ -557,6 +594,8 @@ static int sh_sdhi_start_cmd(struct sh_sdhi_host *host,
 		       INFO2M_RESP_TIMEOUT | INFO2M_ILA) &
 		       sh_sdhi_readw(host, SDHI_INFO2_MASK));
 
+	sh_sdhi_writew(host, SDHI_CMD, (unsigned short)(opc & CMD_MASK));
+
 	time = sh_sdhi_wait_interrupt_flag(host);
 	if (!time)
 		return sh_sdhi_error_manage(host);
@@ -617,12 +656,18 @@ static int sh_sdhi_set_ios(struct mmc *mmc)
 	if (ret)
 		return -EINVAL;
 
-	if (mmc->bus_width == 4)
+	if (mmc->bus_width == 8)
-		sh_sdhi_writew(host, SDHI_OPTION, ~OPT_BUS_WIDTH_1 &
+		sh_sdhi_writew(host, SDHI_OPTION,
-			       sh_sdhi_readw(host, SDHI_OPTION));
+			       OPT_BUS_WIDTH_8 | (~OPT_BUS_WIDTH_M &
+			       sh_sdhi_readw(host, SDHI_OPTION)));
+	else if (mmc->bus_width == 4)
+		sh_sdhi_writew(host, SDHI_OPTION,
+			       OPT_BUS_WIDTH_4 | (~OPT_BUS_WIDTH_M &
+			       sh_sdhi_readw(host, SDHI_OPTION)));
 	else
-		sh_sdhi_writew(host, SDHI_OPTION, OPT_BUS_WIDTH_1 |
+		sh_sdhi_writew(host, SDHI_OPTION,
-			       sh_sdhi_readw(host, SDHI_OPTION));
+			       OPT_BUS_WIDTH_1 | (~OPT_BUS_WIDTH_M &
+			       sh_sdhi_readw(host, SDHI_OPTION)));
 
 	debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
 
@@ -653,6 +698,19 @@ static const struct mmc_ops sh_sdhi_ops = {
 	.init           = sh_sdhi_initialize,
 };
 
+#ifdef CONFIG_RCAR_GEN3
+static struct mmc_config sh_sdhi_cfg = {
+	.name           = DRIVER_NAME,
+	.ops            = &sh_sdhi_ops,
+	.f_min          = CLKDEV_INIT,
+	.f_max          = CLKDEV_HS_DATA,
+	.voltages       = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+	.host_caps      = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HS |
+			  MMC_MODE_HS_52MHz,
+	.part_type      = PART_TYPE_DOS,
+	.b_max          = CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+#else
 static struct mmc_config sh_sdhi_cfg = {
 	.name           = DRIVER_NAME,
 	.ops            = &sh_sdhi_ops,
@@ -663,6 +721,7 @@ static struct mmc_config sh_sdhi_cfg = {
 	.part_type      = PART_TYPE_DOS,
 	.b_max          = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 };
+#endif
 
 int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks)
 {
@@ -687,7 +746,9 @@ int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks)
 	host->addr = addr;
 	host->quirks = quirks;
 
-	if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
+	if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
+		host->bus_shift = 2;
+	else if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
 		host->bus_shift = 1;
 
 	return ret;

drivers/power/pmic/Kconfig

@@ -188,6 +188,13 @@ config PMIC_LP873X
 	The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
 	This driver binds the pmic children.
 
+config PMIC_LP87565
+	bool "Enable driver for Texas Instruments LP87565 PMIC"
+	depends on DM_PMIC
+	---help---
+	The LP87565 is a PMIC containing a bunch of SMPS.
+	This driver binds the pmic children.
+
 config POWER_MC34VR500
 	bool "Enable driver for Freescale MC34VR500 PMIC"
 	---help---

drivers/power/pmic/Makefile

@@ -21,6 +21,7 @@ obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
 obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
 obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
 obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
+obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
 
 obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
 obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o

drivers/power/pmic/lp87565.c

@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2017 Texas Instruments Incorporated, <www.ti.com>
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/lp87565.h>
+#include <dm/device.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+	{ .prefix = "buck", .driver = LP87565_BUCK_DRIVER },
+	{ },
+};
+
+static int lp87565_write(struct udevice *dev, uint reg, const uint8_t *buff,
+			  int len)
+{
+	int ret;
+
+	ret = dm_i2c_write(dev, reg, buff, len);
+	if (ret)
+		error("write error to device: %p register: %#x!", dev, reg);
+
+	return ret;
+}
+
+static int lp87565_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+	int ret;
+
+	ret = dm_i2c_read(dev, reg, buff, len);
+	if (ret)
+		error("read error from device: %p register: %#x!", dev, reg);
+
+	return ret;
+}
+
+static int lp87565_bind(struct udevice *dev)
+{
+	ofnode regulators_node;
+	int children;
+
+	regulators_node = dev_read_subnode(dev, "regulators");
+	if (!ofnode_valid(regulators_node)) {
+		debug("%s: %s regulators subnode not found!", __func__,
+		      dev->name);
+		return -ENXIO;
+	}
+
+	debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+	children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+	if (!children)
+		printf("%s: %s - no child found\n", __func__, dev->name);
+
+	/* Always return success for this device */
+	return 0;
+}
+
+static struct dm_pmic_ops lp87565_ops = {
+	.read = lp87565_read,
+	.write = lp87565_write,
+};
+
+static const struct udevice_id lp87565_ids[] = {
+	{ .compatible = "ti,lp87565", .data = LP87565 },
+	{ .compatible = "ti,lp87565-q1", .data = LP87565_Q1 },
+	{ }
+};
+
+U_BOOT_DRIVER(pmic_lp87565) = {
+	.name = "lp87565_pmic",
+	.id = UCLASS_PMIC,
+	.of_match = lp87565_ids,
+	.bind = lp87565_bind,
+	.ops = &lp87565_ops,
+};

drivers/power/pmic/pmic_tps65218.c

@@ -96,7 +96,8 @@ int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
 int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
 {
 	if ((dc_cntrl_reg != TPS65218_DCDC1) &&
-	    (dc_cntrl_reg != TPS65218_DCDC2))
+	    (dc_cntrl_reg != TPS65218_DCDC2) &&
+	    (dc_cntrl_reg != TPS65218_DCDC3))
 		return 1;
 
 	/* set voltage level */

drivers/power/regulator/Kconfig

@@ -149,3 +149,13 @@ config DM_REGULATOR_LP873X
 	This enables implementation of driver-model regulator uclass
 	features for REGULATOR LP873X and the family of LP873X PMICs.
 	The driver implements get/set api for: value and enable.
+
+config DM_REGULATOR_LP87565
+	bool "Enable driver for LP87565 PMIC regulators"
+        depends on PMIC_LP87565
+	---help---
+	This enables implementation of driver-model regulator uclass
+	features for REGULATOR LP87565 and the family of LP87565 PMICs.
+	LP87565 series of PMICs have 4 single phase BUCKs that can also
+	be configured in multi phase modes. The driver implements
+	get/set api for value and enable.

drivers/power/regulator/Makefile

@@ -18,3 +18,4 @@ obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
 obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o

drivers/power/regulator/lp87565_regulator.c

@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2017
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/lp87565.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char lp87565_buck_ctrl1[LP87565_BUCK_NUM] = {0x2, 0x4, 0x6, 0x8, 0x2, 0x6};
+static const char lp87565_buck_vout[LP87565_BUCK_NUM] = {0xA, 0xC, 0xE, 0x10, 0xA, 0xE };
+
+static int lp87565_buck_enable(struct udevice *dev, int op, bool *enable)
+{
+	int ret;
+	unsigned int adr;
+	struct dm_regulator_uclass_platdata *uc_pdata;
+
+	uc_pdata = dev_get_uclass_platdata(dev);
+	adr = uc_pdata->ctrl_reg;
+
+	ret = pmic_reg_read(dev->parent, adr);
+	if (ret < 0)
+		return ret;
+
+	if (op == PMIC_OP_GET) {
+		ret &= LP87565_BUCK_MODE_MASK;
+
+		if (ret)
+			*enable = true;
+		else
+			*enable = false;
+
+		return 0;
+	} else if (op == PMIC_OP_SET) {
+		if (*enable)
+			ret |= LP87565_BUCK_MODE_MASK;
+		else
+			ret &= ~LP87565_BUCK_MODE_MASK;
+		ret = pmic_reg_write(dev->parent, adr, ret);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int lp87565_buck_volt2val(int uV)
+{
+	if (uV > LP87565_BUCK_VOLT_MAX)
+		return -EINVAL;
+	else if (uV > 1400000)
+		return (uV - 1420000) / 20000 + 0x9E;
+	else if (uV > 730000)
+		return (uV - 735000) / 5000 + 0x18;
+	else if (uV >= 500000)
+		return (uV - 500000) / 10000;
+	else
+		return -EINVAL;
+}
+
+static int lp87565_buck_val2volt(int val)
+{
+	if (val > LP87565_BUCK_VOLT_MAX_HEX)
+		return -EINVAL;
+	else if (val > 0x9D)
+		return 1400000 + (val - 0x9D) * 20000;
+	else if (val > 0x17)
+		return 730000 + (val - 0x17) * 5000;
+	else if (val >= 0x0)
+		return 500000 + val * 10000;
+	else
+		return -EINVAL;
+}
+
+static int lp87565_buck_val(struct udevice *dev, int op, int *uV)
+{
+	unsigned int hex, adr;
+	int ret;
+	struct dm_regulator_uclass_platdata *uc_pdata;
+
+	uc_pdata = dev_get_uclass_platdata(dev);
+
+	if (op == PMIC_OP_GET)
+		*uV = 0;
+
+	adr = uc_pdata->volt_reg;
+
+	ret = pmic_reg_read(dev->parent, adr);
+	if (ret < 0)
+		return ret;
+
+	if (op == PMIC_OP_GET) {
+		ret &= LP87565_BUCK_VOLT_MASK;
+		ret = lp87565_buck_val2volt(ret);
+		if (ret < 0)
+			return ret;
+		*uV = ret;
+
+		return 0;
+	}
+
+	hex = lp87565_buck_volt2val(*uV);
+	if (hex < 0)
+		return hex;
+
+	ret &= 0x0;
+	ret = hex;
+
+	ret = pmic_reg_write(dev->parent, adr, ret);
+
+	return ret;
+}
+
+static int lp87565_buck_probe(struct udevice *dev)
+{
+	struct dm_regulator_uclass_platdata *uc_pdata;
+	int idx;
+
+	uc_pdata = dev_get_uclass_platdata(dev);
+	uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+	idx = dev->driver_data;
+	if (idx == 0 || idx == 1 || idx == 2 || idx == 3) {
+		debug("Single phase regulator\n");
+	} else if (idx == 23) {
+		idx = 5;
+	} else if (idx == 10) {
+		idx = 4;
+	} else {
+		printf("Wrong ID for regulator\n");
+		return -EINVAL;
+	}
+
+	uc_pdata->ctrl_reg = lp87565_buck_ctrl1[idx];
+	uc_pdata->volt_reg = lp87565_buck_vout[idx];
+
+	return 0;
+}
+
+static int buck_get_value(struct udevice *dev)
+{
+	int uV;
+	int ret;
+
+	ret = lp87565_buck_val(dev, PMIC_OP_GET, &uV);
+	if (ret)
+		return ret;
+
+	return uV;
+}
+
+static int buck_set_value(struct udevice *dev, int uV)
+{
+	return lp87565_buck_val(dev, PMIC_OP_SET, &uV);
+}
+
+static bool buck_get_enable(struct udevice *dev)
+{
+	bool enable = false;
+	int ret;
+
+
+	ret = lp87565_buck_enable(dev, PMIC_OP_GET, &enable);
+	if (ret)
+		return ret;
+
+	return enable;
+}
+
+static int buck_set_enable(struct udevice *dev, bool enable)
+{
+	return lp87565_buck_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static const struct dm_regulator_ops lp87565_buck_ops = {
+	.get_value  = buck_get_value,
+	.set_value  = buck_set_value,
+	.get_enable = buck_get_enable,
+	.set_enable = buck_set_enable,
+};
+
+U_BOOT_DRIVER(lp87565_buck) = {
+	.name = LP87565_BUCK_DRIVER,
+	.id = UCLASS_REGULATOR,
+	.ops = &lp87565_buck_ops,
+	.probe = lp87565_buck_probe,
+};

drivers/power/regulator/palmas_regulator.c

@@ -377,7 +377,11 @@ static int palmas_smps_probe(struct udevice *dev)
 			uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
 			uc_pdata->volt_reg = palmas_smps_volt[type][idx];
 			break;
-
+		case 12:
+			idx = 0;
+			uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
+			uc_pdata->volt_reg = palmas_smps_volt[type][idx];
+			break;
 		default:
 			printf("Wrong ID for regulator\n");
 		}

include/blk.h

@@ -616,4 +616,11 @@ ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
  */
 int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart);
 
+/**
+ * blk_get_from_parent() - obtain a block device by looking up its parent
+ *
+ * All devices with
+ */
+int blk_get_from_parent(struct udevice *parent, struct udevice **devp);
+
 #endif

include/power/lp87565.h

@@ -0,0 +1,12 @@
+#define LP87565	0x0
+#define LP87565_Q1	0x1
+
+#define LP87565_BUCK_NUM		6
+
+/* Drivers name */
+#define LP87565_BUCK_DRIVER	"lp87565_buck"
+
+#define LP87565_BUCK_VOLT_MASK		0xFF
+#define LP87565_BUCK_VOLT_MAX_HEX	0xFF
+#define LP87565_BUCK_VOLT_MAX		3360000
+#define LP87565_BUCK_MODE_MASK		0x80

include/power/tps65217.h

@@ -38,6 +38,7 @@ enum {
 	TPS65217_DEFLS1,
 	TPS65217_DEFLS2,
 	TPS65217_ENABLE,
+	TPS65217_RESERVED0, /* no 0x17 register available */
 	TPS65217_DEFUVLO,
 	TPS65217_SEQ1,
 	TPS65217_SEQ2,

include/power/tps65218.h

@@ -63,6 +63,7 @@ enum {
 #define TPS65218_DCDC_VOLT_SEL_1200MV		0x23
 #define TPS65218_DCDC_VOLT_SEL_1260MV		0x29
 #define TPS65218_DCDC_VOLT_SEL_1330MV		0x30
+#define TPS65218_DCDC3_VOLT_SEL_1350MV		0x12
 
 #define TPS65218_CC_STAT	(BIT(0) | BIT(1))
 #define TPS65218_STATE		(BIT(2) | BIT(3))

test/dm/blk.c

@@ -150,3 +150,21 @@ static int dm_test_blk_devnum(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_blk_devnum, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we can get a block from its parent */
+static int dm_test_blk_get_from_parent(struct unit_test_state *uts)
+{
+	struct udevice *dev, *blk;
+
+	ut_assertok(uclass_get_device(UCLASS_MMC, 0, &dev));
+	ut_assertok(blk_get_from_parent(dev, &blk));
+
+	ut_assertok(uclass_get_device(UCLASS_I2C, 0, &dev));
+	ut_asserteq(-ENOTBLK, blk_get_from_parent(dev, &blk));
+
+	ut_assertok(uclass_get_device(UCLASS_GPIO, 0, &dev));
+	ut_asserteq(-ENODEV, blk_get_from_parent(dev, &blk));
+
+	return 0;
+}
+DM_TEST(dm_test_blk_get_from_parent, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);