Add TFA boot flow for more boards

Add TFA boot defconfig for ls1088a and ls2088a.
 Add dts fixup for PCIe endpoint and root complex.
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Merge tag 'fsl-qoriq-for-v2019.04-rc1' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for more boards

Add TFA boot defconfig for ls1088a and ls2088a.
Add dts fixup for PCIe endpoint and root complex.

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -89,7 +89,7 @@ config ARCH_LS1046A
 config ARCH_LS1088A
 	bool
 	select ARMV8_SET_SMPEN
-	select ARM_ERRATA_855873
+	select ARM_ERRATA_855873 if !TFABOOT
 	select FSL_LSCH3
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
@@ -98,11 +98,11 @@ config ARCH_LS1088A
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_EC1
 	select SYS_FSL_EC2
-	select SYS_FSL_ERRATUM_A009803
+	select SYS_FSL_ERRATUM_A009803 if !TFABOOT
-	select SYS_FSL_ERRATUM_A009942
+	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
-	select SYS_FSL_ERRATUM_A010165
+	select SYS_FSL_ERRATUM_A010165 if !TFABOOT
-	select SYS_FSL_ERRATUM_A008511
+	select SYS_FSL_ERRATUM_A008511 if !TFABOOT
-	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_ERRATUM_A008850 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_HAS_CCI400
 	select SYS_FSL_HAS_DDR4
@@ -145,20 +145,20 @@ config ARCH_LS2080A
 	select SYS_FSL_SRDS_2
 	select FSL_TZASC_1
 	select FSL_TZASC_2
-	select SYS_FSL_ERRATUM_A008336
+	select SYS_FSL_ERRATUM_A008336 if !TFABOOT
-	select SYS_FSL_ERRATUM_A008511
+	select SYS_FSL_ERRATUM_A008511 if !TFABOOT
-	select SYS_FSL_ERRATUM_A008514
+	select SYS_FSL_ERRATUM_A008514 if !TFABOOT
 	select SYS_FSL_ERRATUM_A008585
 	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_ERRATUM_A009008
 	select SYS_FSL_ERRATUM_A009635
-	select SYS_FSL_ERRATUM_A009663
+	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A009801
-	select SYS_FSL_ERRATUM_A009803
+	select SYS_FSL_ERRATUM_A009803 if !TFABOOT
-	select SYS_FSL_ERRATUM_A009942
+	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
-	select SYS_FSL_ERRATUM_A010165
+	select SYS_FSL_ERRATUM_A010165 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009203
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -51,7 +51,9 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
 	CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
 	CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+	CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
 	CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+	CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
 	CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
 	CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
 	CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
@@ -675,7 +677,7 @@ enum boot_src __get_boot_src(u32 porsr1)
 			break;
 		case RCW_SRC_EMMC_VAL:
 		/* RCW SRC EMMC */
-			src = BOOT_SOURCE_SD_MMC2;
+			src = BOOT_SOURCE_SD_MMC;
 			break;
 		case RCW_SRC_I2C1_VAL:
 		/* RCW SRC I2C1 Extended */

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -327,7 +327,7 @@ static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
 	memcpy((char *)tmp, p, len);
 
 	val = fdt32_to_cpu(tmp[0][6]);
-	if (rev > REV1_0) {
+	if (rev == REV1_0) {
 		tmp[1][6] = cpu_to_fdt32(val + 1);
 		tmp[2][6] = cpu_to_fdt32(val + 2);
 		tmp[3][6] = cpu_to_fdt32(val + 3);

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -684,7 +684,7 @@ int qspi_ahb_init(void)
 #endif
 
 #ifdef CONFIG_TFABOOT
-#define MAX_BOOTCMD_SIZE	256
+#define MAX_BOOTCMD_SIZE	512
 
 int fsl_setenv_bootcmd(void)
 {
@@ -812,6 +812,17 @@ int board_late_init(void)
 		fsl_setenv_bootcmd();
 		fsl_setenv_mcinitcmd();
 	}
+
+	/*
+	 * If the boot mode is secure, default environment is not present then
+	 * setenv command needs to be run by default
+	 */
+#ifdef CONFIG_CHAIN_OF_TRUST
+	if ((fsl_check_boot_mode_secure() == 1)) {
+		fsl_setenv_bootcmd();
+		fsl_setenv_mcinitcmd();
+	}
+#endif
 #endif
 #ifdef CONFIG_QSPI_AHB_INIT
 	qspi_ahb_init();

arch/arm/dts/fsl-ls2088a-rdb-qspi.dts

@@ -56,3 +56,7 @@
 		reg = <1>;
 	};
 };
+
+&sata {
+	status = "okay";
+};

arch/arm/dts/ls1021a-iot.dtsi

@@ -12,9 +12,9 @@
 	model = "LS1021A IOT Board";
 
 	aliases {
-		enet2_rgmii_phy = &rgmii_phy1;
+		enet2-rgmii-phy = &rgmii_phy1;
-		enet0_sgmii_phy = &sgmii_phy2;
+		enet0-sgmii-phy = &sgmii_phy2;
-		enet1_sgmii_phy = &sgmii_phy0;
+		enet1-sgmii-phy = &sgmii_phy0;
 		spi0 = &qspi;
 		spi1 = &dspi1;
 	};

arch/arm/dts/ls1021a-qds.dtsi

@@ -11,11 +11,11 @@
 	model = "LS1021A QDS Board";
 
 	aliases {
-		enet0_rgmii_phy = &rgmii_phy1;
+		enet0-rgmii-phy = &rgmii_phy1;
-		enet1_rgmii_phy = &rgmii_phy2;
+		enet1-rgmii-phy = &rgmii_phy2;
-		enet2_rgmii_phy = &rgmii_phy3;
+		enet2-rgmii-phy = &rgmii_phy3;
-		enet0_sgmii_phy = &sgmii_phy1c;
+		enet0-sgmii-phy = &sgmii_phy1c;
-		enet1_sgmii_phy = &sgmii_phy1d;
+		enet1-sgmii-phy = &sgmii_phy1d;
 		spi0 = &qspi;
 		spi1 = &dspi0;
 	};

arch/arm/dts/ls1021a-twr.dtsi

@@ -11,9 +11,9 @@
 	model = "LS1021A TWR Board";
 
 	aliases {
-		enet2_rgmii_phy = &rgmii_phy1;
+		enet2-rgmii-phy = &rgmii_phy1;
-		enet0_sgmii_phy = &sgmii_phy2;
+		enet0-sgmii-phy = &sgmii_phy2;
-		enet1_sgmii_phy = &sgmii_phy0;
+		enet1-sgmii-phy = &sgmii_phy0;
 		spi0 = &qspi;
 		spi1 = &dspi1;
 	};

arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h

@@ -55,7 +55,11 @@ void fdt_fixup_icid(void *blob);
 		CONFIG_SYS_FSL_ESDHC_ADDR)
 
 #define SET_QDMA_ICID(compat, streamid) \
-	SET_SCFG_ICID(compat, streamid, dma_icid,\
+	SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
+		QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
+		QDMA_BASE_ADDR), \
+	SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
+		QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
 		QDMA_BASE_ADDR)
 
 #define SET_EDMA_ICID(streamid) \

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h

@@ -94,6 +94,7 @@
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
 
 #define QDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x07380000)
+#define QMAN_CQSIDR_REG				0x20a80
 
 #define CONFIG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL

arch/arm/include/asm/arch-fsl-layerscape/soc.h

@@ -80,6 +80,9 @@ enum boot_src get_boot_src(void);
 #define SVR_LS1012A		0x870400
 #define SVR_LS1043A		0x879200
 #define SVR_LS1023A		0x879208
+/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
+#define SVR_LS1043A_P23		0x879202
+#define SVR_LS1023A_P23		0x87920A
 #define SVR_LS1046A		0x870700
 #define SVR_LS1026A		0x870708
 #define SVR_LS1048A		0x870320

board/freescale/ls1046aqds/eth.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  */
 
 #include <common.h>
@@ -153,6 +154,9 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 			      enum fm_port port, int offset)
 {
 	struct fixed_link f_link;
+	const u32 *handle;
+	const char *prop = NULL;
+	int off;
 
 	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 		switch (port) {
@@ -208,16 +212,27 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				   "qsgmii");
 	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
 		   (port == FM1_10GEC1 || port == FM1_10GEC2)) {
-		/* XFI interface */
+		handle = fdt_getprop(fdt, offset, "phy-handle", NULL);
-		f_link.phy_id = cpu_to_fdt32(port);
+		prop = NULL;
-		f_link.duplex = cpu_to_fdt32(1);
+		if (handle) {
-		f_link.link_speed = cpu_to_fdt32(10000);
+			off = fdt_node_offset_by_phandle(fdt,
-		f_link.pause = 0;
+							 fdt32_to_cpu(*handle));
-		f_link.asym_pause = 0;
+			prop = fdt_getprop(fdt, off, "backplane-mode", NULL);
-		/* no PHY for XFI */
+		}
-		fdt_delprop(fdt, offset, "phy-handle");
+		if (!prop || strcmp(prop, "10gbase-kr")) {
-		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+			/* XFI interface */
-		fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
+			f_link.phy_id = cpu_to_fdt32(port);
+			f_link.duplex = cpu_to_fdt32(1);
+			f_link.link_speed = cpu_to_fdt32(10000);
+			f_link.pause = 0;
+			f_link.asym_pause = 0;
+			/* no PHY for XFI */
+			fdt_delprop(fdt, offset, "phy-handle");
+			fdt_setprop(fdt, offset, "fixed-link", &f_link,
+				    sizeof(f_link));
+			fdt_setprop_string(fdt, offset, "phy-connection-type",
+					   "xgmii");
+		}
 	}
 }
 

board/freescale/ls1088a/MAINTAINERS

@@ -1,15 +1,19 @@
 LS1088ARDB BOARD
 M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
 M:	Ashish Kumar <Ashish.Kumar@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1088a/
 F:	include/configs/ls1088ardb.h
 F:	configs/ls1088ardb_qspi_defconfig
 F:	configs/ls1088ardb_sdcard_qspi_defconfig
+F:	configs/ls1088ardb_tfa_defconfig
+F:	configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
 
 LS1088AQDS BOARD
 M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
 M:	Ashish Kumar <Ashish.Kumar@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1088a/
 F:	include/configs/ls1088aqds.h
@@ -17,6 +21,7 @@ F:	configs/ls1088aqds_qspi_defconfig
 F:	configs/ls1088aqds_sdcard_qspi_defconfig
 F:	configs/ls1088aqds_defconfig
 F:	configs/ls1088aqds_sdcard_ifc_defconfig
+F:	configs/ls1088aqds_tfa_defconfig
 
 LS1088AQDS_QSPI_SECURE_BOOT BOARD
 M:	Udit Agarwal <udit.agarwal@nxp.com>

board/freescale/ls1088a/ddr.c

@@ -111,7 +111,17 @@ found:
 			  DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
 }
 
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
 
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
+#else
 int fsl_initdram(void)
 {
 	puts("Initializing DDR....using SPD\n");
@@ -123,3 +133,4 @@ int fsl_initdram(void)
 #endif
 	return 0;
 }
+#endif /* CONFIG_TFABOOT */

board/freescale/ls1088a/ls1088a.c

@@ -28,6 +28,121 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_TARGET_LS1088AQDS
+#ifdef CONFIG_TFABOOT
+struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"nor0",
+		CONFIG_SYS_NOR0_CSPR_EARLY,
+		CONFIG_SYS_NOR0_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+		0,
+		CONFIG_SYS_NOR0_CSPR,
+		0,
+	},
+	{
+		"nor1",
+		CONFIG_SYS_NOR1_CSPR_EARLY,
+		CONFIG_SYS_NOR0_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK_EARLY,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+		0,
+		CONFIG_SYS_NOR1_CSPR,
+		CONFIG_SYS_NOR_AMASK,
+	},
+	{
+		"nand",
+		CONFIG_SYS_NAND_CSPR,
+		CONFIG_SYS_NAND_CSPR_EXT,
+		CONFIG_SYS_NAND_AMASK,
+		CONFIG_SYS_NAND_CSOR,
+		{
+			CONFIG_SYS_NAND_FTIM0,
+			CONFIG_SYS_NAND_FTIM1,
+			CONFIG_SYS_NAND_FTIM2,
+			CONFIG_SYS_NAND_FTIM3
+		},
+	},
+	{
+		"fpga",
+		CONFIG_SYS_FPGA_CSPR,
+		CONFIG_SYS_FPGA_CSPR_EXT,
+		SYS_FPGA_AMASK,
+		CONFIG_SYS_FPGA_CSOR,
+		{
+			SYS_FPGA_CS_FTIM0,
+			SYS_FPGA_CS_FTIM1,
+			SYS_FPGA_CS_FTIM2,
+			SYS_FPGA_CS_FTIM3
+		},
+		0,
+		SYS_FPGA_CSPR_FINAL,
+		0,
+	}
+};
+
+struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"nand",
+		CONFIG_SYS_NAND_CSPR,
+		CONFIG_SYS_NAND_CSPR_EXT,
+		CONFIG_SYS_NAND_AMASK,
+		CONFIG_SYS_NAND_CSOR,
+		{
+			CONFIG_SYS_NAND_FTIM0,
+			CONFIG_SYS_NAND_FTIM1,
+			CONFIG_SYS_NAND_FTIM2,
+			CONFIG_SYS_NAND_FTIM3
+		},
+	},
+	{
+		"reserved",
+	},
+	{
+		"fpga",
+		CONFIG_SYS_FPGA_CSPR,
+		CONFIG_SYS_FPGA_CSPR_EXT,
+		SYS_FPGA_AMASK,
+		CONFIG_SYS_FPGA_CSOR,
+		{
+			SYS_FPGA_CS_FTIM0,
+			SYS_FPGA_CS_FTIM1,
+			SYS_FPGA_CS_FTIM2,
+			SYS_FPGA_CS_FTIM3
+		},
+		0,
+		SYS_FPGA_CSPR_FINAL,
+		0,
+	}
+};
+
+void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
+{
+	enum boot_src src = get_boot_src();
+
+	if (src == BOOT_SOURCE_QSPI_NOR)
+		regs_info->regs = ifc_cfg_qspi_nor_boot;
+	else
+		regs_info->regs = ifc_cfg_ifc_nor_boot;
+
+	regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
+}
+#endif /* CONFIG_TFABOOT */
+#endif /* CONFIG_TARGET_LS1088AQDS */
+
 int board_early_init_f(void)
 {
 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
@@ -88,6 +203,9 @@ int fixup_ls1088ardb_pb_banner(void *fdt)
 #if !defined(CONFIG_SPL_BUILD)
 int checkboard(void)
 {
+#ifdef CONFIG_TFABOOT
+	enum boot_src src = get_boot_src();
+#endif
 	char buf[64];
 	u8 sw;
 	static const char *const freq[] = {"100", "125", "156.25",
@@ -117,9 +235,14 @@ int checkboard(void)
 	sw = QIXIS_READ(brdcfg[0]);
 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 
+#ifdef CONFIG_TFABOOT
+	if (src == BOOT_SOURCE_SD_MMC)
+		puts("SD card\n");
+#else
 #ifdef CONFIG_SD_BOOT
 	puts("SD card\n");
 #endif
+#endif /* CONFIG_TFABOOT */
 	switch (sw) {
 #ifdef CONFIG_TARGET_LS1088AQDS
 	case 0:
@@ -535,7 +658,8 @@ void fdt_fixup_board_enet(void *fdt)
 		return;
 	}
 
-	if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
+	if (get_mc_boot_status() == 0 &&
+	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 		fdt_status_okay(fdt, offset);
 	else
 		fdt_status_fail(fdt, offset);
@@ -546,6 +670,10 @@ void fdt_fixup_board_enet(void *fdt)
 void fsl_fdt_fixup_flash(void *fdt)
 {
 	int offset;
+#ifdef CONFIG_TFABOOT
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 val;
+#endif
 
 /*
  * IFC-NOR and QSPI are muxed on SoC.
@@ -553,6 +681,37 @@ void fsl_fdt_fixup_flash(void *fdt)
  * disable QSPI node in dts in case QSPI is not enabled.
  */
 
+#ifdef CONFIG_TFABOOT
+	enum boot_src src = get_boot_src();
+	bool disable_ifc = false;
+
+	switch (src) {
+	case BOOT_SOURCE_IFC_NOR:
+		disable_ifc = false;
+		break;
+	case BOOT_SOURCE_QSPI_NOR:
+		disable_ifc = true;
+		break;
+	default:
+		val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+		if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+			disable_ifc = true;
+		break;
+	}
+
+	if (disable_ifc) {
+		offset = fdt_path_offset(fdt, "/soc/ifc/nor");
+
+		if (offset < 0)
+			offset = fdt_path_offset(fdt, "/ifc/nor");
+	} else {
+		offset = fdt_path_offset(fdt, "/soc/quadspi");
+
+		if (offset < 0)
+			offset = fdt_path_offset(fdt, "/quadspi");
+	}
+
+#else
 #ifdef CONFIG_FSL_QSPI
 	offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 
@@ -563,6 +722,7 @@ void fsl_fdt_fixup_flash(void *fdt)
 
 	if (offset < 0)
 		offset = fdt_path_offset(fdt, "/quadspi");
+#endif
 #endif
 	if (offset < 0)
 		return;
@@ -613,3 +773,37 @@ int ft_board_setup(void *blob, bd_t *bd)
 }
 #endif
 #endif /* defined(CONFIG_SPL_BUILD) */
+
+#ifdef CONFIG_TFABOOT
+#ifdef CONFIG_MTD_NOR_FLASH
+int is_flash_available(void)
+{
+	char *env_hwconfig = env_get("hwconfig");
+	enum boot_src src = get_boot_src();
+	int is_nor_flash_available = 1;
+
+	switch (src) {
+	case BOOT_SOURCE_IFC_NOR:
+		is_nor_flash_available = 1;
+		break;
+	case BOOT_SOURCE_QSPI_NOR:
+		is_nor_flash_available = 0;
+		break;
+	/*
+	 * In Case of SD boot,if qspi is defined in env_hwconfig
+	 * disable nor flash probe.
+	 */
+	default:
+		if (hwconfig_f("qspi", env_hwconfig))
+			is_nor_flash_available = 0;
+		break;
+	}
+	return is_nor_flash_available;
+}
+#endif
+
+void *env_sf_get_env_addr(void)
+{
+	return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+}
+#endif

board/freescale/ls2080a/ls2080a.c

@@ -89,7 +89,8 @@ void fdt_fixup_board_enet(void *fdt)
 		return;
 	}
 
-	if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
+	if (get_mc_boot_status() == 0 &&
+	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 		fdt_status_okay(fdt, offset);
 	else
 		fdt_status_fail(fdt, offset);
@@ -142,3 +143,10 @@ void reset_phy(void)
 {
 }
 #endif
+
+#ifdef CONFIG_TFABOOT
+void *env_sf_get_env_addr(void)
+{
+	return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET);
+}
+#endif

board/freescale/ls2080aqds/MAINTAINERS

@@ -1,5 +1,6 @@
 LS2080A BOARD
 M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080aqds/
 F:	board/freescale/ls2080a/ls2080aqds.c
@@ -8,6 +9,7 @@ F:	configs/ls2080aqds_defconfig
 F:	configs/ls2080aqds_nand_defconfig
 F:	configs/ls2080aqds_qspi_defconfig
 F:	configs/ls2080aqds_sdcard_defconfig
+F:	configs/ls2088aqds_tfa_defconfig
 
 LS2080A_SECURE_BOOT BOARD
 #M:	Saksham Jain <saksham.jain@nxp.freescale.com>

board/freescale/ls2080aqds/ddr.c

@@ -155,6 +155,17 @@ found:
 	}
 }
 
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
+#else
 int fsl_initdram(void)
 {
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
@@ -167,3 +178,4 @@ int fsl_initdram(void)
 
 	return 0;
 }
+#endif /* CONFIG_TFABOOT */

board/freescale/ls2080aqds/ls2080aqds.c

@@ -294,7 +294,8 @@ void fdt_fixup_board_enet(void *fdt)
 		return;
 	}
 
-	if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
+	if (get_mc_boot_status() == 0 &&
+	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 		fdt_status_okay(fdt, offset);
 	else
 		fdt_status_fail(fdt, offset);

board/freescale/ls2080ardb/MAINTAINERS

@@ -9,8 +9,11 @@ F:	configs/ls2080ardb_nand_defconfig
 
 LS2088A_QSPI-boot BOARD
 M:	Priyanka Jain <priyanka.jain@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 S:	Maintained
 F:	configs/ls2088ardb_qspi_defconfig
+F:	configs/ls2088ardb_tfa_defconfig
+F:	configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
 
 LS2081ARDB BOARD
 M:	Priyanka Jain <priyanka.jain@nxp.com>

board/freescale/ls2080ardb/ddr.c

@@ -160,6 +160,17 @@ found:
 	}
 }
 
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
+#else
 int fsl_initdram(void)
 {
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
@@ -172,3 +183,4 @@ int fsl_initdram(void)
 
 	return 0;
 }
+#endif /* CONFIG_TFABOOT */

board/freescale/ls2080ardb/ls2080ardb.c

@@ -330,7 +330,8 @@ void fdt_fixup_board_enet(void *fdt)
 		return;
 	}
 
-	if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
+	if (get_mc_boot_status() == 0 &&
+	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 		fdt_status_okay(fdt, offset);
 	else
 		fdt_status_fail(fdt, offset);
@@ -346,12 +347,47 @@ void board_quiesce_devices(void)
 void fsl_fdt_fixup_flash(void *fdt)
 {
 	int offset;
+#ifdef CONFIG_TFABOOT
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 val;
+#endif
 
 /*
  * IFC and QSPI are muxed on board.
  * So disable IFC node in dts if QSPI is enabled or
  * disable QSPI node in dts in case QSPI is not enabled.
  */
+#ifdef CONFIG_TFABOOT
+	enum boot_src src = get_boot_src();
+	bool disable_ifc = false;
+
+	switch (src) {
+	case BOOT_SOURCE_IFC_NOR:
+		disable_ifc = false;
+		break;
+	case BOOT_SOURCE_QSPI_NOR:
+		disable_ifc = true;
+		break;
+	default:
+		val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+		if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+			disable_ifc = true;
+		break;
+	}
+
+	if (disable_ifc) {
+		offset = fdt_path_offset(fdt, "/soc/ifc");
+
+		if (offset < 0)
+			offset = fdt_path_offset(fdt, "/ifc");
+	} else {
+		offset = fdt_path_offset(fdt, "/soc/quadspi");
+
+		if (offset < 0)
+			offset = fdt_path_offset(fdt, "/quadspi");
+	}
+
+#else
 #ifdef CONFIG_FSL_QSPI
 	offset = fdt_path_offset(fdt, "/soc/ifc");
 
@@ -363,6 +399,8 @@ void fsl_fdt_fixup_flash(void *fdt)
 	if (offset < 0)
 		offset = fdt_path_offset(fdt, "/quadspi");
 #endif
+#endif
+
 	if (offset < 0)
 		return;
 

configs/ls1043aqds_tfa_defconfig

@@ -30,6 +30,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y

configs/ls1043ardb_tfa_defconfig

@@ -26,6 +26,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_MMC=y

configs/ls1046aqds_tfa_defconfig

@@ -32,6 +32,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
 CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y

configs/ls1046ardb_tfa_defconfig

@@ -26,6 +26,7 @@ CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
+CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y

configs/ls1088aqds_tfa_defconfig

@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088AQDS=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_FSL_SPI_ALIGNED_TXFIFO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1088ardb_tfa_SECURE_BOOT_defconfig

@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_TFABOOT=y
+CONFIG_SECURE_BOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y

configs/ls1088ardb_tfa_defconfig

@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_FSL_SPI_ALIGNED_TXFIFO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2088aqds_tfa_defconfig

@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_NR_DRAM_BANKS=3
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DATE=y
+CONFIG_MP=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2088ardb_tfa_SECURE_BOOT_defconfig

@@ -0,0 +1,74 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_TFABOOT=y
+CONFIG_SECURE_BOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_NR_DRAM_BANKS=3
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DATE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_CONS_INDEX=2
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_FSL_SPI_ALIGNED_TXFIFO=y
+
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y

configs/ls2088ardb_tfa_defconfig

@@ -0,0 +1,73 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_NR_DRAM_BANKS=3
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DATE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_CONS_INDEX=2
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_FSL_SPI_ALIGNED_TXFIFO=y
+
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

drivers/misc/fsl_ifc.c

@@ -7,6 +7,7 @@
 #include <common.h>
 #include <fsl_ifc.h>
 
+#ifdef CONFIG_TFABOOT
 struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"cs0",
@@ -340,6 +341,7 @@ __weak void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 	regs_info->regs = ifc_cfg_default_boot;
 	regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 }
+#endif
 
 void print_ifc_regs(void)
 {
@@ -355,6 +357,7 @@ void print_ifc_regs(void)
 	}
 }
 
+#ifdef CONFIG_TFABOOT
 void init_early_memctl_regs(void)
 {
 	int i, j;
@@ -405,3 +408,173 @@ void init_final_memctl_regs(void)
 								regs[i].amask);
 	}
 }
+#else
+void init_early_memctl_regs(void)
+{
+#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
+	set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
+	set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
+	set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
+	set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
+
+#ifndef CONFIG_A003399_NOR_WORKAROUND
+#ifdef CONFIG_SYS_CSPR0_EXT
+	set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR0_EXT
+	set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
+#endif
+	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
+	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+#endif
+#endif
+
+#ifdef CONFIG_SYS_CSPR1_EXT
+	set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR1_EXT
+	set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
+	set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
+	set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
+	set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
+	set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
+
+	set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
+	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
+	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
+#endif
+
+#ifdef CONFIG_SYS_CSPR2_EXT
+	set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR2_EXT
+	set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
+	set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
+	set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
+	set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
+	set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
+
+	set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
+	set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
+	set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
+#endif
+
+#ifdef CONFIG_SYS_CSPR3_EXT
+	set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR3_EXT
+	set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
+	set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
+	set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
+	set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
+	set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
+
+	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
+	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
+	set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
+#endif
+
+#ifdef CONFIG_SYS_CSPR4_EXT
+	set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR4_EXT
+	set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
+	set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
+
+	set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
+	set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
+	set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+#endif
+
+#ifdef CONFIG_SYS_CSPR5_EXT
+	set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR5_EXT
+	set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
+	set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
+	set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
+	set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
+	set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
+
+	set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
+	set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
+	set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
+#endif
+
+#ifdef CONFIG_SYS_CSPR6_EXT
+	set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR6_EXT
+	set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
+	set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
+
+	set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
+	set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
+	set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+#endif
+
+#ifdef CONFIG_SYS_CSPR7_EXT
+	set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR7_EXT
+	set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
+	set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+
+	set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
+	set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
+	set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
+#endif
+}
+
+void init_final_memctl_regs(void)
+{
+#ifdef CONFIG_SYS_CSPR0_FINAL
+	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
+#endif
+#ifdef CONFIG_SYS_AMASK0_FINAL
+	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+#endif
+#ifdef CONFIG_SYS_CSPR1_FINAL
+	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
+#endif
+#ifdef CONFIG_SYS_AMASK1_FINAL
+	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
+#endif
+#ifdef CONFIG_SYS_CSPR2_FINAL
+	set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL);
+#endif
+#ifdef CONFIG_SYS_AMASK2_FINAL
+	set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
+#endif
+#ifdef CONFIG_SYS_CSPR3_FINAL
+	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
+#endif
+#ifdef CONFIG_SYS_AMASK3_FINAL
+	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
+#endif
+}
+#endif

drivers/mmc/fsl_esdhc.c

@@ -1545,7 +1545,6 @@ static int fsl_esdhc_get_cd(struct udevice *dev)
 {
 	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
 
-	return true;
 	return esdhc_getcd_common(priv);
 }
 

drivers/net/fsl-mc/mc.c

@@ -834,6 +834,11 @@ int get_dpl_apply_status(void)
 	return mc_dpl_applied;
 }
 
+int is_lazy_dpl_addr_valid(void)
+{
+	return !!mc_lazy_dpl_addr;
+}
+
 /*
  * Return the MC address of private DRAM block.
  * As per MC design document, MC initial base address

drivers/pci/pcie_layerscape.c

@@ -225,6 +225,9 @@ static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
 {
 	struct udevice *bus = pcie->bus;
 
+	if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
+		return -ENODEV;
+
 	if (!pcie->enabled)
 		return -ENXIO;
 
@@ -438,9 +441,7 @@ static int ls_pcie_probe(struct udevice *dev)
 	struct ls_pcie *pcie = dev_get_priv(dev);
 	const void *fdt = gd->fdt_blob;
 	int node = dev_of_offset(dev);
-	u8 header_type;
 	u16 link_sta;
-	bool ep_mode;
 	uint svr;
 	int ret;
 	fdt_size_t cfg_size;
@@ -524,15 +525,15 @@ static int ls_pcie_probe(struct udevice *dev)
 	      (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
 	      pcie->big_endian);
 
-	header_type = readb(pcie->dbi + PCI_HEADER_TYPE);
+	pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
-	ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
-	printf("PCIe%u: %s %s", pcie->idx, dev->name,
-	       ep_mode ? "Endpoint" : "Root Complex");
 
-	if (ep_mode)
+	if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
-		ls_pcie_setup_ep(pcie);
+		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
-	else
+			ls_pcie_setup_ep(pcie);
-		ls_pcie_setup_ctrl(pcie);
+	} else {
+		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+			ls_pcie_setup_ctrl(pcie);
+	}
 
 	if (!ls_pcie_link_up(pcie)) {
 		/* Let the user know there's no PCIe link */

drivers/pci/pcie_layerscape.h

@@ -144,6 +144,7 @@ struct ls_pcie {
 	bool big_endian;
 	bool enabled;
 	int next_lut_index;
+	int mode;
 };
 
 extern struct list_head ls_pcie_list;

drivers/pci/pcie_layerscape_fixup.c

@@ -218,7 +218,7 @@ static void fdt_fixup_pcie(void *blob)
 }
 #endif
 
-static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
 {
 	int off;
 	uint svr;
@@ -243,12 +243,33 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
 			return;
 	}
 
-	if (pcie->enabled)
+	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
 		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
 	else
 		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 }
 
+static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
+{
+	int off;
+
+	off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie-ep",
+					    pcie->dbi_res.start);
+	if (off < 0)
+		return;
+
+	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
+		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+	else
+		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
+
+static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
+{
+	ft_pcie_ep_fix(blob, pcie);
+	ft_pcie_rc_fix(blob, pcie);
+}
+
 /* Fixup Kernel DT for PCIe */
 void ft_pci_setup(void *blob, bd_t *bd)
 {

include/configs/ls1043a_common.h

@@ -323,6 +323,8 @@
 			   "env exists secureboot && esbc_halt;"
 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "	\
 			   "env exists secureboot && esbc_halt;"
+#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;"
 #else
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\

include/configs/ls1088a_common.h

@@ -29,16 +29,23 @@
 
 #define LS1088ARDB_PB_BOARD            0x4A
 /* Link Definitions */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+#else
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#endif
 
 /* Link Definitions */
-
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_FSL_QSPI_BASE	0x20000000
+#else
 #ifdef CONFIG_QSPI_BOOT
 #define CONFIG_SYS_FSL_QSPI_BASE	0x20000000
 #define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FSL_QSPI_BASE + \
 						CONFIG_ENV_OFFSET)
 #endif
+#endif
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
@@ -192,6 +199,7 @@ unsigned long long get_qixis_addr(void);
 	"mcinitcmd=fsl_mc start mc 0x580a00000"	\
 	" 0x580e00000 \0"
 
+#ifndef CONFIG_TFABOOT
 #if defined(CONFIG_QSPI_BOOT)
 #define CONFIG_BOOTCOMMAND	"sf probe 0:0;" \
 				"sf read 0x80001000 0xd00000 0x100000;"\
@@ -208,6 +216,7 @@ unsigned long long get_qixis_addr(void);
 				" cp.b $kernel_start $kernel_load" \
 				" $kernel_size && bootm $kernel_load"
 #endif
+#endif /* CONFIG_TFABOOT  */
 #endif
 
 /* Monitor Command Prompt */

include/configs/ls1088aqds.h

@@ -14,7 +14,15 @@ unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV		0
 
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_ENV_OFFSET		0x500000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#else
 #if defined(CONFIG_QSPI_BOOT)
 #define CONFIG_ENV_SIZE			0x2000          /* 8KB */
 #define CONFIG_ENV_SECT_SIZE		0x40000
@@ -27,6 +35,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x20000
 #endif
+#endif
 
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_QIXIS_I2C_ACCESS
@@ -209,6 +218,44 @@ unsigned long get_board_ddr_clk(void);
 					FTIM2_GPCM_TWP(0x3E))
 #define SYS_FPGA_CS_FTIM3	0x0
 
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK3		SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
+#else
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
@@ -265,6 +312,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
 #define CONFIG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
 #endif
+#endif
 
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
@@ -323,7 +371,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
 
 /* QSPI device */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define FSL_QSPI_FLASH_SIZE		(1 << 26)
 #define FSL_QSPI_FLASH_NUM		2
 
@@ -333,7 +382,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_SPI_FLASH_EON
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#if !defined(CONFIG_TFABOOT) && \
+	!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SF_DEFAULT_BUS		1
 #define CONFIG_SF_DEFAULT_CS		0
 #endif
@@ -377,6 +427,50 @@ unsigned long get_board_ddr_clk(void);
 	"fsl_mc start mc 0xa0a00000 0xa0e00000\0"			\
 	"mcmemsize=0x70000000 \0"
 #else /* if !(CONFIG_SECURE_BOOT) */
+#ifdef CONFIG_TFABOOT
+#define QSPI_MC_INIT_CMD				\
+	"sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"	\
+	"sf read 0x80100000 0xE00000 0x100000;" \
+	"fsl_mc start mc 0x80000000 0x80100000\0"
+#define SD_MC_INIT_CMD				\
+	"mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
+	"mmc read 0x80100000 0x7000 0x800;" \
+	"fsl_mc start mc 0x80000000 0x80100000\0"
+#define IFC_MC_INIT_CMD				\
+	"fsl_mc start mc 0x580A00000 0x580E00000\0"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x90100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"kernel_addr_sd=0x800\0"                \
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x1000000\0"		\
+	"kernel_start_sd=0x8000\0"              \
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernel_size_sd=0x14000\0"               \
+	"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"	\
+	"sf read 0x80100000 0xE00000 0x100000;" \
+	"fsl_mc start mc 0x80000000 0x80100000\0"	\
+	"mcmemsize=0x70000000 \0"
+#define QSPI_NOR_BOOTCOMMAND	"sf probe 0:0;" \
+				"sf read 0x80001000 0xd00000 0x100000;"\
+				" fsl_mc lazyapply dpl 0x80001000 &&" \
+				" sf read $kernel_load $kernel_start" \
+				" $kernel_size && bootm $kernel_load"
+#define SD_BOOTCOMMAND		"mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
+				" fsl_mc lazyapply dpl 0x80001000 &&" \
+				" mmc read $kernel_load $kernel_start_sd" \
+				" $kernel_size_sd && bootm $kernel_load"
+#define IFC_NOR_BOOTCOMMAND	"fsl_mc lazyapply dpl 0x580d00000 &&" \
+				" cp.b $kernel_start $kernel_load" \
+				" $kernel_size && bootm $kernel_load"
+#else
 #if defined(CONFIG_QSPI_BOOT)
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS		\
@@ -427,6 +521,7 @@ unsigned long get_board_ddr_clk(void);
 	"mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"	\
 	"mcmemsize=0x70000000 \0"
 #endif
+#endif /* CONFIG_TFABOOT */
 #endif /* CONFIG_SECURE_BOOT */
 
 #ifdef CONFIG_FSL_MC_ENET

include/configs/ls1088ardb.h

@@ -8,6 +8,15 @@
 
 #include "ls1088a_common.h"
 
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET		0x500000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#else
 #if defined(CONFIG_QSPI_BOOT)
 #define CONFIG_ENV_SIZE			0x2000          /* 8KB */
 #define CONFIG_ENV_SECT_SIZE		0x40000
@@ -21,8 +30,10 @@
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x20000
 #endif
+#endif /* CONFIG_TFABOOT */
 
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_QIXIS_I2C_ACCESS
 #endif
@@ -185,7 +196,8 @@
 					FTIM2_GPCM_TWP(0x3E))
 #define SYS_FPGA_CS_FTIM3	0x0
 
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
@@ -215,7 +227,6 @@
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #endif
 
-
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 #define I2C_MUX_CH_VOL_MONITOR          0xA
@@ -274,7 +285,8 @@
 
 #ifndef SPL_NO_QSPI
 /* QSPI device */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define FSL_QSPI_FLASH_SIZE		(1 << 26)
 #define FSL_QSPI_FLASH_NUM		2
 #endif
@@ -294,6 +306,26 @@
 
 #ifndef SPL_NO_ENV
 /* Initial environment variables */
+#ifdef CONFIG_TFABOOT
+#define QSPI_MC_INIT_CMD				\
+	"sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"	\
+	"sf read 0x80100000 0xE00000 0x100000;"				\
+	"env exists secureboot && "			\
+	"sf read 0x80700000 0x700000 0x40000 && "	\
+	"sf read 0x80740000 0x740000 0x40000 && "	\
+	"esbc_validate 0x80700000 && "			\
+	"esbc_validate 0x80740000 ;"			\
+	"fsl_mc start mc 0x80000000 0x80100000\0"
+#define SD_MC_INIT_CMD				\
+	"mmcinfo;mmc read 0x80000000 0x5000 0x800;"		\
+	"mmc read 0x80100000 0x7000 0x800;"				\
+	"env exists secureboot && "			\
+	"mmc read 0x80700000 0x3800 0x10 && "		\
+	"mmc read 0x80740000 0x3A00 0x10 && "		\
+	"esbc_validate 0x80700000 && "			\
+	"esbc_validate 0x80740000 ;"			\
+	"fsl_mc start mc 0x80000000 0x80100000\0"
+#else
 #if defined(CONFIG_QSPI_BOOT)
 #define MC_INIT_CMD				\
 	"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"	\
@@ -317,8 +349,84 @@
 	"fsl_mc start mc 0x80000000 0x80100000\0"	\
 	"mcmemsize=0x70000000\0"
 #endif
+#endif /* CONFIG_TFABOOT */
 
 #undef CONFIG_EXTRA_ENV_SETTINGS
+#ifdef CONFIG_TFABOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"BOARD=ls1088ardb\0"			\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x64f00000\0"			\
+	"kernel_addr=0x1000000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernelhdr_addr_sd=0x4000\0"		\
+	"kernel_start=0x580100000\0"		\
+	"kernelheader_start=0x580800000\0"	\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr=0x800000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernel_size_sd=0x14000\0"		\
+	"kernelhdr_size_sd=0x10\0"		\
+	QSPI_MC_INIT_CMD			\
+	"mcmemsize=0x70000000\0"		\
+	BOOTENV					\
+	"boot_scripts=ls1088ardb_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls1088ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="		\
+		"part list ${devtype} ${devnum} devplist; "	\
+		"env exists devplist || setenv devplist 1; "	\
+		"for distro_bootpart in ${devplist}; do "	\
+			"if fstype ${devtype} "			\
+				"${devnum}:${distro_bootpart} "	\
+				"bootfstype; then "		\
+				"run scan_dev_for_boot; "	\
+			"fi; "					\
+		"done\0"					\
+	"scan_dev_for_boot="					\
+		"echo Scanning ${devtype} "			\
+		"${devnum}:${distro_bootpart}...; "		\
+		"for prefix in ${boot_prefixes}; do "		\
+			"run scan_dev_for_scripts; "		\
+		"done;\0"					\
+	"boot_a_script="					\
+		"load ${devtype} ${devnum}:${distro_bootpart} " \
+		"${scriptaddr} ${prefix}${script}; "		\
+	"env exists secureboot && load ${devtype} "		\
+		"${devnum}:${distro_bootpart} "			\
+		"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+		"&& esbc_validate ${scripthdraddr};"		\
+		"source ${scriptaddr}\0"			\
+	"installer=load mmc 0:2 $load_addr "			\
+		"/flex_installer_arm64.itb; "			\
+		"env exists mcinitcmd && run mcinitcmd && "	\
+		"mmc read 0x80001000 0x6800 0x800;"		\
+		"fsl_mc lazyapply dpl 0x80001000;"			\
+		"bootm $load_addr#ls1088ardb\0"			\
+	"qspi_bootcmd=echo Trying load from qspi..;"		\
+		"sf probe && sf read $load_addr "		\
+		"$kernel_addr $kernel_size ; env exists secureboot "	\
+		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		"bootm $load_addr#$BOARD\0"			\
+		"sd_bootcmd=echo Trying load from sd card..;"		\
+		"mmcinfo; mmc read $load_addr "			\
+		"$kernel_addr_sd $kernel_size_sd ;"		\
+		"env exists secureboot && mmc read $kernelheader_addr_r "\
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$BOARD\0"
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"BOARD=ls1088ardb\0"			\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
@@ -391,8 +499,28 @@
 		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
 		" && esbc_validate ${kernelheader_addr_r};"	\
 		"bootm $load_addr#$BOARD\0"
+#endif /* CONFIG_TFABOOT */
 
 #undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND					\
+		"sf read 0x80001000 0xd00000 0x100000;"		\
+		"env exists mcinitcmd && env exists secureboot "	\
+		" && sf read 0x80780000 0x780000 0x100000 "	\
+		"&& esbc_validate 0x80780000;env exists mcinitcmd "	\
+		"&& fsl_mc lazyapply dpl 0x80001000;"		\
+		"run distro_bootcmd;run qspi_bootcmd;"		\
+		"env exists secureboot && esbc_halt;"
+#define SD_BOOTCOMMAND						\
+		"env exists mcinitcmd && mmcinfo; "		\
+		"mmc read 0x80001000 0x6800 0x800; "		\
+		"env exists mcinitcmd && env exists secureboot "	\
+		" && mmc read 0x80780000 0x3C00 0x10 "		\
+		"&& esbc_validate 0x80780000;env exists mcinitcmd "	\
+		"&& fsl_mc lazyapply dpl 0x80001000;"		\
+		"run distro_bootcmd;run sd_bootcmd;"		\
+		"env exists secureboot && esbc_halt;"
+#else
 #if defined(CONFIG_QSPI_BOOT)
 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 #define CONFIG_BOOTCOMMAND                                      \
@@ -416,6 +544,7 @@
 		"run distro_bootcmd;run sd_bootcmd;"		\
 		"env exists secureboot && esbc_halt;"
 #endif
+#endif /* CONFIG_TFABOOT */
 
 /* MAC/PHY configuration */
 #ifdef CONFIG_FSL_MC_ENET

include/configs/ls2080a_common.h

@@ -16,17 +16,23 @@
 #include <asm/arch/config.h>
 
 /* Link Definitions */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+#else
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#endif
 
 /* We need architecture specific misc initializations */
 
 /* Link Definitions */
+#ifndef CONFIG_TFABOOT
 #ifndef CONFIG_QSPI_BOOT
 #else
 #define CONFIG_ENV_SIZE			0x2000          /* 8KB */
 #define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
 #define CONFIG_ENV_SECT_SIZE		0x40000
 #endif
+#endif
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
@@ -185,6 +191,7 @@ unsigned long long get_qixis_addr(void);
 	"mcinitcmd=fsl_mc start mc 0x580a00000"	\
 	" 0x580e00000 \0"
 
+#ifndef CONFIG_TFABOOT
 #ifdef CONFIG_SD_BOOT
 #define CONFIG_BOOTCOMMAND	"mmc read 0x80200000 0x6800 0x800;"\
 				" fsl_mc apply dpl 0x80200000 &&" \
@@ -195,6 +202,7 @@ unsigned long long get_qixis_addr(void);
 				" cp.b $kernel_start $kernel_load" \
 				" $kernel_size && bootm $kernel_load"
 #endif
+#endif
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */

include/configs/ls2080aqds.h

@@ -55,6 +55,15 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
 
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_ENV_OFFSET		0x500000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#endif
+
 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
 
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
@@ -261,7 +270,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_TFABOOT)
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x2000
@@ -361,6 +370,33 @@ unsigned long get_board_ddr_clk(void);
 	"esbc_validate 0x580740000;"            \
 	"fsl_mc start mc 0x580a00000"           \
 	" 0x580e00000 \0"
+#else
+#ifdef CONFIG_TFABOOT
+#define SD_MC_INIT_CMD				\
+	"mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
+	"mmc read 0x80100000 0x7000 0x800;" \
+	"fsl_mc start mc 0x80000000 0x80100000\0"
+#define IFC_MC_INIT_CMD				\
+	"fsl_mc start mc 0x580a00000" \
+	" 0x580e00000 \0"
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
+	"loadaddr=0x80100000\0"                 \
+	"loadaddr_sd=0x90100000\0"                 \
+	"kernel_addr=0x100000\0"                \
+	"kernel_addr_sd=0x800\0"                \
+	"ramdisk_addr=0x800000\0"               \
+	"ramdisk_size=0x2000000\0"              \
+	"fdt_high=0xa0000000\0"                 \
+	"initrd_high=0xffffffffffffffff\0"      \
+	"kernel_start=0x581000000\0"            \
+	"kernel_start_sd=0x8000\0"              \
+	"kernel_load=0xa0000000\0"              \
+	"kernel_size=0x2800000\0"               \
+	"kernel_size_sd=0x14000\0"               \
+	"mcinitcmd=fsl_mc start mc 0x580a00000" \
+	" 0x580e00000 \0"			\
+	"mcmemsize=0x70000000 \0"
 #elif defined(CONFIG_SD_BOOT)
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
@@ -392,9 +428,9 @@ unsigned long get_board_ddr_clk(void);
 	"mcmemsize=0x40000000\0"		\
 	"mcinitcmd=fsl_mc start mc 0x580a00000" \
 	" 0x580e00000 \0"
+#endif /* CONFIG_TFABOOT */
 #endif /* CONFIG_SECURE_BOOT */
 
-
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 #define CONFIG_FSL_MEMAC
 #define CONFIG_PHYLIB_10G

include/configs/ls2080ardb.h

@@ -69,8 +69,17 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_SCSI_MAX_LUN			1
 #define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV         0
 
-#ifndef CONFIG_FSL_QSPI
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x500000	/* 5MB */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#endif
+
+#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
 
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
@@ -212,9 +221,11 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
 
+#ifndef CONFIG_TFABOOT
 #define CONFIG_ENV_OFFSET		(2048 * 1024)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x2000
+#endif
 #define CONFIG_SPL_PAD_TO		0x80000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(1024 * 1024)
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
@@ -237,10 +248,12 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 
+#ifndef CONFIG_TFABOOT
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x2000
 #endif
+#endif
 
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
@@ -323,6 +336,27 @@ unsigned long get_board_sys_clk(void);
 	func(SCSI, scsi, 0)
 #include <config_distro_bootcmd.h>
 
+#ifdef CONFIG_TFABOOT
+#define QSPI_MC_INIT_CMD			\
+	"env exists secureboot && "		\
+	"esbc_validate 0x20700000 && "		\
+	"esbc_validate 0x20740000;"		\
+	"fsl_mc start mc 0x20a00000 0x20e00000 \0"
+#define SD_MC_INIT_CMD				\
+	"mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
+	"mmc read 0x80100000 0x7000 0x800;"	\
+	"env exists secureboot && "		\
+	"mmc read 0x80700000 0x3800 0x10 && "	\
+	"mmc read 0x80740000 0x3A00 0x10 && "	\
+	"esbc_validate 0x80700000 && "		\
+	"esbc_validate 0x80740000 ;"		\
+	"fsl_mc start mc 0x80000000 0x80100000\0"
+#define IFC_MC_INIT_CMD				\
+	"env exists secureboot && "	\
+	"esbc_validate 0x580700000 && "		\
+	"esbc_validate 0x580740000; "		\
+	"fsl_mc start mc 0x580a00000 0x580e00000 \0"
+#else
 #ifdef CONFIG_QSPI_BOOT
 #define MC_INIT_CMD				\
 	"mcinitcmd=env exists secureboot && "	\
@@ -347,9 +381,80 @@ unsigned long get_board_sys_clk(void);
 	"esbc_validate 0x580740000; "		\
 	"fsl_mc start mc 0x580a00000 0x580e00000 \0"
 #endif
+#endif
 
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS
+#ifdef CONFIG_TFABOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x64f00000\0"			\
+	"kernel_addr=0x581000000\0"		\
+	"kernel_start=0x1000000\0"		\
+	"kernelheader_start=0x800000\0"		\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernelheader_addr=0x580800000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernel_size_sd=0x14000\0"              \
+	"console=ttyAMA0,38400n8\0"		\
+	"mcmemsize=0x70000000\0"		\
+	"sd_bootcmd=echo Trying load from SD ..;" \
+	"mmcinfo; mmc read $load_addr "		\
+	"$kernel_addr_sd $kernel_size_sd && "	\
+	"bootm $load_addr#$board\0"             \
+	QSPI_MC_INIT_CMD				\
+	BOOTENV					\
+	"boot_scripts=ls2088ardb_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls2088ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="		\
+		"part list ${devtype} ${devnum} devplist; "	\
+		"env exists devplist || setenv devplist 1; "	\
+		"for distro_bootpart in ${devplist}; do "	\
+			"if fstype ${devtype} "			\
+				"${devnum}:${distro_bootpart} "	\
+				"bootfstype; then "		\
+				"run scan_dev_for_boot; "	\
+			"fi; "					\
+		"done\0"					\
+	"scan_dev_for_boot="					\
+		"echo Scanning ${devtype} "			\
+			"${devnum}:${distro_bootpart}...; "	\
+		"for prefix in ${boot_prefixes}; do "		\
+			"run scan_dev_for_scripts; "		\
+		"done;\0"					\
+	"boot_a_script="					\
+		"load ${devtype} ${devnum}:${distro_bootpart} "	\
+			"${scriptaddr} ${prefix}${script}; "	\
+		"env exists secureboot && load ${devtype} "	\
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
+			"&& esbc_validate ${scripthdraddr};"	\
+		"source ${scriptaddr}\0"			\
+	"qspi_bootcmd=echo Trying load from qspi..;"		\
+		"sf probe && sf read $load_addr "		\
+		"$kernel_start $kernel_size ; env exists secureboot &&"	\
+		"sf read $kernelheader_addr_r $kernelheader_start "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		" bootm $load_addr#$board\0"			\
+	"nor_bootcmd=echo Trying load from nor..;"		\
+		"cp.b $kernel_addr $load_addr "			\
+		"$kernel_size ; env exists secureboot && "	\
+		"cp.b $kernelheader_addr $kernelheader_addr_r "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		"bootm $load_addr#$board\0"
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"ramdisk_addr=0x800000\0"		\
@@ -418,7 +523,36 @@ unsigned long get_board_sys_clk(void);
 		"cp.b $kernelheader_addr $kernelheader_addr_r "	\
 		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 		"bootm $load_addr#$board\0"
+#endif
 
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& esbc_validate 0x20780000; "			\
+			"env exists mcinitcmd && "			\
+			"fsl_mc lazyapply dpl 0x20d00000; "		\
+			"run distro_bootcmd;run qspi_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+
+/* Try to boot an on-SD kernel first, then do normal distro boot */
+#define SD_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
+			"&& esbc_validate $load_addr; "			\
+			"env exists mcinitcmd && run mcinitcmd "	\
+			"&& mmc read 0x88000000 0x6800 0x800 "		\
+			"&& fsl_mc lazyapply dpl 0x88000000; "		\
+			"run distro_bootcmd;run sd_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+
+/* Try to boot an on-NOR kernel first, then do normal distro boot */
+#define IFC_NOR_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& esbc_validate 0x580780000; env exists mcinitcmd "\
+			"&& fsl_mc lazyapply dpl 0x580d00000;"		\
+			"run distro_bootcmd;run nor_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+#else
 #undef CONFIG_BOOTCOMMAND
 #ifdef CONFIG_QSPI_BOOT
 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
@@ -449,6 +583,7 @@ unsigned long get_board_sys_clk(void);
 			"run distro_bootcmd;run nor_bootcmd; "		\
 			"env exists secureboot && esbc_halt;"
 #endif
+#endif
 
 /* MAC/PHY configuration */
 #ifdef CONFIG_FSL_MC_ENET

include/environment.h

@@ -162,15 +162,6 @@ extern const unsigned char default_environment[];
 extern void env_reloc(void);
 #endif
 
-#ifdef CONFIG_ENV_IS_IN_MMC
-#include <mmc.h>
-
-extern int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
-# ifdef CONFIG_SYS_MMC_ENV_PART
-extern uint mmc_get_env_part(struct mmc *mmc);
-# endif
-#endif
-
 #ifndef DO_DEPS_ONLY
 
 #include <env_attr.h>

include/fsl-mc/fsl_mc.h

@@ -54,6 +54,7 @@ struct mc_ccsr_registers {
 void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
 int get_mc_boot_status(void);
 int get_dpl_apply_status(void);
+int is_lazy_dpl_addr_valid(void);
 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 int get_aiop_apply_status(void);
 #endif

include/mmc.h

@@ -828,6 +828,9 @@ void board_mmc_power_init(void);
 int board_mmc_init(bd_t *bis);
 int cpu_mmc_init(bd_t *bis);
 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
+# ifdef CONFIG_SYS_MMC_ENV_PART
+extern uint mmc_get_env_part(struct mmc *mmc);
+# endif
 int mmc_get_env_dev(void);
 
 /* Set block count limit because of 16 bit register limit on some hardware*/