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arm: dra7xx: Add DDR related data for DRA752 ES1.0
DRA752 uses DDR3. Populating the corresponding structures with DDR3 data. Writing into MA registers if only MA is present in that soc. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
parent
8b12f1779e
commit
7831419d7b
5 changed files with 42 additions and 6 deletions
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@ -1191,7 +1191,7 @@ void dmm_init(u32 base)
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writel(lisa_map_regs->dmm_lisa_map_0,
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writel(lisa_map_regs->dmm_lisa_map_0,
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&hw_lisa_map_regs->dmm_lisa_map_0);
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&hw_lisa_map_regs->dmm_lisa_map_0);
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if (omap_revision() >= OMAP4460_ES1_0) {
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if (lisa_map_regs->is_ma_present) {
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hw_lisa_map_regs =
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hw_lisa_map_regs =
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(struct dmm_lisa_map_regs *)MA_BASE;
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(struct dmm_lisa_map_regs *)MA_BASE;
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@ -94,14 +94,24 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
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.dmm_lisa_map_0 = 0xFF020100,
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.dmm_lisa_map_0 = 0xFF020100,
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.dmm_lisa_map_1 = 0,
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.dmm_lisa_map_1 = 0,
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.dmm_lisa_map_2 = 0,
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.dmm_lisa_map_2 = 0,
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.dmm_lisa_map_3 = 0x80540300
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.dmm_lisa_map_3 = 0x80540300,
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.is_ma_present = 0x0
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};
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};
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const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
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const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
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.dmm_lisa_map_0 = 0xFF020100,
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.dmm_lisa_map_0 = 0xFF020100,
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.dmm_lisa_map_1 = 0,
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.dmm_lisa_map_1 = 0,
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.dmm_lisa_map_2 = 0,
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.dmm_lisa_map_2 = 0,
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.dmm_lisa_map_3 = 0x80640300
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.dmm_lisa_map_3 = 0x80640300,
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.is_ma_present = 0x0
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};
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const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
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.dmm_lisa_map_0 = 0xFF020100,
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.dmm_lisa_map_1 = 0,
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.dmm_lisa_map_2 = 0,
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.dmm_lisa_map_3 = 0x80640300,
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.is_ma_present = 0x1
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};
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};
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static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
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static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
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@ -126,8 +136,10 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
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if (omap_rev == OMAP4430_ES1_0)
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if (omap_rev == OMAP4430_ES1_0)
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*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
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*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
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else
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else if (omap_rev < OMAP4460_ES1_0)
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*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
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*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
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else
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*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
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}
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}
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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@ -586,6 +586,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
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*regs = &ioregs_omap5432_es1;
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*regs = &ioregs_omap5432_es1;
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break;
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break;
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case OMAP5432_ES2_0:
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case OMAP5432_ES2_0:
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case DRA752_ES1_0:
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*regs = &ioregs_omap5432_es2;
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*regs = &ioregs_omap5432_es2;
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break;
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break;
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@ -155,7 +155,16 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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.dmm_lisa_map_2 = 0x80740300,
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.dmm_lisa_map_2 = 0x80740300,
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.dmm_lisa_map_3 = 0xFF020100
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.dmm_lisa_map_3 = 0xFF020100,
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.is_ma_present = 0x1
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};
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const struct dmm_lisa_map_regs lisa_map_512M_x_1 = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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.dmm_lisa_map_2 = 0x0,
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.dmm_lisa_map_3 = 0x80500100,
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.is_ma_present = 0x1
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};
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};
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static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
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static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
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@ -171,6 +180,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
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*regs = &emif_regs_532_mhz_2cs_es2;
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*regs = &emif_regs_532_mhz_2cs_es2;
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break;
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break;
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case OMAP5432_ES2_0:
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case OMAP5432_ES2_0:
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case DRA752_ES1_0:
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default:
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default:
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*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
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*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
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}
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}
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@ -182,7 +192,18 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
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static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
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**dmm_lisa_regs)
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**dmm_lisa_regs)
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{
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{
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*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
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switch (omap_revision()) {
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case OMAP5430_ES1_0:
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case OMAP5430_ES2_0:
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case OMAP5432_ES1_0:
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case OMAP5432_ES2_0:
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*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
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break;
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case DRA752_ES1_0:
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default:
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*dmm_lisa_regs = &lisa_map_512M_x_1;
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}
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}
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}
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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@ -297,6 +318,7 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
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*regs = ddr3_ext_phy_ctrl_const_base_es1;
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*regs = ddr3_ext_phy_ctrl_const_base_es1;
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break;
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break;
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case OMAP5432_ES2_0:
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case OMAP5432_ES2_0:
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case DRA752_ES1_0:
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default:
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default:
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*regs = ddr3_ext_phy_ctrl_const_base_es2;
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*regs = ddr3_ext_phy_ctrl_const_base_es2;
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@ -697,6 +697,7 @@ struct dmm_lisa_map_regs {
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u32 dmm_lisa_map_1;
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u32 dmm_lisa_map_1;
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u32 dmm_lisa_map_2;
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u32 dmm_lisa_map_2;
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u32 dmm_lisa_map_3;
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u32 dmm_lisa_map_3;
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u8 is_ma_present;
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};
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};
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#define CS0 0
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#define CS0 0
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