From 26f8e0d7f27e19102d6173d1e5831e7a82096779 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Date: Wed, 17 Apr 2019 19:41:05 +0200 Subject: [PATCH 1/4] arm: sunxi: h6: fix reset using r_wdog MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some H6 boards have a watchdog which didn't make the SoC reboot properly. Reason is still unknown but several people have test it. Chen-Yu Tsai : Pine H64 = H6 V200-AWIN H6448BA 7782 => OK OrangePi Lite 2 = H6 V200-AWIN H8068BA 61C2 => KO Martin Ayotte : Pine H64 = H8069BA 6892 => OK OrangePi 3 = HA047BA 69W2 => KO OrangePi One Plus = H7310BA 6842 => KO OrangePi Lite2 = H6448BA 6662 => KO Clément Péron: Beelink GS1 = H6 V200-AWIN H7309BA 6842 => KO After the series of result, Icenowy try to reach Allwinner about this issue but they seems not interested to investigate it. As we don't have the ARIS coproc to do power management and watchdogis the only solution to reset the board. So, Change from watchdog to R_watchdog to allow a reboot on all H6 boards. Signed-off-by: Clément Péron Reviewed-by: Jagan Teki --- arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 1 + arch/arm/mach-sunxi/board.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index 41a9b0fc47..6392cb07b4 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -60,6 +60,7 @@ #define SUNXI_RTC_BASE 0x07000000 #define SUNXI_R_CPUCFG_BASE 0x07000400 #define SUNXI_PRCM_BASE 0x07010000 +#define SUNXI_R_WDOG_BASE 0x07020400 #define SUNXI_R_PIO_BASE 0x07022000 #define SUNXI_R_UART_BASE 0x07080000 #define SUNXI_R_TWI_BASE 0x07081400 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index c6dd7b8e54..921e4c5175 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -289,9 +289,14 @@ void reset_cpu(ulong addr) writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); } #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) +#if defined(CONFIG_MACH_SUN50I_H6) + /* WDOG is broken for some H6 rev. use the R_WDOG instead */ static const struct sunxi_wdog *wdog = - ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; - + (struct sunxi_wdog *)SUNXI_R_WDOG_BASE; +#else + static const struct sunxi_wdog *wdog = + ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; +#endif /* Set the watchdog for its shortest interval (.5s) and wait */ writel(WDT_CFG_RESET, &wdog->cfg); writel(WDT_MODE_EN, &wdog->mode); From b4161b7d1376eb834b993cd4b2f85f49b5e07eeb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Date: Tue, 14 May 2019 20:26:33 +0200 Subject: [PATCH 2/4] sun50i: h6: Fix Beelink GS1 board config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SPL_TEXT_BASE has been moved to Kconfig with commit: f89d6133ee configs: move CONFIG_SPL_TEXT_BASE to Kconfig But Beelink GS1 config file has been introduced in the same time without this modification. Fix this by settings the CONFIG_SPL_TEXT_BASE Suggested-by: Jonas Smedegaard Signed-off-by: Clément Péron Reviewed-by: Jagan Teki --- configs/beelink_gs1_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig index ef4dd29549..437e2d950d 100644 --- a/configs/beelink_gs1_defconfig +++ b/configs/beelink_gs1_defconfig @@ -7,6 +7,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set CONFIG_NR_DRAM_BANKS=1 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_TEXT_BASE=0x20060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set From ee61c168bdc2732a5be1770dc5785693228fd5be Mon Sep 17 00:00:00 2001 From: Jonas Smedegaard Date: Mon, 20 May 2019 22:27:18 +0530 Subject: [PATCH 3/4] sun50i: a64: teres_i: Fix broken SPL_TEXT_BASE SPL_TEXT_BASE was moved into Kconfig, which previously part of include/configs before this teres_i support gets merged. Fix it by explicitly define in defconfig like other boards does. Signed-off-by: Jonas Smedegaard Signed-off-by: Jagan Teki --- configs/teres_i_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig index 421a8d3d40..1b57a48712 100644 --- a/configs/teres_i_defconfig +++ b/configs/teres_i_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PL7" CONFIG_I2C0_ENABLE=y +CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set From c598c4837d782f6d9481f4be07ae5d679c6df976 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 16 Apr 2019 19:18:03 +0200 Subject: [PATCH 4/4] sun8i: h3: NanoPi M1 Plus: Add emac configuration NanoPi M1 plus have a 10/100/1000M ethernet with external phy. Phy power is controlled by PD6. Add the required configuration for it. Signed-off-by: Emmanuel Vadot Reviewed-by: Jagan Teki --- configs/nanopi_m1_plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index ad94d58831..90edbd9b06 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -4,6 +4,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 +CONFIG_MACPWR="PD6" CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -12,6 +13,7 @@ CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus" +CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y