From 350e16cfb460e6910c4fa30119a3adde91243961 Mon Sep 17 00:00:00 2001 From: Udit Agarwal Date: Fri, 3 Feb 2017 22:53:37 +0530 Subject: [PATCH 01/30] armv8: lsch3: SECURE_BOOT: Define CONFIG_SYS_LS_PPA_ESBC_ADDR for LS2080A Add header address for PPA to be validated during ESBC phase for LS2080A platform based on Layescape Chasis 3. Signed-off-by: Sumit Garg Signed-off-by: Udit Agarwal Reviewed-by: York Sun --- arch/arm/include/asm/fsl_secure_boot.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index fd627c0874..8ef866d740 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -112,6 +112,8 @@ #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP #ifdef CONFIG_LS1043A #define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000 +#elif defined(CONFIG_FSL_LSCH3) +#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x580c40000 #endif #else #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined" From a8c6fd4ec11a3bd9cfd3bdb6350686d497158d62 Mon Sep 17 00:00:00 2001 From: Udit Agarwal Date: Fri, 3 Feb 2017 22:53:38 +0530 Subject: [PATCH 02/30] armv8: LS2080A: Move sec_init to board_init Moves sec_init to board_init rather than in misc_init function beacuse PPA will be initialised in board_init function and for PPA validation sec_init has to be done prior to PPA init. Signed-off-by: Sumit Garg Signed-off-by: Udit Agarwal Reviewed-by: York Sun --- board/freescale/ls2080aqds/ls2080aqds.c | 6 +++--- board/freescale/ls2080ardb/ls2080ardb.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 277013bfcc..e1de799ee5 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -224,6 +224,9 @@ int board_init(void) #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); rtc_enable_32khz_output(); +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } @@ -266,9 +269,6 @@ void detail_board_ddr_info(void) #if defined(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif return 0; } #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 4c01f560bc..6d410c05e9 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -185,6 +185,9 @@ int board_init(void) /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); #endif +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } @@ -223,9 +226,6 @@ void detail_board_ddr_info(void) #if defined(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif return 0; } #endif From 9e052d975058cd01c1421c4beb9ddd387dd525da Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 6 Feb 2017 11:27:27 +0800 Subject: [PATCH 03/30] fsl-layerscape/ppa: cleanup ppa.h Moved the ifdef into ppa.h and removed the duplicated macros. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/ppa.h | 7 ++----- arch/arm/include/asm/armv8/sec_firmware.h | 4 ---- board/freescale/ls1043ardb/ls1043ardb.c | 2 -- 3 files changed, 2 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h index 1f1442b6f0..da4098ebd3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h @@ -7,10 +7,7 @@ #ifndef __FSL_PPA_H_ #define __FSL_PPA_H_ -#define SEC_FIRMWARE_FIT_IMAGE "firmware" -#define SEC_FIRMEWARE_FIT_CNF_NAME "config@1" -#define SEC_FIRMWARE_TARGET_EL 2 - +#ifdef CONFIG_FSL_LS_PPA int ppa_init(void); - +#endif #endif diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h index 5ae00fa8d2..bcdb1b0072 100644 --- a/arch/arm/include/asm/armv8/sec_firmware.h +++ b/arch/arm/include/asm/armv8/sec_firmware.h @@ -7,10 +7,6 @@ #ifndef __SEC_FIRMWARE_H_ #define __SEC_FIRMWARE_H_ -#ifdef CONFIG_FSL_LS_PPA -#include -#endif - int sec_firmware_init(const void *, u32 *, u32 *); int _sec_firmware_entry(const void *, u32 *, u32 *); bool sec_firmware_is_valid(const void *); diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 2333843958..728de2e3f1 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -23,9 +23,7 @@ #ifdef CONFIG_U_QE #include #endif -#ifdef CONFIG_FSL_LS_PPA #include -#endif DECLARE_GLOBAL_DATA_PTR; From 6d7b9e78f531210fd4dc99d12e81b0df8d8cdae0 Mon Sep 17 00:00:00 2001 From: Santan Kumar Date: Mon, 6 Feb 2017 14:18:12 +0530 Subject: [PATCH 04/30] armv8: ls2080ardb, ls2080aqds: Add mcmemsize in default env setting Initialize mcmemsize to 0x40000000 Signed-off-by: Santan Kumar Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- include/configs/ls2080aqds.h | 2 ++ include/configs/ls2080ardb.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 08d1586867..beacb997a3 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -368,6 +368,7 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "mcmemsize=0x40000000\0" \ "mcinitcmd=esbc_validate 0x580c80000;" \ "esbc_validate 0x580cc0000;" \ "fsl_mc start mc 0x580300000" \ @@ -384,6 +385,7 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "mcmemsize=0x40000000\0" \ "mcinitcmd=fsl_mc start mc 0x580300000" \ " 0x580800000 \0" #endif /* CONFIG_SECURE_BOOT */ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 408140f4e8..2155a89e36 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -339,6 +339,7 @@ unsigned long get_board_sys_clk(void); "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "mcmemsize=0x40000000\0" \ "fdtfile=fsl-ls2080a-rdb.dtb\0" \ "mcinitcmd=esbc_validate 0x580c80000;" \ "esbc_validate 0x580cc0000;" \ @@ -362,6 +363,7 @@ unsigned long get_board_sys_clk(void); "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "mcmemsize=0x40000000\0" \ "fdtfile=fsl-ls2080a-rdb.dtb\0" \ "mcinitcmd=fsl_mc start mc 0x580300000" \ " 0x580800000 \0" \ From ac55dadb1cb6a350604affd84e19006984933fa0 Mon Sep 17 00:00:00 2001 From: Udit Agarwal Date: Thu, 9 Feb 2017 21:36:11 +0530 Subject: [PATCH 05/30] fsl: Secure Boot: Enable IE (Key extention) Feature For validating images from uboot (Such as Kernel Image), either keys from SoC fuses can be used or keys from a verified table of public keys can be used. The latter feature is called IE Key Extension Feature. For Layerscape Chasis 3 based platforms, IE table is validated by Bootrom and address of this table is written in scratch registers 13 and 14 via PBI commands. Following are the steps describing usage of this feature: 1) Verify IE Table in ISBC phase using keys stored in fuses. 2) Install IE table. (To be used across verification of multiple images stored in a static global structure.) 3) Use keys from IE table, to verify further images. Signed-off-by: Aneesh Bansal Signed-off-by: Saksham Jain Signed-off-by: Udit Agarwal Reviewed-by: York Sun --- arch/arm/include/asm/fsl_secure_boot.h | 6 +- board/freescale/common/fsl_validate.c | 88 +++++++++++++++++++++----- include/fsl_validate.h | 24 ++++++- 3 files changed, 97 insertions(+), 21 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 8ef866d740..d98a1e8f89 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -38,11 +38,11 @@ * in boot ROM of the SoC. * The feature is only applicable in case of NOR boot and is * not applicable in case of RAMBOOT (NAND, SD, SPI). + * For LS, this feature is available for all device if IE Table + * is copied to XIP memory + * Also, for LS, ISBC doesn't verify this table. */ -#ifndef CONFIG_ESBC_HDR_LS -/* Current Key EXT feature not available in LS ESBC Header */ #define CONFIG_FSL_ISBC_KEY_EXT -#endif #endif diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 2b723a4b9c..7396aa2f69 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -27,6 +27,10 @@ #define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ ((key_len) == 2 * KEY_SIZE_BYTES)) +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +/* Global data structure */ +static struct fsl_secboot_glb glb; +#endif /* This array contains DER value for SHA-256 */ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, @@ -60,7 +64,7 @@ self: #if defined(CONFIG_FSL_ISBC_KEY_EXT) static u32 check_ie(struct fsl_secboot_img_priv *img) { - if (img->hdr.ie_flag) + if (img->hdr.ie_flag & IE_FLAG_MASK) return 1; return 0; @@ -119,7 +123,21 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) } #endif -static int get_ie_info_addr(u32 *ie_addr) +#if defined(CONFIG_ESBC_HDR_LS) +static int get_ie_info_addr(uintptr_t *ie_addr) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + /* For LS-CH3, the address of IE Table is + * stated in Scratch13 and scratch14 of DCFG. + * Bootrom validates this table while validating uboot. + * DCFG is LE*/ + *ie_addr = in_le32(&gur->scratchrw[SCRATCH_IE_HIGH_ADR - 1]); + *ie_addr = *ie_addr << 32; + *ie_addr |= in_le32(&gur->scratchrw[SCRATCH_IE_LOW_ADR - 1]); + return 0; +} +#else /* CONFIG_ESBC_HDR_LS */ +static int get_ie_info_addr(uintptr_t *ie_addr) { struct fsl_secboot_img_hdr *hdr; struct fsl_secboot_sg_table *sg_tbl; @@ -147,16 +165,17 @@ static int get_ie_info_addr(u32 *ie_addr) /* IE Key Table is the first entry in the SG Table */ #if defined(CONFIG_MPC85xx) - *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) + - flash_base_addr; + *ie_addr = (uintptr_t)((sg_tbl->src_addr & + ~(CONFIG_SYS_PBI_FLASH_BASE)) + + flash_base_addr); #else - *ie_addr = sg_tbl->src_addr; + *ie_addr = (uintptr_t)sg_tbl->src_addr; #endif - debug("IE Table address is %x\n", *ie_addr); + debug("IE Table address is %lx\n", *ie_addr); return 0; } - +#endif /* CONFIG_ESBC_HDR_LS */ #endif #ifdef CONFIG_KEY_REVOCATION @@ -164,7 +183,10 @@ static int get_ie_info_addr(u32 *ie_addr) static u32 check_srk(struct fsl_secboot_img_priv *img) { #ifdef CONFIG_ESBC_HDR_LS - /* In LS, No SRK Flag as SRK is always present*/ + /* In LS, No SRK Flag as SRK is always present if IE not present*/ +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + return !check_ie(img); +#endif return 1; #else if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) @@ -253,14 +275,29 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) #endif /* CONFIG_ESBC_HDR_LS */ #if defined(CONFIG_FSL_ISBC_KEY_EXT) + +static void install_ie_tbl(uintptr_t ie_tbl_addr, + struct fsl_secboot_img_priv *img) +{ + /* Copy IE tbl to Global Data */ + memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info)); + img->ie_addr = (uintptr_t)&glb.ie_tbl; + glb.ie_addr = img->ie_addr; +} + static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) { struct fsl_secboot_img_hdr *hdr = &img->hdr; u32 ie_key_len, ie_revoc_flag, ie_num; struct ie_key_info *ie_info; - if (get_ie_info_addr(&img->ie_addr)) - return ERROR_IE_TABLE_NOT_FOUND; + if (!img->ie_addr) { + if (get_ie_info_addr(&img->ie_addr)) + return ERROR_IE_TABLE_NOT_FOUND; + else + install_ie_tbl(img->ie_addr, img); + } + ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; if (ie_info->num_keys == 0 || ie_info->num_keys > 32) return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; @@ -786,6 +823,26 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) return 0; } +/* Function to initialize img priv and global data structure + */ +static int secboot_init(struct fsl_secboot_img_priv **img_ptr) +{ + *img_ptr = malloc(sizeof(struct fsl_secboot_img_priv)); + + struct fsl_secboot_img_priv *img = *img_ptr; + + if (!img) + return -ENOMEM; + memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + if (glb.ie_addr) + img->ie_addr = glb.ie_addr; +#endif + return 0; +} + + /* haddr - Address of the header of image to be validated. * arg_hash_str - Option hash string. If provided, this * overrides the key hash in the SFP fuses. @@ -839,12 +896,9 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, hash_cmd = 1; } - img = malloc(sizeof(struct fsl_secboot_img_priv)); - - if (!img) - return -1; - - memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + ret = secboot_init(&img); + if (ret) + goto exit; /* Update the information in Private Struct */ hdr = &img->hdr; @@ -899,5 +953,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, } exit: + /* Free Img as it was malloc'ed*/ + free(img); return ret; } diff --git a/include/fsl_validate.h b/include/fsl_validate.h index c350938d1f..452c6df83f 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -40,8 +40,8 @@ struct fsl_secboot_img_hdr { u8 num_srk; u8 srk_sel; u8 reserve; - u8 ie_flag; } len_kr; + u8 ie_flag; u32 uid_flag; @@ -69,6 +69,11 @@ struct fsl_secboot_img_hdr { #define MAX_KEY_ENTRIES 8 #endif +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#define IE_FLAG_MASK 0x1 +#define SCRATCH_IE_LOW_ADR 13 +#define SCRATCH_IE_HIGH_ADR 14 +#endif #else /* CONFIG_ESBC_HDR_LS */ @@ -150,6 +155,10 @@ struct fsl_secboot_img_hdr { #define MAX_KEY_ENTRIES 4 #endif +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#define IE_FLAG_MASK 0xFFFFFFFF +#endif + #endif /* CONFIG_ESBC_HDR_LS */ @@ -202,6 +211,17 @@ struct fsl_secboot_sg_table { }; #endif +/* ESBC global structure. + * Data to be used across verification of different images. + * Stores follwoing Data: + * IE Table + */ +struct fsl_secboot_glb { +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + uintptr_t ie_addr; + struct ie_key_info ie_tbl; +#endif +}; /* * ESBC private structure. * Private structure used by ESBC to store following fields @@ -213,7 +233,7 @@ struct fsl_secboot_sg_table { */ struct fsl_secboot_img_priv { uint32_t hdr_location; - u32 ie_addr; + uintptr_t ie_addr; u32 key_len; struct fsl_secboot_img_hdr hdr; From d170aca1a0716331cde0af957e3bd59c5531d04f Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 10 Feb 2017 15:42:11 +0800 Subject: [PATCH 06/30] pci: layerscape: enable PCIe config ready In EP mode, to enable accesses from the Root Complex, the CONFIG_READY bit must be set, otherwise any config attempts from the Root Complex will be returned with config retry status (CRS). Signed-off-by: Hou Zhiqiang Signed-off-by: Minghuan Lian Reviewed-by: York Sun --- drivers/pci/pcie_layerscape.c | 7 +++++++ drivers/pci/pcie_layerscape.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index b6806cf67b..47dd806ad2 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -409,6 +409,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base) ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); } +static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie) +{ + ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG); +} + static void ls_pcie_setup_ep(struct ls_pcie *pcie) { u32 sriov; @@ -432,6 +437,8 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie) ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); ls_pcie_ep_setup_atu(pcie); } + + ls_pcie_ep_enable_cfg(pcie); } static int ls_pcie_probe(struct udevice *dev) diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 1e635ef1f2..0f9d2fe6d3 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -94,8 +94,10 @@ #define PCIE_LUT_ENTRY_COUNT 32 /* PF Controll registers */ +#define PCIE_PF_CONFIG 0x14 #define PCIE_PF_VF_CTRL 0x7F8 #define PCIE_PF_DBG 0x7FC +#define PCIE_CONFIG_READY (1 << 0) #define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx)) #define PCIE_SYS_BASE_ADDR 0x3400000 From eea1cb77cef061392658d3a4a9b7f0ec7eb74634 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 14 Feb 2017 10:34:31 +0530 Subject: [PATCH 07/30] armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 7e66ee08b5..78e250c1cc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -436,7 +436,14 @@ int arch_early_init_r(void) #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 - erratum_a009635(); + u32 svr_dev_id; + /* + * erratum A009635 is valid only for LS2080A SoC and + * its personalitiesi + */ + svr_dev_id = get_svr() >> 16; + if (svr_dev_id == SVR_DEV_LS2080A) + erratum_a009635(); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) erratum_a009942_check_cpo(); From 1b7dba990f60b461fb7af92464590cc0f326ae81 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Wed, 15 Feb 2017 20:40:00 +0530 Subject: [PATCH 08/30] arm: fsl-layerscape: Move QSGMII wriop_init to SoC file MAC number used per QSGMII is not fixed. It may wary from SoC to SoC. So move QSGMII wriop_init_dpmac() to SoC file. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- .../armv8/fsl-layerscape/fsl_lsch3_serdes.c | 25 ++++------------ .../asm/arch-fsl-layerscape/fsl_serdes.h | 8 ++--- drivers/net/ldpaa_eth/ls2080a.c | 30 +++++++++++++++++++ include/fsl-mc/ldpaa_wriop.h | 1 + 4 files changed, 41 insertions(+), 23 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 7faa86c3fd..c2fc6468e1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -23,6 +23,11 @@ int xfi_dpmac[XFI8 + 1]; int sgmii_dpmac[SGMII16 + 1]; #endif +__weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) +{ + return; +} + int is_serdes_configured(enum srds_prtcl device) { int ret = 0; @@ -106,28 +111,10 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, #ifdef CONFIG_FSL_MC_ENET switch (lane_prtcl) { case QSGMII_A: - wriop_init_dpmac(sd, 5, (int)lane_prtcl); - wriop_init_dpmac(sd, 6, (int)lane_prtcl); - wriop_init_dpmac(sd, 7, (int)lane_prtcl); - wriop_init_dpmac(sd, 8, (int)lane_prtcl); - break; case QSGMII_B: - wriop_init_dpmac(sd, 1, (int)lane_prtcl); - wriop_init_dpmac(sd, 2, (int)lane_prtcl); - wriop_init_dpmac(sd, 3, (int)lane_prtcl); - wriop_init_dpmac(sd, 4, (int)lane_prtcl); - break; case QSGMII_C: - wriop_init_dpmac(sd, 13, (int)lane_prtcl); - wriop_init_dpmac(sd, 14, (int)lane_prtcl); - wriop_init_dpmac(sd, 15, (int)lane_prtcl); - wriop_init_dpmac(sd, 16, (int)lane_prtcl); - break; case QSGMII_D: - wriop_init_dpmac(sd, 9, (int)lane_prtcl); - wriop_init_dpmac(sd, 10, (int)lane_prtcl); - wriop_init_dpmac(sd, 11, (int)lane_prtcl); - wriop_init_dpmac(sd, 12, (int)lane_prtcl); + wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl); break; default: if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index d9d948e2ab..70181c5077 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -48,10 +48,10 @@ enum srds_prtcl { SGMII14, SGMII15, SGMII16, - QSGMII_A, /* A indicates MACs 1-4 */ - QSGMII_B, /* B indicates MACs 5-8 */ - QSGMII_C, /* C indicates MACs 9-12 */ - QSGMII_D, /* D indicates MACs 12-16 */ + QSGMII_A, + QSGMII_B, + QSGMII_C, + QSGMII_D, SERDES_PRCTL_COUNT }; diff --git a/drivers/net/ldpaa_eth/ls2080a.c b/drivers/net/ldpaa_eth/ls2080a.c index 93ed4f18fe..673e428a40 100644 --- a/drivers/net/ldpaa_eth/ls2080a.c +++ b/drivers/net/ldpaa_eth/ls2080a.c @@ -79,3 +79,33 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) return PHY_INTERFACE_MODE_NONE; } + +void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) +{ + switch (lane_prtcl) { + case QSGMII_A: + wriop_init_dpmac(sd, 5, (int)lane_prtcl); + wriop_init_dpmac(sd, 6, (int)lane_prtcl); + wriop_init_dpmac(sd, 7, (int)lane_prtcl); + wriop_init_dpmac(sd, 8, (int)lane_prtcl); + break; + case QSGMII_B: + wriop_init_dpmac(sd, 1, (int)lane_prtcl); + wriop_init_dpmac(sd, 2, (int)lane_prtcl); + wriop_init_dpmac(sd, 3, (int)lane_prtcl); + wriop_init_dpmac(sd, 4, (int)lane_prtcl); + break; + case QSGMII_C: + wriop_init_dpmac(sd, 13, (int)lane_prtcl); + wriop_init_dpmac(sd, 14, (int)lane_prtcl); + wriop_init_dpmac(sd, 15, (int)lane_prtcl); + wriop_init_dpmac(sd, 16, (int)lane_prtcl); + break; + case QSGMII_D: + wriop_init_dpmac(sd, 9, (int)lane_prtcl); + wriop_init_dpmac(sd, 10, (int)lane_prtcl); + wriop_init_dpmac(sd, 11, (int)lane_prtcl); + wriop_init_dpmac(sd, 12, (int)lane_prtcl); + break; + } +} diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h index 6dc159d9d7..8ae0fc071e 100644 --- a/include/fsl-mc/ldpaa_wriop.h +++ b/include/fsl-mc/ldpaa_wriop.h @@ -68,4 +68,5 @@ phy_interface_t wriop_get_enet_if(int); void wriop_dpmac_disable(int); void wriop_dpmac_enable(int); phy_interface_t wriop_dpmac_enet_if(int, int); +void wriop_init_dpmac_qsgmii(int, int); #endif /* __LDPAA_WRIOP_H */ From 7b45b383fd0a05e6b6ee42676210b728596c86bc Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Wed, 15 Feb 2017 20:40:35 +0530 Subject: [PATCH 09/30] armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding SerDes information is not necessary to be present in RCWSR29 register. It may vary from SoC to SoC. So Avoid RCWSR28 register hard-coding. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- .../armv8/fsl-layerscape/fsl_lsch3_serdes.c | 28 +++++++++++-------- .../asm/arch-fsl-layerscape/immap_lsch3.h | 9 ++++++ 2 files changed, 25 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index c2fc6468e1..955e0b7478 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -51,20 +51,22 @@ int is_serdes_configured(enum srds_prtcl device) int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - u32 cfg = gur_in32(&gur->rcwsr[28]); + u32 cfg = 0; int i; switch (sd) { #ifdef CONFIG_SYS_FSL_SRDS_1 case FSL_SRDS_1: - cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; - cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); + cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; break; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 case FSL_SRDS_2: - cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; - cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); + cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT; break; #endif default: @@ -83,8 +85,8 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) return -ENODEV; } -void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, - u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) +void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, + u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 cfg; @@ -95,7 +97,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); - cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; + cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask; cfg >>= sd_prctl_shift; printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); @@ -152,15 +154,17 @@ void fsl_serdes_init(void) #ifdef CONFIG_SYS_FSL_SRDS_1 serdes_init(FSL_SRDS_1, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK, - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT, + FSL_CHASSIS3_SRDS1_REGSR, + FSL_CHASSIS3_SRDS1_PRTCL_MASK, + FSL_CHASSIS3_SRDS1_PRTCL_SHIFT, serdes1_prtcl_map); #endif #ifdef CONFIG_SYS_FSL_SRDS_2 serdes_init(FSL_SRDS_2, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK, - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT, + FSL_CHASSIS3_SRDS2_REGSR, + FSL_CHASSIS3_SRDS2_PRTCL_MASK, + FSL_CHASSIS3_SRDS2_PRTCL_SHIFT, serdes2_prtcl_map); #endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 08ea8fb8ef..80c421f710 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -230,10 +230,19 @@ struct ccsr_gur { #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +#if defined(CONFIG_ARCH_LS2080A) #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 29 +#endif #define RCW_SB_EN_REG_INDEX 9 #define RCW_SB_EN_MASK 0x00000400 From 38a5c57ac57614079061678bec277b330e958041 Mon Sep 17 00:00:00 2001 From: Suresh Gupta Date: Tue, 21 Feb 2017 14:26:46 +0530 Subject: [PATCH 10/30] spi: fsl_qspi: Add support for single chip select MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SOC’s like LS1012A has only one chip select signal for QSPI flash. Avoid scanning other flash. Signed-off-by: Suresh Gupta Reviewed-by: York Sun --- drivers/spi/fsl_qspi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index b2a058380f..e61c67b088 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -1037,8 +1037,11 @@ static int fsl_qspi_probe(struct udevice *bus) * setting the size of these devices to 0. This would ensure * that the complete memory map is assigned to only one flash device. */ - qspi_write32(priv->flags, &priv->regs->sfa1ad, priv->amba_base[1]); + qspi_write32(priv->flags, &priv->regs->sfa1ad, + priv->amba_base[0] + amba_size_per_chip); switch (priv->num_chipselect) { + case 1: + break; case 2: qspi_write32(priv->flags, &priv->regs->sfa2ad, priv->amba_base[1]); From 2652a28fee2f1e804afeb3373eca5c237f59218e Mon Sep 17 00:00:00 2001 From: Suresh Gupta Date: Tue, 21 Feb 2017 14:26:47 +0530 Subject: [PATCH 11/30] armv8: dts: fsl-ls1012a: Change number of CS in SPI node LS1012A has only one chip select for QSPI flash. Signed-off-by: Suresh Gupta Reviewed-by: York Sun --- arch/arm/dts/fsl-ls1012a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index ed5ea54a5e..23b3cec434 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -114,7 +114,7 @@ reg = <0x0 0x1550000 0x0 0x10000>, <0x0 0x40000000 0x0 0x4000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - num-cs = <2>; + num-cs = <1>; big-endian; status = "disabled"; }; From dd48f0bfb5d44475481f2808338b90848d4a01e7 Mon Sep 17 00:00:00 2001 From: Ashish kumar Date: Thu, 23 Feb 2017 16:03:57 +0530 Subject: [PATCH 12/30] armv8: fsl-lsch3: Conditionally apply workaround for erratum a0009203 This i2c errata only applies to LS2080A and its variants, namely LS2080A, LS2085A and LS2088A. Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a99b1c6a99..8edbf4d267 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -73,6 +73,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 + select SYS_FSL_ERRATUM_A009203 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F @@ -307,6 +308,9 @@ config SYS_FSL_ERRATUM_A008585 config SYS_FSL_ERRATUM_A008850 bool +config SYS_FSL_ERRATUM_A009203 + bool + config SYS_FSL_ERRATUM_A009635 bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index b54a937971..9e3cdd78af 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -152,6 +152,7 @@ static void erratum_rcw_src(void) * This erratum requires setting glitch_en bit to enable * digital glitch filter to improve clock stability. */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009203 static void erratum_a009203(void) { u8 __iomem *ptr; @@ -178,6 +179,7 @@ static void erratum_a009203(void) #endif #endif } +#endif void bypass_smmu(void) { @@ -191,7 +193,9 @@ void fsl_lsch3_early_init_f(void) { erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009203 erratum_a009203(); +#endif erratum_a008514(); erratum_a008336(); #ifdef CONFIG_CHAIN_OF_TRUST From 33ed57495ae7b442b364ff3ab55a836544700d5e Mon Sep 17 00:00:00 2001 From: yuan linyu Date: Sun, 26 Feb 2017 08:38:27 +0800 Subject: [PATCH 13/30] tools: plbimage support generate rcw file some system will not generate pbl format u-boot, but require rcw. Signed-off-by: yuan linyu Reviewed-by: Alison Wang Reviewed-by: York Sun --- tools/pblimage.c | 48 +++++++++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/tools/pblimage.c b/tools/pblimage.c index 16d94c98c6..ffc3268209 100644 --- a/tools/pblimage.c +++ b/tools/pblimage.c @@ -194,17 +194,20 @@ void pbl_load_uboot(int ifd, struct image_tool_params *params) pbl_parser(params->imagename); /* parse the pbi.cfg file. */ - pbl_parser(params->imagename2); + if (params->imagename2[0] != '\0') + pbl_parser(params->imagename2); - fp_uboot = fopen(params->datafile, "r"); - if (fp_uboot == NULL) { - printf("Error: %s open failed\n", params->datafile); - exit(EXIT_FAILURE); + if (params->datafile) { + fp_uboot = fopen(params->datafile, "r"); + if (fp_uboot == NULL) { + printf("Error: %s open failed\n", params->datafile); + exit(EXIT_FAILURE); + } + + load_uboot(fp_uboot); + fclose(fp_uboot); } - - load_uboot(fp_uboot); add_end_cmd(); - fclose(fp_uboot); lseek(ifd, 0, SEEK_SET); size = pbl_size; @@ -265,21 +268,24 @@ int pblimage_check_params(struct image_tool_params *params) if (!params) return EXIT_FAILURE; - fp_uboot = fopen(params->datafile, "r"); - if (fp_uboot == NULL) { - printf("Error: %s open failed\n", params->datafile); - exit(EXIT_FAILURE); - } - fd = fileno(fp_uboot); + if (params->datafile) { + fp_uboot = fopen(params->datafile, "r"); + if (fp_uboot == NULL) { + printf("Error: %s open failed\n", params->datafile); + exit(EXIT_FAILURE); + } + fd = fileno(fp_uboot); - if (fstat(fd, &st) == -1) { - printf("Error: Could not determine u-boot image size. %s\n", - strerror(errno)); - exit(EXIT_FAILURE); - } + if (fstat(fd, &st) == -1) { + printf("Error: Could not determine u-boot image size. %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } - /* For the variable size, we need to pad it to 64 byte boundary */ - uboot_size = roundup(st.st_size, 64); + /* For the variable size, pad it to 64 byte boundary */ + uboot_size = roundup(st.st_size, 64); + fclose(fp_uboot); + } if (params->arch == IH_ARCH_ARM) { arch_flag = IH_ARCH_ARM; From 3d8553f0a3eea4a0b9b2f6b3ce247fee9c4232f2 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 3 Mar 2017 12:35:09 +0800 Subject: [PATCH 14/30] pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 46 +++++++++++++++++++++++++ drivers/pci/pcie_layerscape.c | 35 +++++++++++++++++++ drivers/pci/pcie_layerscape.h | 8 +++++ 3 files changed, 89 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 78e250c1cc..cebbb0fec5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -89,6 +89,49 @@ static inline void early_mmu_setup(void) set_sctlr(get_sctlr() | CR_M); } +static void fix_pcie_mmu_map(void) +{ +#ifdef CONFIG_LS2080A + unsigned int i; + u32 svr, ver; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + svr = gur_in32(&gur->svr); + ver = SVR_SOC_VER(svr); + + /* Fix PCIE base and size for LS2088A */ + if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) || + (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) { + for (i = 0; i < ARRAY_SIZE(final_map); i++) { + switch (final_map[i].phys) { + case CONFIG_SYS_PCIE1_PHYS_ADDR: + final_map[i].phys = 0x2000000000ULL; + final_map[i].virt = 0x2000000000ULL; + final_map[i].size = 0x800000000ULL; + break; + case CONFIG_SYS_PCIE2_PHYS_ADDR: + final_map[i].phys = 0x2800000000ULL; + final_map[i].virt = 0x2800000000ULL; + final_map[i].size = 0x800000000ULL; + break; + case CONFIG_SYS_PCIE3_PHYS_ADDR: + final_map[i].phys = 0x3000000000ULL; + final_map[i].virt = 0x3000000000ULL; + final_map[i].size = 0x800000000ULL; + break; + case CONFIG_SYS_PCIE4_PHYS_ADDR: + final_map[i].phys = 0x3800000000ULL; + final_map[i].virt = 0x3800000000ULL; + final_map[i].size = 0x800000000ULL; + break; + default: + break; + } + } + } +#endif +} + /* * The final tables look similar to early tables, but different in detail. * These tables are in DRAM. Sub tables are added to enable cache for @@ -103,6 +146,9 @@ static inline void final_mmu_setup(void) unsigned int el = current_el(); int index; + /* fix the final_map before filling in the block entries */ + fix_pcie_mmu_map(); + mem_map = final_map; /* Update mapping for DDR to actual size */ diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 47dd806ad2..1c5a33ac28 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -167,6 +167,27 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie) pci_get_regions(pcie->bus, &io, &mem, &pref); idx = PCIE_ATU_REGION_INDEX1 + 1; + /* Fix the pcie memory map for LS2088A series SoCs */ + svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; + if (svr == SVR_LS2088A || svr == SVR_LS2084A || + svr == SVR_LS2048A || svr == SVR_LS2044A) { + if (io) + io->phys_start = (io->phys_start & + (PCIE_PHYS_SIZE - 1)) + + LS2088A_PCIE1_PHYS_ADDR + + LS2088A_PCIE_PHYS_SIZE * pcie->idx; + if (mem) + mem->phys_start = (mem->phys_start & + (PCIE_PHYS_SIZE - 1)) + + LS2088A_PCIE1_PHYS_ADDR + + LS2088A_PCIE_PHYS_SIZE * pcie->idx; + if (pref) + pref->phys_start = (pref->phys_start & + (PCIE_PHYS_SIZE - 1)) + + LS2088A_PCIE1_PHYS_ADDR + + LS2088A_PCIE_PHYS_SIZE * pcie->idx; + } + if (io) /* ATU : OUTBOUND : IO */ ls_pcie_atu_outbound_set(pcie, idx++, @@ -449,6 +470,7 @@ static int ls_pcie_probe(struct udevice *dev) u8 header_type; u16 link_sta; bool ep_mode; + uint svr; int ret; pcie->bus = dev; @@ -502,6 +524,19 @@ static int ls_pcie_probe(struct udevice *dev) return ret; } + /* + * Fix the pcie memory map address and PF control registers address + * for LS2088A series SoCs + */ + svr = get_svr(); + svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; + if (svr == SVR_LS2088A || svr == SVR_LS2084A || + svr == SVR_LS2048A || svr == SVR_LS2044A) { + pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + + LS2088A_PCIE_PHYS_SIZE * pcie->idx; + pcie->ctrl = pcie->lut + 0x40000; + } + pcie->cfg0 = map_physmem(pcie->cfg_res.start, fdt_resource_size(&pcie->cfg_res), MAP_NOCACHE); diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 0f9d2fe6d3..e3324a5e52 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -26,6 +26,10 @@ #define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR #endif +#define PCIE_PHYS_SIZE 0x200000000 +#define LS2088A_PCIE_PHYS_SIZE 0x800000000 +#define LS2088A_PCIE1_PHYS_ADDR 0x2000000000 + /* iATU registers */ #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) @@ -109,6 +113,10 @@ #define SVR_LS102XA 0 #define SVR_VAR_PER_SHIFT 8 #define SVR_LS102XA_MASK 0x700 +#define SVR_LS2088A 0x870900 +#define SVR_LS2084A 0x870910 +#define SVR_LS2048A 0x870920 +#define SVR_LS2044A 0x870930 /* LS1021a PCIE space */ #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL From 0aaa1a90b3ac806808971c8f5729c59ca7abff67 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 3 Mar 2017 12:35:10 +0800 Subject: [PATCH 15/30] pci: layerscape: Fixup device tree node for ls2088a LS2088A and its variants have different PCIe node than LS2080A. The compatible string is updated accordingly. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- drivers/pci/pcie_layerscape_fixup.c | 35 ++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 19ede2f104..64e461eabc 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -72,19 +72,26 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie, u32 *prop; u32 phandle; int nodeoffset; + uint svr; + char *compat = NULL; /* find pci controller node */ nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", pcie->dbi_res.start); if (nodeoffset < 0) { #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ - nodeoffset = fdt_node_offset_by_compat_reg(blob, - CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start); + svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; + if (svr == SVR_LS2088A || svr == SVR_LS2084A || + svr == SVR_LS2048A || svr == SVR_LS2044A) + compat = "fsl,ls2088a-pcie"; + else + compat = CONFIG_FSL_PCIE_COMPAT; + if (compat) + nodeoffset = fdt_node_offset_by_compat_reg(blob, + compat, pcie->dbi_res.start); +#endif if (nodeoffset < 0) return; -#else - return; -#endif } /* get phandle to MSI controller */ @@ -146,19 +153,25 @@ static void fdt_fixup_pcie(void *blob) static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie) { int off; + uint svr; + char *compat = NULL; off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", pcie->dbi_res.start); if (off < 0) { #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ - off = fdt_node_offset_by_compat_reg(blob, - CONFIG_FSL_PCIE_COMPAT, - pcie->dbi_res.start); + svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; + if (svr == SVR_LS2088A || svr == SVR_LS2084A || + svr == SVR_LS2048A || svr == SVR_LS2044A) + compat = "fsl,ls2088a-pcie"; + else + compat = CONFIG_FSL_PCIE_COMPAT; + if (compat) + off = fdt_node_offset_by_compat_reg(blob, + compat, pcie->dbi_res.start); +#endif if (off < 0) return; -#else - return; -#endif } if (pcie->enabled) From 54ad7b5ab8ad4e5577e79f782582d1d0f79b4659 Mon Sep 17 00:00:00 2001 From: Santan Kumar Date: Tue, 7 Mar 2017 11:21:03 +0530 Subject: [PATCH 16/30] board: freescale: ls2080a/ls2088a: Enable PPA Enable PPA on LS2080A, LS2088A boards: -LS2080ARDB, LS2080AQDS -LS2088ARDB, LS2088AQDS Signed-off-by: Santan Kumar Signed-off-by: Abhimanyu Saini Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + board/freescale/ls2080aqds/ls2080aqds.c | 7 +++++++ board/freescale/ls2080ardb/ls2080ardb.c | 5 +++++ configs/ls2080aqds_defconfig | 1 + configs/ls2080ardb_defconfig | 1 + 5 files changed, 15 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 8edbf4d267..0068d3c1fa 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -149,6 +149,7 @@ config SYS_LS_PPA_FW_ADDR hex "Address of PPA firmware loading from" depends on FSL_LS_PPA default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT + default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A default 0x60500000 if SYS_LS_PPA_FW_IN_XIP help If the PPA firmware locate at XIP flash, such as NOR or diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index e1de799ee5..6da9c6cfe8 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -19,6 +19,8 @@ #include #include #include +#include + #include "../common/qixis.h" #include "ls2080aqds_qixis.h" @@ -224,6 +226,11 @@ int board_init(void) #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); rtc_enable_32khz_output(); + +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + #ifdef CONFIG_FSL_CAAM sec_init(); #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 6d410c05e9..ea05ec6f65 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "../common/qixis.h" @@ -181,6 +182,10 @@ int board_init(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + #ifdef CONFIG_FSL_MC_ENET /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 0344d5f4a9..fb9a3e4041 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080AQDS=y +CONFIG_FSL_LS_PPA=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index c4d8204dae..a1e552d69a 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y +CONFIG_FSL_LS_PPA=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y From 7f33963289e73f5d29a5574a2ca908f99a93be23 Mon Sep 17 00:00:00 2001 From: Wenbin Song Date: Fri, 24 Mar 2017 18:05:48 +0800 Subject: [PATCH 17/30] armv8: ls1043a/ls1046aqds: fix the offsets of MTD partitions on NOR flash Fix the offsets of MTD partitions on Nor flash on ls1043ardb, ls1043aqds and ls1046aqds boards. Delete the rcw, uboot env and fman partitions. Add user partitions for general usage. Signed-off-by: Wenbin Song Reviewed-by: York Sun --- include/configs/ls1043a_common.h | 14 ++++++++------ include/configs/ls1046aqds.h | 14 ++++++++------ 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 5a5f9516e3..1c5b6021db 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -187,12 +187,14 @@ #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ "5m(kernel),1m(dtb),9m(file_system)" #else -#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ - "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ - "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ - "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ - "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ - "40m(nor_bank4_fit);7e800000.flash:" \ +#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \ + "2m@0x100000(nor_bank0_uboot),"\ + "40m@0x1100000(nor_bank0_fit)," \ + "7m(nor_bank0_user)," \ + "2m@0x4100000(nor_bank4_uboot)," \ + "40m@0x5100000(nor_bank4_fit),"\ + "-(nor_bank4_user);" \ + "7e800000.flash:" \ "1m(nand_uboot),1m(nand_uboot_env)," \ "20m(nand_fit);spi0.0:1m(uboot)," \ "5m(kernel),1m(dtb),9m(file_system)" diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 4b3b21eaa1..476387d5ad 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -485,12 +485,14 @@ unsigned long get_board_ddr_clk(void); #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \ "14m(free)" #else -#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ - "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ - "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ - "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ - "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ - "40m(nor_bank4_fit);7e800000.flash:" \ +#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \ + "2m@0x100000(nor_bank0_uboot),"\ + "40m@0x1100000(nor_bank0_fit)," \ + "7m(nor_bank0_user)," \ + "2m@0x4100000(nor_bank4_uboot)," \ + "40m@0x5100000(nor_bank4_fit),"\ + "-(nor_bank4_user);" \ + "7e800000.flash:" \ "4m(nand_uboot),36m(nand_kernel)," \ "472m(nand_free);spi0.0:2m(uboot)," \ "14m(free)" From 132a1468dcc0bb79553bf2e219014cc8c527c8e6 Mon Sep 17 00:00:00 2001 From: Yingxi Yu Date: Thu, 16 Mar 2017 15:18:32 +0800 Subject: [PATCH 18/30] armv8/fsl-layerscape: fdt: Skip checking USB clock on LS1012A USB requires 100MHz clock. On LS1012A, a dedicated 100MHz is provided instead of SYSCLK (125MHz). Skipping checking SYSCLK for FDT fixup. Signed-off-by: Yingxi Yu Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 26d4a303a5..762a95b945 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -387,8 +387,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif +#ifndef CONFIG_LS1012A fsl_fdt_disable_usb(blob); - +#endif #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN fdt_fixup_gic(blob); #endif From d72158c045eacf5022b052bdc56a32bc98c89034 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 17 Mar 2017 16:12:30 +0800 Subject: [PATCH 19/30] mtd: nand: add initialization flag Add initialization flag to avoid initializing NAND Flash multiple times, otherwise it will calculate a wrong total size. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- drivers/mtd/nand/nand.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index 05512412b9..3ea2dcfb73 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -133,6 +133,16 @@ static void create_mtd_concat(void) void nand_init(void) { + static int initialized; + + /* + * Avoid initializing NAND Flash multiple times, + * otherwise it will calculate a wrong total size. + */ + if (initialized) + return; + initialized = 1; + #ifdef CONFIG_SYS_NAND_SELF_INIT board_nand_init(); #else From 203db38a94a424bb1ab6a91e85148e8a8ea795d0 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 17 Mar 2017 16:12:31 +0800 Subject: [PATCH 20/30] mtd: nand: remove nand size print from nand_init function Add nand_size() function to move the nand size print into initr_nand(). Remove nand size print from nand_init() to allow other function to call nand_init() without printing nand size. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- common/board_r.c | 1 + drivers/mtd/nand/nand.c | 7 +++++-- include/nand.h | 1 + 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/common/board_r.c b/common/board_r.c index 5c9e6987b9..3344913399 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -426,6 +426,7 @@ static int initr_nand(void) { puts("NAND: "); nand_init(); + printf("%lu MiB\n", nand_size() / 1024); return 0; } #endif diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index 3ea2dcfb73..168bac6055 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -131,6 +131,11 @@ static void create_mtd_concat(void) } #endif +unsigned long nand_size(void) +{ + return total_nand_size; +} + void nand_init(void) { static int initialized; @@ -152,8 +157,6 @@ void nand_init(void) nand_init_chip(i); #endif - printf("%lu MiB\n", total_nand_size / 1024); - #ifdef CONFIG_SYS_NAND_SELECT_DEVICE /* * Select the chip in the board/cpu specific driver diff --git a/include/nand.h b/include/nand.h index b6eb223fb6..a86552878e 100644 --- a/include/nand.h +++ b/include/nand.h @@ -28,6 +28,7 @@ #endif extern void nand_init(void); +unsigned long nand_size(void); #include #include From 75ce8ee4e4206fdfe5811d1ea7e5a313b97782f6 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 17 Mar 2017 16:12:32 +0800 Subject: [PATCH 21/30] fsl: PPA: add support PPA image loading from NAND and SD Signed-off-by: Hou Zhiqiang Reviewed-by: Jaehoon Chung Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 143 +++++++++++++++++++++++- 1 file changed, 142 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c index b68e87d657..b35ad5fb6f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include @@ -21,9 +22,17 @@ #include #endif +#ifdef CONFIG_SYS_LS_PPA_FW_IN_NAND +#include +#elif defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + int ppa_init(void) { - const void *ppa_fit_addr; + void *ppa_fit_addr; u32 *boot_loc_ptr_l, *boot_loc_ptr_h; int ret; @@ -34,10 +43,137 @@ int ppa_init(void) #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR; + debug("%s: PPA image load from XIP\n", __func__); +#else /* !CONFIG_SYS_LS_PPA_FW_IN_XIP */ + size_t fw_length, fdt_header_len = sizeof(struct fdt_header); + + /* Copy PPA image from MMC/SD/NAND to allocated memory */ +#ifdef CONFIG_SYS_LS_PPA_FW_IN_MMC + struct mmc *mmc; + int dev = CONFIG_SYS_MMC_ENV_DEV; + struct fdt_header *fitp; + u32 cnt; + u32 blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512; + + debug("%s: PPA image load from eMMC/SD\n", __func__); + + ret = mmc_initialize(gd->bd); + if (ret) { + printf("%s: mmc_initialize() failed\n", __func__); + return ret; + } + mmc = find_mmc_device(dev); + if (!mmc) { + printf("PPA: MMC cannot find device for PPA firmware\n"); + return -ENODEV; + } + + ret = mmc_init(mmc); + if (ret) { + printf("%s: mmc_init() failed\n", __func__); + return ret; + } + + fitp = malloc(roundup(fdt_header_len, 512)); + if (!fitp) { + printf("PPA: malloc failed for FIT header(size 0x%zx)\n", + roundup(fdt_header_len, 512)); + return -ENOMEM; + } + + cnt = DIV_ROUND_UP(fdt_header_len, 512); + debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n", + __func__, dev, blk, cnt); + ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, fitp); + if (ret != cnt) { + free(fitp); + printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n", + CONFIG_SYS_LS_PPA_FW_ADDR); + return -EIO; + } + + /* flush cache after read */ + flush_cache((ulong)fitp, cnt * 512); + + ret = fdt_check_header(fitp); + if (ret) { + free(fitp); + printf("%s: fdt_check_header() failed\n", __func__); + return ret; + } + + fw_length = fdt_totalsize(fitp); + free(fitp); + + fw_length = roundup(fw_length, 512); + ppa_fit_addr = malloc(fw_length); + if (!ppa_fit_addr) { + printf("PPA: malloc failed for PPA image(size 0x%zx)\n", + fw_length); + return -ENOMEM; + } + + cnt = DIV_ROUND_UP(fw_length, 512); + debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n", + __func__, dev, blk, cnt); + ret = mmc->block_dev.block_read(&mmc->block_dev, + blk, cnt, ppa_fit_addr); + if (ret != cnt) { + free(ppa_fit_addr); + printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n", + CONFIG_SYS_LS_PPA_FW_ADDR); + return -EIO; + } + + /* flush cache after read */ + flush_cache((ulong)ppa_fit_addr, cnt * 512); + +#elif defined(CONFIG_SYS_LS_PPA_FW_IN_NAND) + struct fdt_header fit; + + debug("%s: PPA image load from NAND\n", __func__); + + nand_init(); + ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR, + &fdt_header_len, (u_char *)&fit); + if (ret == -EUCLEAN) { + printf("NAND read of PPA FIT header at offset 0x%x failed\n", + CONFIG_SYS_LS_PPA_FW_ADDR); + return -EIO; + } + + ret = fdt_check_header(&fit); + if (ret) { + printf("%s: fdt_check_header() failed\n", __func__); + return ret; + } + + fw_length = fdt_totalsize(&fit); + + ppa_fit_addr = malloc(fw_length); + if (!ppa_fit_addr) { + printf("PPA: malloc failed for PPA image(size 0x%zx)\n", + fw_length); + return -ENOMEM; + } + + ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR, + &fw_length, (u_char *)ppa_fit_addr); + if (ret == -EUCLEAN) { + free(ppa_fit_addr); + printf("NAND read of PPA firmware at offset 0x%x failed\n", + CONFIG_SYS_LS_PPA_FW_ADDR); + return -EIO; + } + + /* flush cache after read */ + flush_cache((ulong)ppa_fit_addr, fw_length); #else #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined" #endif +#endif + #ifdef CONFIG_CHAIN_OF_TRUST ppa_img_addr = (uintptr_t)ppa_fit_addr; if (fsl_check_boot_mode_secure() != 0) { @@ -65,5 +201,10 @@ int ppa_init(void) boot_loc_ptr_l, boot_loc_ptr_h); ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h); +#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \ + defined(CONFIG_SYS_LS_PPA_FW_IN_NAND) + free(ppa_fit_addr); +#endif + return ret; } From 77bbe55d9272741eb206590271aea6cc91cf6bd9 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 17 Mar 2017 16:12:33 +0800 Subject: [PATCH 22/30] armv8: Kconfig: fsl-ppa: support load PPA from eMMC/SD and NAND Flash Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 0068d3c1fa..b24462bede 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -135,6 +135,8 @@ config FSL_LS_PPA choice prompt "FSL Layerscape PPA firmware loading-media select" depends on FSL_LS_PPA + default SYS_LS_PPA_FW_IN_MMC if SD_BOOT + default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT default SYS_LS_PPA_FW_IN_XIP config SYS_LS_PPA_FW_IN_XIP @@ -143,6 +145,16 @@ config SYS_LS_PPA_FW_IN_XIP Say Y here if the PPA firmware locate at XIP flash, such as NOR or QSPI flash. +config SYS_LS_PPA_FW_IN_MMC + bool "eMMC or SD Card" + help + Say Y here if the PPA firmware locate at eMMC/SD card. + +config SYS_LS_PPA_FW_IN_NAND + bool "NAND" + help + Say Y here if the PPA firmware locate at NAND flash. + endchoice config SYS_LS_PPA_FW_ADDR @@ -151,6 +163,9 @@ config SYS_LS_PPA_FW_ADDR default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A default 0x60500000 if SYS_LS_PPA_FW_IN_XIP + default 0x500000 if SYS_LS_PPA_FW_IN_MMC + default 0x500000 if SYS_LS_PPA_FW_IN_NAND + help If the PPA firmware locate at XIP flash, such as NOR or QSPI flash, this address is a directly memory-mapped. From f6bf0a2b14b9ab4e9b95013b710a5d560d980d69 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 17 Mar 2017 16:12:34 +0800 Subject: [PATCH 23/30] fsl-layerscape/ls104xardb: enable PPA support for eMMC/SD and NAND boot Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls1046ardb_emmc_defconfig | 1 + configs/ls1046ardb_sdcard_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 4f4ae5aeeb..ed429cb509 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" CONFIG_NAND_BOOT=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index e57c42b507..02b5b5434a 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_SD_BOOT=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 9beb050b90..711fc10ab6 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT" CONFIG_SD_BOOT=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 032aab3581..a3965f245f 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL" CONFIG_SD_BOOT=y From 08c5130d28c42016e9d8a7207388245cd5d2f91d Mon Sep 17 00:00:00 2001 From: Bharat Bhushan Date: Wed, 22 Mar 2017 12:06:25 +0530 Subject: [PATCH 24/30] armv8: fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h The stream ID allocation for Chasis 3.0 devices can be shared among LS1088, LS2088 and LS2080. Signed-off-by: Bharat Bhushan Reviewed-by: York Sun --- .../{ls2080a_stream_id.h => stream_id_lsch3.h} | 0 include/configs/ls2080a_common.h | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/include/asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h} (100%) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h similarity index 100% rename from arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h rename to arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 5072e20811..427f623e8c 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -13,7 +13,7 @@ #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 -#include +#include #include /* Link Definitions */ From a4954f9467fd720fc386ada6ec43833a85078cce Mon Sep 17 00:00:00 2001 From: Bharat Bhushan Date: Wed, 22 Mar 2017 12:06:26 +0530 Subject: [PATCH 25/30] armv8: fsl-lsch3: Rewrite comment for stream IDs LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared same stream-id partitioning. This patch rewords the definition to support all these SOCs. Also have changes in description about iommu-map property updates in PCI node. Signed-off-by: Bharat Bhushan Reviewed-by: York Sun --- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index ee28323f8c..d7d527d8f4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -8,11 +8,11 @@ #define __FSL_STREAM_ID_H /* - * Stream IDs on ls2080a devices are not hardwired and are - * programmed by sw. There are a limited number of stream IDs - * available, and the partitioning of them is scenario dependent. - * This header defines the partitioning between legacy, PCI, - * and DPAA2 devices. + * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a) + * devices are not hardwired and are programmed by sw. There are a limited + * number of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, + * PCI, and DPAA2 devices. * * This partitioning can be customized in this file depending * on the specific hardware config: @@ -29,6 +29,9 @@ * -set a msi-map entry in the PEXn controller node in the * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt * for more info on the msi-map definition) + * -set a iommu-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt + * for more info on the iommu-map definition) * * -DPAA2 * -u-boot will allocate a range of stream IDs to be used by the Management @@ -36,7 +39,7 @@ * -the MC is responsible for allocating and setting up 'isolation context * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. * - * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for + * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: * AMQ bit streamID bit From 5344c7b7833dbaad7fe468e38b5b0e98ced6d888 Mon Sep 17 00:00:00 2001 From: Bharat Bhushan Date: Wed, 22 Mar 2017 12:06:27 +0530 Subject: [PATCH 26/30] arvm8: pcie-layerscape: Define stream-ids for Layerscape Chassis-2 Layerscape Chassis-2 have PCIe device, some platform devices and DPAA1 devices which will use stream-ids for iommu level isolation as they are behind SMMU. This patch defines the stream-ids for Chassis-2 devices. DPAA1 is reserved for future use. Signed-off-by: Bharat Bhushan Reviewed-by: York Sun --- .../asm/arch-fsl-layerscape/stream_id_lsch2.h | 63 +++++++++++++++++++ include/configs/ls1043a_common.h | 1 + 2 files changed, 64 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h new file mode 100644 index 0000000000..b326fe5c40 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -0,0 +1,63 @@ +/* + * Copyright 2017 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* + * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices + * are not hardwired and are programmed by sw. There are a limited number + * of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, PCI, + * and DPAA1 devices. + * + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of stream IDs set aside for PCI in this + * file. U-boot will scan the PCI bus and for each device discovered: + * -allocate a streamID + * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' + * -set a msi-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt + * for more info on the msi-map definition) + * -set a iommu-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt + * for more info on the iommu-map definition) + * + * -DPAA1 + * - Stream ids for DPAA1 use are reserved for future usecase. + * + */ + + +#define FSL_INVALID_STREAM_ID 0 + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_USB3_STREAM_ID 3 +#define FSL_SDHC_STREAM_ID 4 +#define FSL_SATA_STREAM_ID 5 +#define FSL_QE_STREAM_ID 6 +#define FSL_QDMA_STREAM_ID 7 +#define FSL_EDMA_STREAM_ID 8 +#define FSL_ETR_STREAM_ID 9 + +/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START 11 +#define FSL_PEX_STREAM_ID_END 26 + +/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ +#define FSL_DPAA1_STREAM_ID_START 27 +#define FSL_DPAA1_STREAM_ID_END 63 + +#endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 1c5b6021db..46d54a0f0d 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -13,6 +13,7 @@ #define CONFIG_MP #define CONFIG_GICV2 +#include #include /* Link Definitions */ From b52a05076c55428b62557d09391767ea985d68af Mon Sep 17 00:00:00 2001 From: Bharat Bhushan Date: Wed, 22 Mar 2017 12:06:28 +0530 Subject: [PATCH 27/30] armv8: fsl-lsch2: Use Chassis-2 streamid definition for ls1046a LS1046A is Chassis-2 type SOC and shares same streamid definition, this patch adds using streamids for LS1046A. Signed-off-by: Bharat Bhushan Reviewed-by: York Sun --- include/configs/ls1046a_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 1ed7517e01..cb792961b8 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -13,6 +13,7 @@ #define CONFIG_GICV2 #include +#include /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) From 9f076dbe7ec3d1ea96e0d4f5d1bdc37273b88265 Mon Sep 17 00:00:00 2001 From: Bharat Bhushan Date: Wed, 22 Mar 2017 12:06:29 +0530 Subject: [PATCH 28/30] armv8: fsl-lsch2: Use Chassis-2 streamid definition for ls1012a LS1012A is Chassis-2 type SOC and shares same streamid definition. This patch adds using streamids for ls1012a Signed-off-by: Bharat Bhushan Reviewed-by: York Sun --- include/configs/ls1012a_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index af076725ba..1a0c7f8e5f 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -11,6 +11,7 @@ #define CONFIG_GICV2 #include +#include #define CONFIG_SUPPORT_RAW_INITRD From 47d1736231dcad185662222754e1015dc025f67a Mon Sep 17 00:00:00 2001 From: Bharat Bhushan Date: Wed, 22 Mar 2017 12:06:30 +0530 Subject: [PATCH 29/30] pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs Layerscape Chasis-2 also uses same PCIe controller as Chasis-3 and have similar PCI-Lut. Signed-off-by: Bharat Bhushan Reviewed-by: York Sun --- drivers/pci/pcie_layerscape_fixup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 64e461eabc..d7591bcff0 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -15,7 +15,7 @@ #include #include "pcie_layerscape.h" -#ifdef CONFIG_FSL_LSCH3 +#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) /* * Return next available LUT index. */ @@ -188,7 +188,7 @@ void ft_pci_setup(void *blob, bd_t *bd) list_for_each_entry(pcie, &ls_pcie_list, list) ft_pcie_ls_setup(blob, pcie); -#ifdef CONFIG_FSL_LSCH3 +#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) fdt_fixup_pcie(blob); #endif } From 78be6222b01efa12d9267876ad1d1d0daf38dfa0 Mon Sep 17 00:00:00 2001 From: Bharat Bhushan Date: Wed, 22 Mar 2017 12:12:33 +0530 Subject: [PATCH 30/30] pcie-layerscape: Fixup iommu-map property of pci node This patch fixup iommu-map property on pci node to have a valid mapping of requester-id to stream-id. The requester-id to stream-id mapping is based on PCI-LUT table initialization. Signed-off-by: Bharat Bhushan Reviewed-by: York Sun --- drivers/pci/pcie_layerscape_fixup.c | 55 +++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index d7591bcff0..d504bbda37 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -110,6 +110,58 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie, fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); } +/* + * An iommu-map is a property to be added to the pci controller + * node. It is a table, where each entry consists of 4 fields + * e.g.: + * + * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count] + * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>; + */ +static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie, + u32 devid, u32 streamid) +{ + u32 *prop; + u32 iommu_map[4]; + int nodeoffset; + int lenp; + + /* find pci controller node */ + nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", + pcie->dbi_res.start); + if (nodeoffset < 0) { +#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ + nodeoffset = fdt_node_offset_by_compat_reg(blob, + CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start); + if (nodeoffset < 0) + return; +#else + return; +#endif + } + + /* get phandle to iommu controller */ + prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp); + if (prop == NULL) { + debug("\n%s: ERROR: missing iommu-map: PCIe%d\n", + __func__, pcie->idx); + return; + } + + /* set iommu-map row */ + iommu_map[0] = cpu_to_fdt32(devid); + iommu_map[1] = *++prop; + iommu_map[2] = cpu_to_fdt32(streamid); + iommu_map[3] = cpu_to_fdt32(1); + + if (devid == 0) { + fdt_setprop_inplace(blob, nodeoffset, "iommu-map", + iommu_map, 16); + } else { + fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16); + } +} + static void fdt_fixup_pcie(void *blob) { struct udevice *dev, *bus; @@ -146,6 +198,9 @@ static void fdt_fixup_pcie(void *blob) /* update msi-map in device tree */ fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, streamid); + /* update iommu-map in device tree */ + fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8, + streamid); } } #endif