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omap730p2: Remove board
Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Tom Rini
parent
abcaa6ee2a
commit
79c5c08d7c
11 changed files with 3 additions and 1766 deletions
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@ -1,9 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := omap730p2.o flash.o
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obj-y += lowlevel_init.o
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@ -1,91 +0,0 @@
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u-boot for the TI OMAP730 Perseus2
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Dave Peverley, MPC-Data Limited
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http://www.mpc-data.co.uk
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Overview :
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As the OMAP730 is similar to the OMAP1610 in many ways, this port was based
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on the u-boot port to the OMAP1610 Innovator. Supported features are :
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- Serial terminal support
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- Onboard NOR Flash
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- Ethernet via the seperate debug board
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- Tested on Rev4 and Rev5 boards
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It has also been tested to work correctly when built with a 'standard' GCC
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3.2.1 cross-compiler as well as Montavista Linux CEE 3.1's toolchain.
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Hardware Configuration :
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The main dips on the P2 board should be set to 2,3,7 and 9 on with all
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others off. On the debug board, dips 1 and 7 should be on with the rest off.
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The serial console has been set up to run from the DB9 connector on the
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P2 board at 115200 baud, 8 data bits, no stop bits, 1 parity bit.
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It should be noted that the P2 board has NOR flash that is addressable via
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either CS0 or CS3. This mode can be changed via DIP9 on the P2 board.
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Installing u-boot for the P2 :
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You can simply build u-boot for the Perseus by following the instructions
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in the main readme file. The target configuration is "omap730p2_config".
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Once u-boot has been built, you should strip the executable so it can be
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loaded via CCS (which cant cope with the symbols in the ELF binary) :
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$ cp u-boot u-boot.out
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$ arm-linux-strip u-boot.out
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The method we've used for installing u-boot the first time on a P2 is
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as follows :
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1) Configure TI Code Composer Studio to connect to the P2 board via JTAG
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as described in the Users Guide.
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2) Set up the P2 to boot from CS3, and connect with CCS. Reset the CPU
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and run the "init_mmu" GEL script.
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3) Use the "Load Program" option to send the u-boot.out file to the P2 and
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run.
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At this point, u-boot should run and you will see the boot menu on your
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serial terminal. You can then load the u-boot image to memory :
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# loadb 0x10000000
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Send the "u-boot.bin" binary via the serial using Kermit. Once loaded
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you can self-flash u-boot :
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# protect off 1:0
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# erase 1:0
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# cp.b 0x10000000 0x0 0x20000
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You should now be able to reset the board and run u-boot from flash.
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Alternative flash option :
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Sometimes, if you've been silly, you can get the board into a state where
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whats in flash has upset the board so much that you can no longer connect
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to the P2 via JTAG. However, you can set DIP9 to off to swap the boot mode
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of the P2 so that you boot from RAM instead of NOR flash. This moves NOR
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flash up to 0x0C000000. You can build a special version of u-boot to
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utilise this by the following config :
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$ make omap730p2_cs0boot_config
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If you load this up via CCS it will detect flash at its alternate location
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and allow you to programme your u-boot image (which, remember must be built
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for CS3 boot!) Once you do this, you can revert to CS3 boot and it will work
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fine again.
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Errata :
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1) It's been observed that sometimes the tftp transfer of kernels to the
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board can have checksum errors or stall. This appears to be an issue
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with the lan91c96.c driver, and can normally be worked around by
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resetting the board and trying again.
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@ -1,25 +0,0 @@
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#
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# (C) Copyright 2002
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# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# (C) Copyright 2003
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# Texas Instruments, <www.ti.com>
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# Kshitij Gupta <Kshitij@ti.com>
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#
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# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu
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# see http://www.ti.com/ for more information on Texas Instruments
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#
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# Innovator has 1 bank of 256 MB SDRAM
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# Physical Address:
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# 1000'0000 to 2000'0000
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#
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#
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# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
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# (mem base + reserved)
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#
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# we load ourself to 1108'0000
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#
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#
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CONFIG_SYS_TEXT_BASE = 0x11080000
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@ -1,463 +0,0 @@
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/*
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* (C) Copyright 2001
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/byteorder/swab.h>
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#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/* Board support for 1 or 2 flash devices */
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#undef FLASH_PORT_WIDTH32
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#define FLASH_PORT_WIDTH16
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#ifdef FLASH_PORT_WIDTH16
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#define FLASH_PORT_WIDTH ushort
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#define FLASH_PORT_WIDTHV vu_short
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#define SWAP(x) __swab16(x)
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#else
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#define FLASH_PORT_WIDTH ulong
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#define FLASH_PORT_WIDTHV vu_long
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#define SWAP(x) __swab32(x)
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#endif
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define mb() __asm__ __volatile__ ("" : : : "memory")
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/* Flash Organization Structure */
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typedef struct OrgDef {
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unsigned int sector_number;
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unsigned int sector_size;
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} OrgDef;
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/* Flash Organizations */
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OrgDef OrgIntel_28F256L18T[] = {
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{4, 32 * 1024}, /* 4 * 32kBytes sectors */
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{255, 128 * 1024}, /* 255 * 128kBytes sectors */
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};
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/*-----------------------------------------------------------------------
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* Functions
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*/
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unsigned long flash_init (void);
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static ulong flash_get_size (FPW * addr, flash_info_t * info);
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static int write_data (flash_info_t * info, ulong dest, FPW data);
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static void flash_get_offsets (ulong base, flash_info_t * info);
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void inline spin_wheel (void);
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void flash_print_info (flash_info_t * info);
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void flash_unprotect_sectors (FPWV * addr);
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int flash_erase (flash_info_t * info, int s_first, int s_last);
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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int i;
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ulong size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
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switch (i) {
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case 0:
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flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
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flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
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break;
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default:
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panic ("configured too many flash banks!\n");
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break;
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}
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size += flash_info[i].size;
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}
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/* Protect monitor and environment sectors
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*/
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_SYS_FLASH_BASE,
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CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
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return size;
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_get_offsets (ulong base, flash_info_t * info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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return;
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}
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
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for (i = 0; i < info->sector_count; i++) {
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if (i > 255) {
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info->start[i] = base + (i * 0x8000);
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info->protect[i] = 0;
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} else {
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info->start[i] = base +
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(i * PHYS_FLASH_SECT_SIZE);
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info->protect[i] = 0;
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}
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}
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}
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t * info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_INTEL:
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printf ("INTEL ");
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break;
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default:
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printf ("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_28F256L18T:
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printf ("FLASH 28F256L18T\n");
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break;
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default:
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printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i], info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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return;
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}
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/*
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* The following code cannot be run from FLASH!
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*/
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static ulong flash_get_size (FPW * addr, flash_info_t * info)
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{
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volatile FPW value;
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/* Write auto select command: read Manufacturer ID */
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addr[0x5555] = (FPW) 0x00AA00AA;
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addr[0x2AAA] = (FPW) 0x00550055;
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addr[0x5555] = (FPW) 0x00900090;
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mb ();
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value = addr[0];
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switch (value) {
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case (FPW) INTEL_MANUFACT:
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info->flash_id = FLASH_MAN_INTEL;
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
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return (0); /* no or unknown flash */
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}
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mb ();
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value = addr[1]; /* device ID */
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switch (value) {
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case (FPW) (INTEL_ID_28F256L18T):
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info->flash_id += FLASH_28F256L18T;
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info->sector_count = 259;
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info->size = 0x02000000;
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break; /* => 32 MB */
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default:
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info->flash_id = FLASH_UNKNOWN;
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break;
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}
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if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
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printf ("** ERROR: sector count %d > max (%d) **\n",
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info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
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info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
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}
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
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return (info->size);
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}
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/* unprotects a sector for write and erase
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* on some intel parts, this unprotects the entire chip, but it
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* wont hurt to call this additional times per sector...
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*/
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void flash_unprotect_sectors (FPWV * addr)
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{
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#define PD_FINTEL_WSMS_READY_MASK 0x0080
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*addr = (FPW) 0x00500050; /* clear status register */
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/* this sends the clear lock bit command */
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*addr = (FPW) 0x00600060;
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*addr = (FPW) 0x00D000D0;
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t * info, int s_first, int s_last)
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{
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int flag, prot, sect;
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ulong type, start;
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int rcode = 0;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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} else {
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printf ("- no sectors to erase\n");
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}
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return 1;
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}
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type = (info->flash_id & FLASH_VENDMASK);
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if ((type != FLASH_MAN_INTEL)) {
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printf ("Can't erase unknown flash type %08lx - aborted\n",
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info->flash_id);
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return 1;
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}
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prot = 0;
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for (sect = s_first; sect <= s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot) {
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printf ("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf ("\n");
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}
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts ();
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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FPWV *addr = (FPWV *) (info->start[sect]);
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FPW status;
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printf ("Erasing sector %2d ... ", sect);
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flash_unprotect_sectors (addr);
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/* arm simple, non interrupt dependent timer */
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start = get_timer(0);
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*addr = (FPW) 0x00500050;/* clear status register */
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*addr = (FPW) 0x00200020;/* erase setup */
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*addr = (FPW) 0x00D000D0;/* erase confirm */
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while (((status =
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*addr) & (FPW) 0x00800080) !=
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(FPW) 0x00800080) {
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if (get_timer(start) >
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CONFIG_SYS_FLASH_ERASE_TOUT) {
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printf ("Timeout\n");
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/* suspend erase */
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*addr = (FPW) 0x00B000B0;
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/* reset to read mode */
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*addr = (FPW) 0x00FF00FF;
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rcode = 1;
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break;
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}
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}
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/* clear status register cmd. */
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*addr = (FPW) 0x00500050;
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*addr = (FPW) 0x00FF00FF;/* resest to read mode */
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printf (" done\n");
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}
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}
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if (flag)
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enable_interrupts();
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return rcode;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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* 4 - Flash not identified
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*/
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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{
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ulong cp, wp;
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FPW data;
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int count, i, l, rc, port_width;
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if (info->flash_id == FLASH_UNKNOWN) {
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return 4;
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}
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/* get lower word aligned address */
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#ifdef FLASH_PORT_WIDTH16
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wp = (addr & ~1);
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port_width = 2;
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#else
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wp = (addr & ~3);
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port_width = 4;
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#endif
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/*
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* handle unaligned start bytes
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*/
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if ((l = addr - wp) != 0) {
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data = 0;
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for (i = 0, cp = wp; i < l; ++i, ++cp) {
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data = (data << 8) | (*(uchar *) cp);
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}
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for (; i < port_width && cnt > 0; ++i) {
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data = (data << 8) | *src++;
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--cnt;
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++cp;
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}
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for (; cnt == 0 && i < port_width; ++i, ++cp) {
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data = (data << 8) | (*(uchar *) cp);
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}
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if ((rc = write_data (info, wp, SWAP (data))) != 0) {
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||||
return (rc);
|
||||
}
|
||||
wp += port_width;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
count = 0;
|
||||
while (cnt >= port_width) {
|
||||
data = 0;
|
||||
for (i = 0; i < port_width; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += port_width;
|
||||
cnt -= port_width;
|
||||
if (count++ > 0x800) {
|
||||
spin_wheel ();
|
||||
count = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i < port_width; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
return (write_data (info, wp, SWAP (data)));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word or halfword to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_data (flash_info_t * info, ulong dest, FPW data)
|
||||
{
|
||||
FPWV *addr = (FPWV *) dest;
|
||||
ulong status;
|
||||
int flag, rc = 0;
|
||||
ulong start;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*addr & data) != data) {
|
||||
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
|
||||
return (2);
|
||||
}
|
||||
flash_unprotect_sectors (addr);
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
*addr = (FPW) 0x00400040; /* write setup */
|
||||
*addr = data;
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
start = get_timer(0);
|
||||
|
||||
/* wait while polling the status register */
|
||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
rc = 1;
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
done:
|
||||
*addr = (FPW)0x00FF00FF; /* restore read mode */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
return rc;
|
||||
}
|
||||
|
||||
void inline spin_wheel (void)
|
||||
{
|
||||
static int p = 0;
|
||||
static char w[] = "\\/-";
|
||||
|
||||
printf ("\010%c", w[p]);
|
||||
(++p == 3) ? (p = 0) : 0;
|
||||
}
|
||||
|
|
@ -1,379 +0,0 @@
|
|||
/*
|
||||
* Board specific setup info
|
||||
*
|
||||
* (C) Copyright 2003-2004
|
||||
*
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Kshitij Gupta <Kshitij@ti.com>
|
||||
*
|
||||
* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
|
||||
*
|
||||
* Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
|
||||
* (http://www.mpc-data.co.uk)
|
||||
*
|
||||
* TODO : Tidy up and change to use system register defines
|
||||
* from omap730.h where possible.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
|
||||
#if defined(CONFIG_OMAP730)
|
||||
#include <./configs/omap730.h>
|
||||
#endif
|
||||
|
||||
_TEXT_BASE:
|
||||
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
/* Save callers address in r11 - r11 must never be modified */
|
||||
mov r11, lr
|
||||
|
||||
/*------------------------------------------------------*
|
||||
*mask all IRQs by setting all bits in the INTMR default*
|
||||
*------------------------------------------------------*/
|
||||
mov r1, #0xffffffff
|
||||
ldr r0, =REG_IHL1_MIR
|
||||
str r1, [r0]
|
||||
ldr r0, =REG_IHL2_MIR
|
||||
str r1, [r0]
|
||||
|
||||
/*------------------------------------------------------*
|
||||
* Set up ARM CLM registers (IDLECT1) *
|
||||
*------------------------------------------------------*/
|
||||
ldr r0, REG_ARM_IDLECT1
|
||||
ldr r1, VAL_ARM_IDLECT1
|
||||
str r1, [r0]
|
||||
|
||||
/*------------------------------------------------------*
|
||||
* Set up ARM CLM registers (IDLECT2) *
|
||||
*------------------------------------------------------*/
|
||||
ldr r0, REG_ARM_IDLECT2
|
||||
ldr r1, VAL_ARM_IDLECT2
|
||||
str r1, [r0]
|
||||
|
||||
/*------------------------------------------------------*
|
||||
* Set up ARM CLM registers (IDLECT3) *
|
||||
*------------------------------------------------------*/
|
||||
ldr r0, REG_ARM_IDLECT3
|
||||
ldr r1, VAL_ARM_IDLECT3
|
||||
str r1, [r0]
|
||||
|
||||
|
||||
mov r1, #0x01 /* PER_EN bit */
|
||||
ldr r0, REG_ARM_RSTCT2
|
||||
strh r1, [r0] /* CLKM; Peripheral reset. */
|
||||
|
||||
/* Set CLKM to Sync-Scalable */
|
||||
/* I supposedly need to enable the dsp clock before switching */
|
||||
mov r1, #0x1000
|
||||
ldr r0, REG_ARM_SYSST
|
||||
strh r1, [r0]
|
||||
mov r0, #0x400
|
||||
1:
|
||||
subs r0, r0, #0x1 /* wait for any bubbles to finish */
|
||||
bne 1b
|
||||
ldr r1, VAL_ARM_CKCTL
|
||||
ldr r0, REG_ARM_CKCTL
|
||||
strh r1, [r0]
|
||||
|
||||
/* a few nops to let settle */
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
/* setup DPLL 1 */
|
||||
/* Ramp up the clock to 96Mhz */
|
||||
ldr r1, VAL_DPLL1_CTL
|
||||
ldr r0, REG_DPLL1_CTL
|
||||
strh r1, [r0]
|
||||
ands r1, r1, #0x10 /* Check if PLL is enabled. */
|
||||
beq lock_end /* Do not look for lock if BYPASS selected */
|
||||
2:
|
||||
ldrh r1, [r0]
|
||||
ands r1, r1, #0x01 /* Check the LOCK bit.*/
|
||||
beq 2b /* loop until bit goes hi. */
|
||||
lock_end:
|
||||
|
||||
/*------------------------------------------------------*
|
||||
* Turn off the watchdog during init... *
|
||||
*------------------------------------------------------*/
|
||||
ldr r0, REG_WATCHDOG
|
||||
ldr r1, WATCHDOG_VAL1
|
||||
str r1, [r0]
|
||||
ldr r1, WATCHDOG_VAL2
|
||||
str r1, [r0]
|
||||
ldr r0, REG_WSPRDOG
|
||||
ldr r1, WSPRDOG_VAL1
|
||||
str r1, [r0]
|
||||
ldr r0, REG_WWPSDOG
|
||||
|
||||
watch1Wait:
|
||||
ldr r1, [r0]
|
||||
tst r1, #0x10
|
||||
bne watch1Wait
|
||||
|
||||
ldr r0, REG_WSPRDOG
|
||||
ldr r1, WSPRDOG_VAL2
|
||||
str r1, [r0]
|
||||
ldr r0, REG_WWPSDOG
|
||||
watch2Wait:
|
||||
ldr r1, [r0]
|
||||
tst r1, #0x10
|
||||
bne watch2Wait
|
||||
|
||||
/* Set memory timings corresponding to the new clock speed */
|
||||
|
||||
/* Check execution location to determine current execution location
|
||||
* and branch to appropriate initialization code.
|
||||
*/
|
||||
/* Compare physical SDRAM base & current execution location. */
|
||||
and r0, pc, #0xF0000000
|
||||
/* Compare. */
|
||||
cmp r0, #0
|
||||
/* Skip over EMIF-fast initialization if running from SDRAM. */
|
||||
bne skip_sdram
|
||||
|
||||
/*
|
||||
* Delay for SDRAM initialization.
|
||||
*/
|
||||
mov r3, #0x1800 /* value should be checked */
|
||||
3:
|
||||
subs r3, r3, #0x1 /* Decrement count */
|
||||
bne 3b
|
||||
|
||||
ldr r0, REG_SDRAM_CONFIG
|
||||
ldr r1, SDRAM_CONFIG_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, REG_SDRAM_MRS_LEGACY
|
||||
ldr r1, SDRAM_MRS_VAL
|
||||
str r1, [r0]
|
||||
|
||||
skip_sdram:
|
||||
|
||||
common_tc:
|
||||
/* slow interface */
|
||||
ldr r1, VAL_TC_EMIFS_CS0_CONFIG
|
||||
ldr r0, REG_TC_EMIFS_CS0_CONFIG
|
||||
str r1, [r0] /* Chip Select 0 */
|
||||
|
||||
ldr r1, VAL_TC_EMIFS_CS1_CONFIG
|
||||
ldr r0, REG_TC_EMIFS_CS1_CONFIG
|
||||
str r1, [r0] /* Chip Select 1 */
|
||||
ldr r1, VAL_TC_EMIFS_CS2_CONFIG
|
||||
ldr r0, REG_TC_EMIFS_CS2_CONFIG
|
||||
str r1, [r0] /* Chip Select 2 */
|
||||
ldr r1, VAL_TC_EMIFS_CS3_CONFIG
|
||||
ldr r0, REG_TC_EMIFS_CS3_CONFIG
|
||||
str r1, [r0] /* Chip Select 3 */
|
||||
|
||||
/* 48MHz clock request for UART1 */
|
||||
ldr r1, PERSEUS2_CONFIG_BASE
|
||||
ldrh r0, [r1, #CONFIG_PCC_CONF]
|
||||
orr r0, r0, #CONF_MOD_UART1_CLK_MODE_R
|
||||
strh r0, [r1, #CONFIG_PCC_CONF]
|
||||
|
||||
/* Initialize public and private rheas
|
||||
* - set access factor 2 on both rhea / strobe
|
||||
* - disable write buffer on strb0, enable write buffer on strb1
|
||||
*/
|
||||
|
||||
ldr R0, REG_RHEA_PUB_CTL
|
||||
ldr R1, REG_RHEA_PRIV_CTL
|
||||
ldr R2, VAL_RHEA_CTL
|
||||
strh R2, [R0]
|
||||
strh R2, [R1]
|
||||
mov R3, #2 /* disable write buffer on strb0, enable write buffer on strb1 */
|
||||
strh R3, [R0, #0x08] /* arm rhea control reg */
|
||||
strh R3, [R1, #0x08]
|
||||
|
||||
/* enable IRQ and FIQ */
|
||||
|
||||
mrs r4, CPSR
|
||||
bic r4, r4, #IRQ_MASK
|
||||
bic r4, r4, #FIQ_MASK
|
||||
msr CPSR, r4
|
||||
|
||||
/* set TAP CONF to TRI EMULATION */
|
||||
|
||||
ldr r1, [r0, #CONFIG_MODE2]
|
||||
bic r1, r1, #0x18
|
||||
orr r1, r1, #0x10
|
||||
str r1, [r0, #CONFIG_MODE2]
|
||||
|
||||
/* set tdbgen to 1 */
|
||||
|
||||
ldr r0, PERSEUS2_CONFIG_BASE
|
||||
ldr r1, [r0, #CONFIG_MODE1]
|
||||
mov r2, #0x10000
|
||||
orr r1, r1, r2
|
||||
str r1, [r0, #CONFIG_MODE1]
|
||||
|
||||
#ifdef CONFIG_P2_OMAP1610
|
||||
/* inserting additional 2 clock cycle hold time for LAN */
|
||||
ldr r0, REG_TC_EMIFS_CS1_ADVANCED
|
||||
ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
|
||||
str r1, [r0]
|
||||
#endif
|
||||
/* Start MPU Timer 1 */
|
||||
ldr r0, REG_MPU_LOAD_TIMER
|
||||
ldr r1, VAL_MPU_LOAD_TIMER
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, REG_MPU_CNTL_TIMER
|
||||
ldr r1, VAL_MPU_CNTL_TIMER
|
||||
str r1, [r0]
|
||||
|
||||
/* back to arch calling code */
|
||||
mov pc, r11
|
||||
|
||||
/* the literal pools origin */
|
||||
.ltorg
|
||||
|
||||
REG_TC_EMIFS_CONFIG: /* 32 bits */
|
||||
.word 0xfffecc0c
|
||||
REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
|
||||
.word 0xfffecc10
|
||||
REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
|
||||
.word 0xfffecc14
|
||||
REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
|
||||
.word 0xfffecc18
|
||||
REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
|
||||
.word 0xfffecc1c
|
||||
|
||||
#ifdef CONFIG_P2_OMAP730
|
||||
REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
|
||||
.word 0xfffecc54
|
||||
#endif
|
||||
|
||||
/* MPU clock/reset/power mode control registers */
|
||||
REG_ARM_CKCTL: /* 16 bits */
|
||||
.word 0xfffece00
|
||||
|
||||
REG_ARM_IDLECT3: /* 16 bits */
|
||||
.word 0xfffece24
|
||||
REG_ARM_IDLECT2: /* 16 bits */
|
||||
.word 0xfffece08
|
||||
REG_ARM_IDLECT1: /* 16 bits */
|
||||
.word 0xfffece04
|
||||
|
||||
REG_ARM_RSTCT2: /* 16 bits */
|
||||
.word 0xfffece14
|
||||
REG_ARM_SYSST: /* 16 bits */
|
||||
.word 0xfffece18
|
||||
/* DPLL control registers */
|
||||
REG_DPLL1_CTL: /* 16 bits */
|
||||
.word 0xfffecf00
|
||||
|
||||
/* Watch Dog register */
|
||||
/* secure watchdog stop */
|
||||
REG_WSPRDOG:
|
||||
.word 0xfffeb048
|
||||
/* watchdog write pending */
|
||||
REG_WWPSDOG:
|
||||
.word 0xfffeb034
|
||||
|
||||
WSPRDOG_VAL1:
|
||||
.word 0x0000aaaa
|
||||
WSPRDOG_VAL2:
|
||||
.word 0x00005555
|
||||
|
||||
/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
|
||||
counter @8192 rows, 10 ns, 8 burst */
|
||||
REG_SDRAM_CONFIG:
|
||||
.word 0xfffecc20
|
||||
|
||||
REG_SDRAM_MRS_LEGACY:
|
||||
.word 0xfffecc24
|
||||
|
||||
REG_WATCHDOG:
|
||||
.word 0xfffec808
|
||||
|
||||
REG_MPU_LOAD_TIMER:
|
||||
.word 0xfffec504
|
||||
REG_MPU_CNTL_TIMER:
|
||||
.word 0xfffec500
|
||||
|
||||
/* Public and private rhea bridge registers definition */
|
||||
|
||||
REG_RHEA_PUB_CTL:
|
||||
.word 0xFFFECA00
|
||||
|
||||
REG_RHEA_PRIV_CTL:
|
||||
.word 0xFFFED300
|
||||
|
||||
/* EMIFF SDRAM Configuration register
|
||||
- self refresh disable
|
||||
- auto refresh enabled
|
||||
- SDRAM type 64 Mb, 16 bits bus 4 banks
|
||||
- power down enabled
|
||||
- SDRAM clock disabled
|
||||
*/
|
||||
SDRAM_CONFIG_VAL:
|
||||
.word 0x0C017DF4
|
||||
|
||||
/* Burst full page length ; cas latency = 3 */
|
||||
SDRAM_MRS_VAL:
|
||||
.word 0x00000037
|
||||
|
||||
VAL_ARM_CKCTL:
|
||||
.word 0x6505
|
||||
VAL_DPLL1_CTL:
|
||||
.word 0x3412
|
||||
|
||||
#ifdef CONFIG_P2_OMAP730
|
||||
VAL_TC_EMIFS_CS0_CONFIG:
|
||||
.word 0x0000FFF3
|
||||
VAL_TC_EMIFS_CS1_CONFIG:
|
||||
.word 0x00004278
|
||||
VAL_TC_EMIFS_CS2_CONFIG:
|
||||
.word 0x00004278
|
||||
VAL_TC_EMIFS_CS3_CONFIG:
|
||||
.word 0x00004278
|
||||
VAL_TC_EMIFS_CS1_ADVANCED:
|
||||
.word 0x00000022
|
||||
#endif
|
||||
|
||||
VAL_ARM_IDLECT1:
|
||||
.word 0x00000400
|
||||
VAL_ARM_IDLECT2:
|
||||
.word 0x00000886
|
||||
VAL_ARM_IDLECT3:
|
||||
.word 0x00000015
|
||||
|
||||
WATCHDOG_VAL1:
|
||||
.word 0x000000f5
|
||||
WATCHDOG_VAL2:
|
||||
.word 0x000000a0
|
||||
|
||||
VAL_MPU_LOAD_TIMER:
|
||||
.word 0xffffffff
|
||||
VAL_MPU_CNTL_TIMER:
|
||||
.word 0xffffffa1
|
||||
|
||||
VAL_RHEA_CTL:
|
||||
.word 0xFF22
|
||||
|
||||
/* Config Register vals */
|
||||
PERSEUS2_CONFIG_BASE:
|
||||
.word 0xFFFE1000
|
||||
|
||||
.equ CONFIG_PCC_CONF, 0xB4
|
||||
.equ CONFIG_MODE1, 0x10
|
||||
.equ CONFIG_MODE2, 0x14
|
||||
.equ CONF_MOD_UART1_CLK_MODE_R, 0x0A
|
||||
|
||||
/* misc values */
|
||||
.equ IRQ_MASK, 0x80 /* IRQ mask value */
|
||||
.equ FIQ_MASK, 0x40 /* FIQ mask value */
|
||||
|
|
@ -1,255 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
*
|
||||
* (C) Copyright 2003
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Kshitij Gupta <Kshitij@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#if defined(CONFIG_OMAP730)
|
||||
#include <./configs/omap730.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int test_boot_mode(void);
|
||||
void spin_up_leds(void);
|
||||
void flash__init (void);
|
||||
void ether__init (void);
|
||||
void set_muxconf_regs (void);
|
||||
void peripheral_power_enable (void);
|
||||
|
||||
#define FLASH_ON_CS0 1
|
||||
#define FLASH_ON_CS3 0
|
||||
|
||||
static inline void delay (unsigned long loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n"
|
||||
"subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0" (loops));
|
||||
}
|
||||
|
||||
int test_boot_mode(void)
|
||||
{
|
||||
/* Check for CS0 and CS3 address decode swapping */
|
||||
if (*((volatile int *)EMIFS_CONFIG) & 0x00000002)
|
||||
return(FLASH_ON_CS3);
|
||||
else
|
||||
return(FLASH_ON_CS0);
|
||||
}
|
||||
|
||||
/* Toggle backup LED indication */
|
||||
void toggle_backup_led(void)
|
||||
{
|
||||
static int backupLEDState = 0; /* Init variable so that the LED will be ON the first time */
|
||||
volatile unsigned int *IOConfReg;
|
||||
|
||||
|
||||
IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT);
|
||||
|
||||
if (backupLEDState != 0) {
|
||||
*IOConfReg &= (0xFFFFEFFF);
|
||||
backupLEDState = 0;
|
||||
} else {
|
||||
*IOConfReg |= (0x00001000);
|
||||
backupLEDState = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
int board_init (void)
|
||||
{
|
||||
/* arch number of OMAP 730 P2 Board - Same as the Innovator! */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = 0x10000100;
|
||||
|
||||
/* Configure MUX settings */
|
||||
set_muxconf_regs ();
|
||||
|
||||
peripheral_power_enable ();
|
||||
|
||||
/* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */
|
||||
toggle_backup_led();
|
||||
|
||||
/* Hold GSM in reset until needed */
|
||||
*((volatile unsigned short *)M_CTL) &= ~1;
|
||||
|
||||
/*
|
||||
* CSx timings, GPIO Mux ... setup
|
||||
*/
|
||||
|
||||
/* Flash: CS0 timings setup */
|
||||
*((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3;
|
||||
*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088;
|
||||
|
||||
/* Ethernet support trough the debug board */
|
||||
/* CS1 timings setup */
|
||||
*((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3;
|
||||
*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000;
|
||||
|
||||
/* this speeds up your boot a quite a bit. However to make it
|
||||
* work, you need make sure your kernel startup flush bug is fixed.
|
||||
* ... rkw ...
|
||||
*/
|
||||
icache_enable ();
|
||||
|
||||
flash__init ();
|
||||
ether__init ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
******************************/
|
||||
void flash__init (void)
|
||||
{
|
||||
unsigned int regval;
|
||||
|
||||
regval = *((volatile unsigned int *) EMIFS_CONFIG);
|
||||
/* Turn off write protection for flash devices. */
|
||||
regval = regval | 0x0001;
|
||||
*((volatile unsigned int *) EMIFS_CONFIG) = regval;
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
Routine:ether__init
|
||||
Description: take the Ethernet controller out of reset and wait
|
||||
for the EEPROM load to complete.
|
||||
*************************************************************/
|
||||
void ether__init (void)
|
||||
{
|
||||
#define LAN_RESET_REGISTER 0x0400001c
|
||||
|
||||
*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
|
||||
do {
|
||||
*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
|
||||
udelay (100);
|
||||
} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
|
||||
|
||||
do {
|
||||
*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
|
||||
udelay (100);
|
||||
} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
|
||||
|
||||
#define ETH_CONTROL_REG 0x0400030b
|
||||
|
||||
*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
|
||||
udelay (100);
|
||||
}
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
******************************/
|
||||
int dram_init (void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************
|
||||
Routine: set_muxconf_regs
|
||||
Description: Setting up the configuration Mux registers
|
||||
specific to the hardware
|
||||
*******************************************************/
|
||||
void set_muxconf_regs (void)
|
||||
{
|
||||
volatile unsigned int *MuxConfReg;
|
||||
/* set each registers to its reset value; */
|
||||
|
||||
/*
|
||||
* Backup LED Indication
|
||||
*/
|
||||
|
||||
/* Configure MUXed pin. Mode 6: GPIO_140 */
|
||||
MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10);
|
||||
*MuxConfReg &= (0xFFFFFF1F); /* Clear D_MPU_LPG1 */
|
||||
*MuxConfReg |= 0x000000C0; /* Set D_MPU_LPG1 to 0x6 */
|
||||
|
||||
/* Configure GPIO_140 as output */
|
||||
MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL);
|
||||
*MuxConfReg &= (0xFFFFEFFF); /* Clear direction (output) for GPIO 140 */
|
||||
|
||||
/*
|
||||
* Configure GPIOs for battery charge & feedback
|
||||
*/
|
||||
|
||||
/* Configure MUXed pin. Mode 6: GPIO_35 */
|
||||
MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
|
||||
*MuxConfReg &= 0xFFFFFFF1; /* Clear M_CLK_OUT */
|
||||
*MuxConfReg |= 0x0000000C; /* Set M_CLK_OUT = 0x6 (GPIOs) */
|
||||
|
||||
/* Configure MUXed pin. Mode 6: GPIO_72,73,74 */
|
||||
MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5);
|
||||
*MuxConfReg &= 0xFFFF1FFF; /* Clear D_DDR */
|
||||
*MuxConfReg |= 0x0000C000; /* Set D_DDR = 0x6 (GPIOs) */
|
||||
|
||||
MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL);
|
||||
*MuxConfReg |= 0x00000100; /* Configure GPIO_72 as input */
|
||||
*MuxConfReg &= 0xFFFFFDFF; /* Configure GPIO_73 as output */
|
||||
|
||||
/*
|
||||
* Allow battery charge
|
||||
*/
|
||||
|
||||
MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT);
|
||||
*MuxConfReg &= (0xFFFFFDFF); /* Clear GPIO_73 pin */
|
||||
|
||||
/*
|
||||
* Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
|
||||
* It is used as the Ethernet controller interrupt
|
||||
*/
|
||||
MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9);
|
||||
*MuxConfReg &= 0x1FFFFFFF;
|
||||
}
|
||||
|
||||
/******************************************************
|
||||
Routine: peripheral_power_enable
|
||||
Description: Enable the power for UART1
|
||||
*******************************************************/
|
||||
void peripheral_power_enable (void)
|
||||
{
|
||||
volatile unsigned int *MuxConfReg;
|
||||
|
||||
|
||||
/* Set up pins used by UART */
|
||||
|
||||
/* Start UART clock (48MHz) */
|
||||
MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG);
|
||||
*MuxConfReg &= (0xFFFFFFF7);
|
||||
*MuxConfReg |= (0x00000008);
|
||||
|
||||
/* Get the UART pin in mode0 */
|
||||
MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
|
||||
*MuxConfReg &= (0xFF1FFFFF);
|
||||
*MuxConfReg &= (0xF1FFFFFF);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_NET
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_LAN91C96
|
||||
rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -213,9 +213,6 @@ Active arm arm926ejs mxs schulercontrol sc_sps_1
|
|||
Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
|
||||
Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
|
||||
Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya <rishi@ti.com>
|
||||
Active arm arm926ejs omap ti omap730p2 omap730p2 omap730p2:CS3_BOOT Dave Peverley <dpeverley@mpc-data.co.uk>
|
||||
Active arm arm926ejs omap ti omap730p2 omap730p2_cs0boot omap730p2:CS0_BOOT Dave Peverley <dpeverley@mpc-data.co.uk>
|
||||
Active arm arm926ejs omap ti omap730p2 omap730p2_cs3boot omap730p2:CS3_BOOT Dave Peverley <dpeverley@mpc-data.co.uk>
|
||||
Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD <albert.u.boot@aribaud.net>
|
||||
Active arm arm926ejs pantheon Marvell - dkb - Lei Wen <leiwen@marvell.com>
|
||||
Active arm arm926ejs spear spear - x600 x600 Stefan Roese <sr@denx.de>
|
||||
|
|
|
|||
|
|
@ -11,8 +11,9 @@ easily if here is something they might want to dig for...
|
|||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
pdnb3 arm ixp - 2013-09-24 Stefan Roese <sr@denx.de>
|
||||
scpu arm ixp - 2013-09-24 Stefan Roese <sr@denx.de>
|
||||
omap730p2 arm arm926ejs - 2013-11-11
|
||||
pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
|
||||
scpu arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
|
||||
omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij@ti.com>
|
||||
CANBT powerpc 405CR fb8f4fd 2013-08-07 Matthias Fuchs <matthias.fuchs@esd.eu>
|
||||
Alaska8220 powerpc mpc8220 d6ed322 2013-05-11
|
||||
|
|
|
|||
|
|
@ -1,120 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* TI H2 and P2 Debug Board hardware map
|
||||
*
|
||||
* Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
|
||||
* Author: MPC-Data Limited
|
||||
* Dave Peverley
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDED_H2_P2_DBH_BOARD_H
|
||||
#define __INCLUDED_H2_P2_DBH_BOARD_H
|
||||
|
||||
#include <asm/sizes.h>
|
||||
|
||||
/*
|
||||
* The Debug board is designed to function with the P2 Sample, H2
|
||||
* Sample and 1610 Innovator boards. The main difference AFAICT is
|
||||
* the chip selects used with each system ;
|
||||
*
|
||||
* P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs
|
||||
* H2 Sample : CS1a is used to select the CPLD registers.
|
||||
*
|
||||
*/
|
||||
|
||||
/***************************************************************************
|
||||
* CPLD Registers
|
||||
**************************************************************************/
|
||||
|
||||
#define H2DBG_CPLD_REVISION 0x04000010
|
||||
#define H2DBG_BOARD_REVISION 0x04000012
|
||||
#define H2DBG_GPIO_REGISTER 0x04000014
|
||||
#define H2DBG_LED_CONTROL 0x04000016
|
||||
#define H2DBG_MISC_INPUT 0x04000018
|
||||
#define H2DBG_LAN_STATUS 0x0400001A
|
||||
#define H2DBG_LAN_RESET 0x0400001C
|
||||
#define H2DBG_ETH_REG_BASE 0x04000300
|
||||
|
||||
/***************************************************************************
|
||||
* Ethernet Control Registers
|
||||
* These are for the LAN91C96 on the debug board
|
||||
**************************************************************************/
|
||||
|
||||
/* Bank 0 in IO space */
|
||||
|
||||
#define ETH_TCR (H2DBG_ETH_REG_BASE + 0x00) /* Transmit Control Register */
|
||||
#define ETH_EPH_STATUS (H2DBG_ETH_REG_BASE + 0x02) /* EPH Status Register */
|
||||
#define ETH_RCR (H2DBG_ETH_REG_BASE + 0x04) /* Receive Control Register */
|
||||
#define ETH_COUNTER (H2DBG_ETH_REG_BASE + 0x06) /* Counter Register */
|
||||
#define ETH_MIR (H2DBG_ETH_REG_BASE + 0x08) /* Memory Information Register */
|
||||
#define ETH_MCR (H2DBG_ETH_REG_BASE + 0x0A) /* Memory Configuration Register */
|
||||
|
||||
/* Bank 1 in IO space */
|
||||
|
||||
#define ETH_CONFIG (H2DBG_ETH_REG_BASE + 0x00) /* Configuration Register */
|
||||
#define ETH_BASE (H2DBG_ETH_REG_BASE + 0x02) /* Base Address Register */
|
||||
#define ETH_IA0 (H2DBG_ETH_REG_BASE + 0x04) /* Individual Address Register - 0 */
|
||||
#define ETH_IA1 (H2DBG_ETH_REG_BASE + 0x05) /* Individual Address Register - 1 */
|
||||
#define ETH_IA2 (H2DBG_ETH_REG_BASE + 0x06) /* Individual Address Register - 2 */
|
||||
#define ETH_IA3 (H2DBG_ETH_REG_BASE + 0x07) /* Individual Address Register - 3 */
|
||||
#define ETH_IA4 (H2DBG_ETH_REG_BASE + 0x08) /* Individual Address Register - 4 */
|
||||
#define ETH_IA5 (H2DBG_ETH_REG_BASE + 0x09) /* Individual Address Register - 5 */
|
||||
#define ETH_GEN_PURPOSE (H2DBG_ETH_REG_BASE + 0x0A) /* General Address Registers */
|
||||
#define ETH_CONTROL (H2DBG_ETH_REG_BASE + 0x0B) /* Control Register */
|
||||
|
||||
/* Bank 2 in IO space */
|
||||
|
||||
#define ETH_MMU (H2DBG_ETH_REG_BASE + 0x00) /* MMU Command Register */
|
||||
#define ETH_AUTO_TX_START (H2DBG_ETH_REG_BASE + 0x01) /* Auto Tx Start Register */
|
||||
#define ETH_PNR (H2DBG_ETH_REG_BASE + 0x02) /* Packet Number Register */
|
||||
#define ETH_ARR (H2DBG_ETH_REG_BASE + 0x03) /* Allocation Result Register */
|
||||
#define ETH_FIFO (H2DBG_ETH_REG_BASE + 0x04) /* FIFO Ports Register */
|
||||
#define ETH_POINTER (H2DBG_ETH_REG_BASE + 0x06) /* Pointer Register */
|
||||
#define ETH_DATA_HIGH (H2DBG_ETH_REG_BASE + 0x08) /* Data High Register */
|
||||
#define ETH_DATA_LOW (H2DBG_ETH_REG_BASE + 0x0A) /* Data Low Register */
|
||||
#define ETH_INT_STATS (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Status Register - RO */
|
||||
#define ETH_INT_ACK (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Acknowledge Register -WO */
|
||||
#define ETH_INT_MASK (H2DBG_ETH_REG_BASE + 0x0D) /* Interrupt Mask Register */
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
* A couple of utility inlines to aid debugging using the LED's on the
|
||||
* debug board.
|
||||
*/
|
||||
|
||||
static inline void set_led_state(int state)
|
||||
{
|
||||
static unsigned long hw_led_state = 0;
|
||||
volatile unsigned short *led_address = (volatile unsigned short *)0x04000016;
|
||||
|
||||
hw_led_state = ((unsigned long)state);
|
||||
*((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF);
|
||||
}
|
||||
|
||||
|
||||
static inline void spin_up_leds(void)
|
||||
{
|
||||
volatile int i, j, k;
|
||||
|
||||
for (k = 0; k < 2; k++) {
|
||||
for (i = 0; i < 16; i++) {
|
||||
for (j = 0; j < 5000; j++) {
|
||||
set_led_state(1 << i);
|
||||
}
|
||||
}
|
||||
for (i = 15; i >= 0; i--) {
|
||||
for (j = 0; j < 5000; j++) {
|
||||
set_led_state(1 << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* ! __ASSEMBLY__ */
|
||||
|
||||
#endif /* ! __INCLUDED_H2_P2_DBH_BOARD_H */
|
||||
|
|
@ -1,246 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* OMAP730 hardware map
|
||||
*
|
||||
* Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
|
||||
* Author: MPC-Data Limited
|
||||
* Dave Peverley
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDED_OMAP730_H
|
||||
#define __INCLUDED_OMAP730_H
|
||||
|
||||
#include <asm/sizes.h>
|
||||
|
||||
/***************************************************************************
|
||||
* OMAP730 Configuration Registers
|
||||
**************************************************************************/
|
||||
|
||||
#define PERSEUS2_MPU_DEV_ID ((unsigned int)(0xFFFE1000))
|
||||
#define PERSEUS2_GSM_DEV_ID0 ((unsigned int)(0xFFFE1000))
|
||||
#define PERSEUS2_GDM_DEV_ID1 ((unsigned int)(0xFFFE1002))
|
||||
#define DSP_CONF ((unsigned int)(0xFFFE1004))
|
||||
#define PERSEUS2_MPU_DIE_ID0 ((unsigned int)(0xFFFE1008))
|
||||
#define GSM_ASIC_CONF ((unsigned int)(0xFFFE1008))
|
||||
#define PERSEUS2_MPU_DIE_ID1 ((unsigned int)(0xFFFE100C))
|
||||
#define PERSEUS2_MODE1 ((unsigned int)(0xFFFE1010))
|
||||
#define PERSEUS2_GSM_DIE_ID0 ((unsigned int)(0xFFFE1010))
|
||||
#define PERSEUS2_GSM_DIE_ID1 ((unsigned int)(0xFFFE1012))
|
||||
#define PERSEUS2_MODE2 ((unsigned int)(0xFFFE1014))
|
||||
#define PERSEUS2_GSM_DIE_ID2 ((unsigned int)(0xFFFE1014))
|
||||
#define PERSEUS2_GSM_DIE_ID3 ((unsigned int)(0xFFFE1016))
|
||||
#define PERSEUS2_ANALOG_CELLS_CONF ((unsigned int)(0xFFFE1018))
|
||||
#define SPECCTL ((unsigned int)(0xFFFE101C))
|
||||
#define SPARE1 ((unsigned int)(0xFFFE1020))
|
||||
#define SPARE2 ((unsigned int)(0xFFFE1024))
|
||||
#define GSM_PBG_IRQ ((unsigned int)(0xFFFE1028))
|
||||
#define DMA_REQ_CONF ((unsigned int)(0xFFFE1030))
|
||||
#define PE_CONF_NO_DUAL ((unsigned int)(0xFFFE1060))
|
||||
#define PERSEUS2_IO_CONF0 ((unsigned int)(0xFFFE1070))
|
||||
#define PERSEUS2_IO_CONF1 ((unsigned int)(0xFFFE1074))
|
||||
#define PERSEUS2_IO_CONF2 ((unsigned int)(0xFFFE1078))
|
||||
#define PERSEUS2_IO_CONF3 ((unsigned int)(0xFFFE107C))
|
||||
#define PERSEUS2_IO_CONF4 ((unsigned int)(0xFFFE1080))
|
||||
#define PERSEUS2_IO_CONF5 ((unsigned int)(0xFFFE1084))
|
||||
#define PERSEUS2_IO_CONF6 ((unsigned int)(0xFFFE1088))
|
||||
#define PERSEUS2_IO_CONF7 ((unsigned int)(0xFFFE108C))
|
||||
#define PERSEUS2_IO_CONF8 ((unsigned int)(0xFFFE1090))
|
||||
#define PERSEUS2_IO_CONF9 ((unsigned int)(0xFFFE1094))
|
||||
#define PERSEUS2_IO_CONF10 ((unsigned int)(0xFFFE1098))
|
||||
#define PERSEUS2_IO_CONF11 ((unsigned int)(0xFFFE109C))
|
||||
#define PERSEUS2_IO_CONF12 ((unsigned int)(0xFFFE10A0))
|
||||
#define PERSEUS2_IO_CONF13 ((unsigned int)(0xFFFE10A4))
|
||||
#define PERSEUS_PCC_CONF_REG ((unsigned int)(0xFFFE10B4))
|
||||
#define BIST_STATUS_INTERNAL ((unsigned int)(0xFFFE10B8))
|
||||
#define BIST_CONTROL ((unsigned int)(0xFFFE10C0))
|
||||
#define BOOT_ROM_REG ((unsigned int)(0xFFFE10C4))
|
||||
#define PRODUCTION_ID_REG ((unsigned int)(0xFFFE10C8))
|
||||
#define BIST_SECROM_SIGNATURE1_INTERNAL ((unsigned int)(0xFFFE10D0))
|
||||
#define BIST_SECROM_SIGNATURE2_INTERNAL ((unsigned int)(0xFFFE10D4))
|
||||
#define BIST_CONTROL_2 ((unsigned int)(0xFFFE10D8))
|
||||
#define DEBUG1 ((unsigned int)(0xFFFE10E0))
|
||||
#define DEBUG2 ((unsigned int)(0xFFFE10E4))
|
||||
#define DEBUG_DMA_IRQ ((unsigned int)(0xFFFE10E8))
|
||||
|
||||
/***************************************************************************
|
||||
* OMAP730 EMIFS Registers (TRM 2.5.7)
|
||||
**************************************************************************/
|
||||
|
||||
#define TCMIF_BASE 0xFFFECC00
|
||||
|
||||
#define EMIFS_LRUREG (TCMIF_BASE + 0x04)
|
||||
#define EMIFS_CONFIG (TCMIF_BASE + 0x0C)
|
||||
#define FLASH_CFG_0 (TCMIF_BASE + 0x10)
|
||||
#define FLASH_CFG_1 (TCMIF_BASE + 0x14)
|
||||
#define FLASH_CFG_2 (TCMIF_BASE + 0x18)
|
||||
#define FLASH_CFG_3 (TCMIF_BASE + 0x1C)
|
||||
#define FL_CFG_DYN_WAIT (TCMIF_BASE + 0x40)
|
||||
#define EMIFS_TIMEOUT1_REG (TCMIF_BASE + 0x28)
|
||||
#define EMIFS_TIMEOUT2_REG (TCMIF_BASE + 0x2C)
|
||||
#define EMIFS_TIMEOUT3_REG (TCMIF_BASE + 0x30)
|
||||
#define EMIFS_ABORT_ADDR (TCMIF_BASE + 0x44)
|
||||
#define EMIFS_ABORT_TYPE (TCMIF_BASE + 0x48)
|
||||
#define EMIFS_ABORT_TOUT (TCMIF_BASE + 0x4C)
|
||||
#define FLASH_ACFG_0_1 (TCMIF_BASE + 0x50)
|
||||
#define FLASH_ACFG_1_1 (TCMIF_BASE + 0x54)
|
||||
#define FLASH_ACFG_2_1 (TCMIF_BASE + 0x58)
|
||||
#define FLASH_ACFG_3_1 (TCMIF_BASE + 0x5C)
|
||||
|
||||
/***************************************************************************
|
||||
* OMAP730 Interrupt handlers
|
||||
**************************************************************************/
|
||||
|
||||
#define OMAP_IH1_BASE 0xFFFECB00 /* MPU Level 1 IRQ handler */
|
||||
#define OMAP_IH2_BASE 0xfffe0000
|
||||
|
||||
/***************************************************************************
|
||||
* OMAP730 Timers
|
||||
*
|
||||
* There are three general purpose OS timers in the 730 that can be
|
||||
* configured in autoreload or one-shot modes.
|
||||
**************************************************************************/
|
||||
|
||||
#define OMAP730_32kHz_TIMER_BASE 0xFFFB9000
|
||||
|
||||
/* 32k Timer Registers */
|
||||
#define TIMER32k_CR 0x08
|
||||
#define TIMER32k_TVR 0x00
|
||||
#define TIMER32k_TCR 0x04
|
||||
|
||||
/* 32k Timer Control Register definition */
|
||||
#define TIMER32k_TSS (1<<0)
|
||||
#define TIMER32k_TRB (1<<1)
|
||||
#define TIMER32k_INT (1<<2)
|
||||
#define TIMER32k_ARL (1<<3)
|
||||
|
||||
/* MPU Timer base addresses */
|
||||
#define OMAP730_MPUTIMER_BASE 0xfffec500
|
||||
#define OMAP730_MPUTIMER_OFF 0x00000100
|
||||
|
||||
#define OMAP730_TIMER1_BASE 0xFFFEC500
|
||||
#define OMAP730_TIMER2_BASE 0xFFFEC600
|
||||
#define OMAP730_TIMER3_BASE 0xFFFEC700
|
||||
|
||||
/* MPU Timer Register offsets */
|
||||
#define CNTL_TIMER 0x00 /* MPU_CNTL_TIMER */
|
||||
#define LOAD_TIM 0x04 /* MPU_LOAD_TIMER */
|
||||
#define READ_TIM 0x08 /* MPU_READ_TIMER */
|
||||
|
||||
/* MPU_CNTL_TIMER register bits */
|
||||
#define MPUTIM_FREE (1<<6)
|
||||
#define MPUTIM_CLOCK_ENABLE (1<<5)
|
||||
#define MPUTIM_PTV_MASK (0x7<<MPUTIM_PTV_BIT)
|
||||
#define MPUTIM_PTV_BIT 2
|
||||
#define MPUTIM_AR (1<<1)
|
||||
#define MPUTIM_ST (1<<0)
|
||||
|
||||
/***************************************************************************
|
||||
* OMAP730 GPIO
|
||||
*
|
||||
* The GPIO control is split over 6 register bases in the OMAP730 to allow
|
||||
* access to all the (6 x 32) GPIO pins!
|
||||
**************************************************************************/
|
||||
|
||||
#define OMAP730_GPIO_BASE_1 0xFFFBC000
|
||||
#define OMAP730_GPIO_BASE_2 0xFFFBC800
|
||||
#define OMAP730_GPIO_BASE_3 0xFFFBD000
|
||||
#define OMAP730_GPIO_BASE_4 0xFFFBD800
|
||||
#define OMAP730_GPIO_BASE_5 0xFFFBE000
|
||||
#define OMAP730_GPIO_BASE_6 0xFFFBE800
|
||||
|
||||
#define GPIO_DATA_INPUT 0x00
|
||||
#define GPIO_DATA_OUTPUT 0x04
|
||||
#define GPIO_DIRECTION_CONTROL 0x08
|
||||
#define GPIO_INTERRUPT_CONTROL 0x0C
|
||||
#define GPIO_INTERRUPT_MASK 0x10
|
||||
#define GPIO_INTERRUPT_STATUS 0x14
|
||||
|
||||
#define GPIO_DATA_INPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT))
|
||||
#define GPIO_DATA_OUTPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT))
|
||||
#define GPIO_DIRECTION_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL))
|
||||
#define GPIO_INTERRUPT_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL))
|
||||
#define GPIO_INTERRUPT_MASK_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK))
|
||||
#define GPIO_INTERRUPT_STATUS_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS))
|
||||
|
||||
#define GPIO_DATA_INPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT))
|
||||
#define GPIO_DATA_OUTPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT))
|
||||
#define GPIO_DIRECTION_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL))
|
||||
#define GPIO_INTERRUPT_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL))
|
||||
#define GPIO_INTERRUPT_MASK_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK))
|
||||
#define GPIO_INTERRUPT_STATUS_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS))
|
||||
|
||||
#define GPIO_DATA_INPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT))
|
||||
#define GPIO_DATA_OUTPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT))
|
||||
#define GPIO_DIRECTION_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL))
|
||||
#define GPIO_INTERRUPT_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL))
|
||||
#define GPIO_INTERRUPT_MASK_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK))
|
||||
#define GPIO_INTERRUPT_STATUS_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS))
|
||||
|
||||
#define GPIO_DATA_INPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT))
|
||||
#define GPIO_DATA_OUTPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT))
|
||||
#define GPIO_DIRECTION_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL))
|
||||
#define GPIO_INTERRUPT_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL))
|
||||
#define GPIO_INTERRUPT_MASK_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK))
|
||||
#define GPIO_INTERRUPT_STATUS_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS))
|
||||
|
||||
#define GPIO_DATA_INPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT))
|
||||
#define GPIO_DATA_OUTPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT))
|
||||
#define GPIO_DIRECTION_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL))
|
||||
#define GPIO_INTERRUPT_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL))
|
||||
#define GPIO_INTERRUPT_MASK_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK))
|
||||
#define GPIO_INTERRUPT_STATUS_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS))
|
||||
|
||||
#define GPIO_DATA_INPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT))
|
||||
#define GPIO_DATA_OUTPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT))
|
||||
#define GPIO_DIRECTION_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL))
|
||||
#define GPIO_INTERRUPT_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL))
|
||||
#define GPIO_INTERRUPT_MASK_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
|
||||
#define GPIO_INTERRUPT_STATUS_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
|
||||
|
||||
/***************************************************************************
|
||||
* OMAP730 Watchdog timers
|
||||
**************************************************************************/
|
||||
|
||||
#define WDTIM_BASE 0xFFFEC800
|
||||
#define WDTIM_CONTROL (WDTIM_BASE + 0x00) /* MPU_CNTL_TIMER */
|
||||
#define WDTIM_LOAD (WDTIM_BASE + 0x04) /* MPU_LOAD_TIMER */
|
||||
#define WDTIM_READ (WDTIM_BASE + 0x04) /* MPU_READ_TIMER */
|
||||
#define WDTIM_MODE (WDTIM_BASE + 0x08) /* MPU_TIMER_MODE */
|
||||
|
||||
/***************************************************************************
|
||||
* OMAP730 Interrupt Registers
|
||||
**************************************************************************/
|
||||
|
||||
/* Interrupt Register offsets */
|
||||
|
||||
#define IRQ_ITR 0x00
|
||||
#define IRQ_MIR 0x04
|
||||
#define IRQ_SIR_IRQ 0x10
|
||||
#define IRQ_SIR_FIQ 0x14
|
||||
#define IRQ_CONTROL_REG 0x18
|
||||
#define IRQ_ILR0 0x1C /* ILRx == ILR0 + (0x4 * x) */
|
||||
#define IRQ_SIR 0x9C /* a.k.a.IRQ_ISR */
|
||||
#define IRQ_GMIR 0xA0
|
||||
|
||||
#define REG_IHL1_MIR (OMAP_IH1_BASE + IRQ_MIR)
|
||||
#define REG_IHL2_MIR (OMAP_IH2_BASE + IRQ_MIR)
|
||||
|
||||
/***************************************************************************
|
||||
* OMAP730 Intersystem Communication Register (TRM 4.5)
|
||||
**************************************************************************/
|
||||
|
||||
#define ICR_BASE 0xFFFBB800
|
||||
|
||||
#define M_ICR (ICR_BASE + 0x00)
|
||||
#define G_ICR (ICR_BASE + 0x02)
|
||||
#define M_CTL (ICR_BASE + 0x04)
|
||||
#define G_CTL (ICR_BASE + 0x06)
|
||||
#define PM_BA (ICR_BASE + 0x0A)
|
||||
#define DM_BA (ICR_BASE + 0x0C)
|
||||
#define RM_BA (ICR_BASE + 0x0E)
|
||||
#define SSPI_TAS (ICR_BASE + 0x12)
|
||||
|
||||
#endif /* ! __INCLUDED_OMAP730_H */
|
||||
|
|
@ -1,173 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2004
|
||||
* MPC Data Limited (http://www.mpc-data.co.uk)
|
||||
* Dave Peverley <dpeverley at mpc-data.co.uk>
|
||||
*
|
||||
* Configuation settings for the TI OMAP Perseus 2 board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
|
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */
|
||||
#define CONFIG_OMAP730 1 /* which is in a 730 */
|
||||
#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
|
||||
|
||||
/*
|
||||
* Input clock of PLL
|
||||
* The OMAP730 Perseus 2 has 13MHz input clock
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 13000000
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
#define CONFIG_LAN91C96
|
||||
#define CONFIG_LAN91C96_BASE 0x04000300
|
||||
#define CONFIG_LAN91C96_EXT_PHY
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (1)
|
||||
#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
|
||||
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
|
||||
* on perseus */
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
|
||||
|
||||
#include <configs/omap730.h>
|
||||
#include <configs/h2_p2_dbg_board.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
|
||||
|
||||
#define CONFIG_LOADADDR 0x10000000
|
||||
|
||||
#define CONFIG_ETHADDR
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 192.168.0.23
|
||||
#define CONFIG_SERVERIP 192.150.0.100
|
||||
#define CONFIG_BOOTFILE "uImage" /* File to load */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
|
||||
|
||||
/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
|
||||
* the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
|
||||
* local divisor.
|
||||
*/
|
||||
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
|
||||
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
|
||||
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
|
||||
|
||||
#if defined(CONFIG_CS0_BOOT)
|
||||
#define PHYS_FLASH_1 0x0C000000
|
||||
#elif defined(CONFIG_CS3_BOOT)
|
||||
#define PHYS_FLASH_1 0x00000000
|
||||
#else
|
||||
#error Unknown Boot Chip-Select number
|
||||
#endif
|
||||
|
||||
#define PHYS_SRAM 0x20000000
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
|
||||
/* addr of environment */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
|
||||
|
||||
#endif /* ! __CONFIG_H */
|
||||
Loading…
Add table
Reference in a new issue