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Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xx
This commit is contained in:
commit
79d14faf54
6 changed files with 40 additions and 5 deletions
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@ -99,7 +99,10 @@ int checkboard(void)
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
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volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
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puts("Board: MPC8610HPCD\n");
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printf ("Board: MPC8610HPCD, System ID: 0x%02lx, "
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"System Version: 0x%02lx, FPGA Version: 0x%02lx\n",
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in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
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in8(PIXIS_BASE + PIXIS_PVER));
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mcm->abcr |= 0x00010000; /* 0 */
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mcm->abcr |= 0x00010000; /* 0 */
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mcm->hpmr3 = 0x80000008; /* 4c */
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mcm->hpmr3 = 0x80000008; /* 4c */
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@ -47,8 +47,10 @@ int board_early_init_f(void)
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int checkboard(void)
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int checkboard(void)
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{
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{
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puts("Board: MPC8641HPCN\n");
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printf ("Board: MPC8641HPCN, System ID: 0x%02lx, "
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"System Version: 0x%02lx, FPGA Version: 0x%02lx\n",
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in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
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in8(PIXIS_BASE + PIXIS_PVER));
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return 0;
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return 0;
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}
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}
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@ -214,6 +214,20 @@ get_tbclk(void)
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void
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void
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watchdog_reset(void)
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watchdog_reset(void)
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{
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{
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#if defined(CONFIG_MPC8610)
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/*
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* This actually feed the hard enabled watchdog.
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*/
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_wdt_t *wdt = &immap->im_wdt;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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u32 tmp = gur->pordevsr;
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if (tmp & 0x4000) {
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wdt->swsrr = 0x556c;
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wdt->swsrr = 0xaa39;
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}
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#endif
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}
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}
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#endif /* CONFIG_WATCHDOG */
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#endif /* CONFIG_WATCHDOG */
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@ -36,6 +36,7 @@
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#include <command.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/processor.h>
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#include <ppc_asm.tmpl>
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#include <ppc_asm.tmpl>
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#include <watchdog.h>
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unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */
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unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */
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unsigned long timestamp;
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unsigned long timestamp;
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@ -1304,9 +1304,21 @@ typedef struct ccsr_gur {
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uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/
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uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/
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int res14[6];
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int res14[6];
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uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
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uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
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char res15[61656];
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char res15[216];
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} ccsr_gur_t;
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} ccsr_gur_t;
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/*
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* Watchdog register block(0xe_4000-0xe_4fff)
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*/
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typedef struct ccsr_wdt {
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uint res0;
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uint swcrr; /* System watchdog control register */
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uint swcnr; /* System watchdog count register */
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char res1[2];
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ushort swsrr; /* System watchdog service register */
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char res2[4080];
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} ccsr_wdt_t;
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typedef struct immap {
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typedef struct immap {
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ccsr_local_mcm_t im_local_mcm;
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ccsr_local_mcm_t im_local_mcm;
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ccsr_ddr_t im_ddr1;
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ccsr_ddr_t im_ddr1;
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@ -1330,6 +1342,8 @@ typedef struct immap {
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char res5[389120];
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char res5[389120];
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ccsr_rio_t im_rio;
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ccsr_rio_t im_rio;
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ccsr_gur_t im_gur;
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ccsr_gur_t im_gur;
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char res6[12288];
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ccsr_wdt_t im_wdt;
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} immap_t;
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} immap_t;
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extern immap_t *immr;
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extern immap_t *immr;
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@ -485,7 +485,8 @@
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#endif
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_WATCHDOG /* watchdog enabled */
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#define CFG_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
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/*DIU Configuration*/
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/*DIU Configuration*/
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#define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/
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#define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/
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