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Fix LOWBOOT configuration for MPC5200 with DDR memory

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This commit is contained in:
wdenk 2004-03-11 22:46:36 +00:00
parent f8d813e34f
commit 79d696fc55
5 changed files with 119 additions and 118 deletions
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2
CHANGELOG
View file

@ -2,6 +2,8 @@
Changes for U-Boot 1.0.2:
======================================================================
* Fix LOWBOOT configuration for MPC5200 with DDR memory
* Fix SDRAM timings for LITE5200 / IceCube board
* Handle Auti-MDIX / connection status for INCA-IP

3
Makefile
View file

@ -207,9 +207,10 @@ PATI_config:unconfig
MPC5200LITE_config \
MPC5200LITE_LOWBOOT_config \
MPC5200LITE_LOWBOOT08_config \
icecube_5200_DDR_LOWBOOT_config \
icecube_5200_DDR_config \
IceCube_5200_DDR_config \
icecube_5200_DDR_LOWBOOT_config \
icecube_5200_DDR_LOWBOOT08_config \
icecube_5200_config \
IceCube_5200_config \
IceCube_5100_config: unconfig

33
cpu/mpc5xxx/start.S
View file

@ -108,18 +108,19 @@ boot_warm:
#error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
#endif /* CFG_RAMBOOT */
lis r4, CFG_DEFAULT_MBAR@h
lis r3, 0x0000FF00@h
ori r3, r3, 0x0000FF00@l
stw r3, 0x4(r4)
lis r3, 0x0000FFFF@h
ori r3, r3, 0x0000FFFF@l
stw r3, 0x8(r4)
lis r3, START_REG(CFG_BOOTCS_START)@h
ori r3, r3, START_REG(CFG_BOOTCS_START)@l
stw r3, 0x4(r4) /* CS0 start */
lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
stw r3, 0x8(r4) /* CS0 stop */
lis r3, 0x00047800@h
ori r3, r3, 0x00047800@l
stw r3, 0x300(r4)
stw r3, 0x300(r4) /* set timing, CS0/boot conf reg */
lis r3, 0x02010000@h
ori r3, r3, 0x02010000@l
stw r3, 0x54(r4)
stw r3, 0x54(r4) /* CS0 and Boot enable, IPBI ctrl reg */
lis r3, lowboot_reentry@h
ori r3, r3, lowboot_reentry@l
@ -127,18 +128,18 @@ boot_warm:
blr /* jump to flash based address */
lowboot_reentry:
lis r3, 0x0000FF00@h
ori r3, r3, 0x0000FF00@l
stw r3, 0x4c(r4)
lis r3, 0x0000FFFF@h
ori r3, r3, 0x0000FFFF@l
stw r3, 0x50(r4)
lis r3, START_REG(CFG_BOOTCS_START)@h
ori r3, r3, START_REG(CFG_BOOTCS_START)@l
stw r3, 0x4c(r4) /* Boot start */
lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
stw r3, 0x50(r4) /* Boot stop */
lis r3, 0x00047800@h
ori r3, r3, 0x00047800@l
stw r3, 0x300(r4)
stw r3, 0x300(r4) /* set timing, CS0/boot conf reg */
lis r3, 0x02000001@h
ori r3, r3, 0x02000001@l
stw r3, 0x54(r4)
stw r3, 0x54(r4) /* Boot enable, CS0 disable, wait state enable */
#endif /* CFG_LOWBOOT */
#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)

12
cpu/mpc5xxx/usb_ohci.c
View file

@ -488,7 +488,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
if (ohci->ed_controltail == NULL) {
writel (ed, &ohci->regs->ed_controlhead);
} else {
ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 (ed);
ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
}
ed->ed_prev = ohci->ed_controltail;
if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
@ -504,7 +504,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
if (ohci->ed_bulktail == NULL) {
writel (ed, &ohci->regs->ed_bulkhead);
} else {
ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 (ed);
ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
}
ed->ed_prev = ohci->ed_bulktail;
if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
@ -598,7 +598,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
/* dummy td; end of td list for ed */
td = td_alloc (usb_dev);
ed->hwTailP = ohci_cpu_to_le32 (td);
ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
ed->hwHeadP = ed->hwTailP;
ed->state = ED_UNLINK;
ed->type = usb_pipetype (pipe);
@ -656,12 +656,12 @@ static void td_fill (ohci_t *ohci, unsigned int info,
data = 0;
td->hwINFO = ohci_cpu_to_le32 (info);
td->hwCBP = ohci_cpu_to_le32 (data);
td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
if (data)
td->hwBE = ohci_cpu_to_le32 (data + len - 1);
td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
else
td->hwBE = 0;
td->hwNextTD = ohci_cpu_to_le32 (td_pt);
td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
td->hwPSW [0] = ohci_cpu_to_le16 (((__u32)data & 0x0FFF) | 0xE000);
/* append to queue */

11
drivers/inca-ip_sw.c
View file

@ -80,7 +80,7 @@
#define WAIT_SIGNAL_RETRIES 100
#define WAIT_LINK_RETRIES 100
#define LINK_RETRY_DELAY 300 /* ms */
#define LINK_RETRY_DELAY 2000 /* ms */
/********************************************************************/
typedef struct
@ -152,8 +152,7 @@ static int initialized = 0;
static int inca_switch_init(struct eth_device *dev, bd_t * bis);
static int inca_switch_send(struct eth_device *dev, volatile void *packet,
int length);
static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length);
static int inca_switch_recv(struct eth_device *dev);
static void inca_switch_halt(struct eth_device *dev);
static void inca_init_switch_chip(void);
@ -296,8 +295,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
/* Writing to the COMMAND REG.
*/
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0,
INCA_IP_DMA_DMA_RXCCR0_INIT);
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT);
/* Initialize TxDMA.
*/
@ -450,8 +448,7 @@ static int inca_switch_recv(struct eth_device *dev)
#if 0
printf("Received %d bytes\n", length);
#endif
NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]),
length - 4);
NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), length - 4);
} else {
#if 1
printf("Zero length!!!\n");