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board: freescale: ls1012ardb: enable network support on ls1012ardb
This patch enables ethernet support for ls1012ardb. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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parent
a141f33af5
commit
7ab16479e1
5 changed files with 140 additions and 4 deletions
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@ -12,6 +12,35 @@ config SYS_SOC
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config SYS_CONFIG_NAME
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default "ls1012ardb"
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if FSL_PFE
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select PHYLIB
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imply PHY_REALTEK
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config SYS_LS_PFE_FW_ADDR
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hex "Flash address of PFE firmware"
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default 0x40a00000
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config DDR_PFE_PHYS_BASEADDR
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hex "PFE DDR physical base address"
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default 0x03800000
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config DDR_PFE_BASEADDR
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hex "PFE DDR base address"
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default 0x83800000
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config PFE_EMAC1_PHY_ADDR
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hex "PFE DDR base address"
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default 0x2
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config PFE_EMAC2_PHY_ADDR
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hex "PFE DDR base address"
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default 0x1
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endif
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source "board/freescale/common/Kconfig"
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endif
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@ -5,3 +5,4 @@
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#
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obj-y += ls1012ardb.o
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obj-$(CONFIG_FSL_PFE) += eth.o
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106
board/freescale/ls1012ardb/eth.c
Normal file
106
board/freescale/ls1012ardb/eth.c
Normal file
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@ -0,0 +1,106 @@
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier:GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <netdev.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <asm/types.h>
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#include <fsl_dtsec.h>
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#include <asm/arch/soc.h>
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#include <asm/arch-fsl-layerscape/config.h>
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#include <asm/arch-fsl-layerscape/immap_lsch2.h>
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#include <asm/arch/fsl_serdes.h>
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#include <net/pfe_eth/pfe_eth.h>
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#include <dm/platform_data/pfe_dm_eth.h>
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#include <i2c.h>
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#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
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static inline void ls1012ardb_reset_phy(void)
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{
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/* Through reset IO expander reset both RGMII and SGMII PHYs */
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i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
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i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
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mdelay(10);
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i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
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mdelay(10);
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i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
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mdelay(50);
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}
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int pfe_eth_board_init(struct udevice *dev)
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{
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static int init_done;
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struct mii_dev *bus;
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struct pfe_mdio_info mac_mdio_info;
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struct pfe_eth_dev *priv = dev_get_priv(dev);
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if (!init_done) {
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ls1012ardb_reset_phy();
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mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
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mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
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bus = pfe_mdio_init(&mac_mdio_info);
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if (!bus) {
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printf("Failed to register mdio\n");
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return -1;
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}
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init_done = 1;
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}
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pfe_set_mdio(priv->gemac_port,
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miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
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if (!priv->gemac_port) {
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/* MAC1 */
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pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
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PHY_INTERFACE_MODE_SGMII);
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} else {
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/* MAC2 */
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pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
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PHY_INTERFACE_MODE_RGMII_TXID);
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}
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return 0;
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}
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static struct pfe_eth_pdata pfe_pdata0 = {
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.pfe_eth_pdata_mac = {
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.iobase = (phys_addr_t)EMAC1_BASE_ADDR,
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.phy_interface = 0,
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},
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.pfe_ddr_addr = {
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.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
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.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
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},
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};
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static struct pfe_eth_pdata pfe_pdata1 = {
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.pfe_eth_pdata_mac = {
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.iobase = (phys_addr_t)EMAC2_BASE_ADDR,
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.phy_interface = 1,
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},
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.pfe_ddr_addr = {
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.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
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.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
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},
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};
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U_BOOT_DEVICE(ls1012a_pfe0) = {
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.name = "pfe_eth",
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.platdata = &pfe_pdata0,
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};
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U_BOOT_DEVICE(ls1012a_pfe1) = {
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.name = "pfe_eth",
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.platdata = &pfe_pdata1,
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};
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@ -114,10 +114,6 @@ int dram_init(void)
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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int board_early_init_f(void)
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{
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@ -25,6 +25,7 @@
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*/
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#define I2C_MUX_IO_ADDR 0x24
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#define I2C_MUX_IO2_ADDR 0x25
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#define I2C_MUX_IO_0 0
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#define I2C_MUX_IO_1 1
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#define SW_BOOT_MASK 0x03
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@ -39,6 +40,9 @@
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#define SW_REV_C2 0xD8
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#define SW_REV_D 0xD0
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#define SW_REV_E 0xC8
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#define __PHY_MASK 0xF9
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#define __PHY_ETH2_MASK 0xFB
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#define __PHY_ETH1_MASK 0xFD
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/* MMC */
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#ifdef CONFIG_MMC
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