mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-17 20:51:39 +00:00
Merge git://git.denx.de/u-boot-mmc
This commit is contained in:
commit
7b1cfec317
18 changed files with 1125 additions and 111 deletions
|
@ -25,6 +25,11 @@
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|||
pinctrl-1 = <&mmc1_pins_hs>;
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||||
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vmmc-supply = <&ldo1_reg>;
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/delete-property/ sd-uhs-sdr104;
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/delete-property/ sd-uhs-sdr50;
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/delete-property/ sd-uhs-ddr50;
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/delete-property/ sd-uhs-sdr25;
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/delete-property/ sd-uhs-sdr12;
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};
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&mmc2 {
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@ -32,6 +37,7 @@
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pinctrl-0 = <&mmc2_pins_default>;
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pinctrl-1 = <&mmc2_pins_hs>;
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pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
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/delete-property/ mmc-hs200-1_8v;
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};
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/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
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|
|
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@ -413,6 +413,8 @@
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bus-width = <8>;
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ti,non-removable;
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max-frequency = <96000000>;
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no-1-8-v;
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/delete-property/ mmc-hs200-1_8v;
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};
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&dcan1 {
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|
|
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@ -1056,7 +1056,7 @@
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};
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mmc1: mmc@4809c000 {
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compatible = "ti,omap4-hsmmc";
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compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
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reg = <0x4809c000 0x400>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mmc1";
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@ -1067,10 +1067,15 @@
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status = "disabled";
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pbias-supply = <&pbias_mmc_reg>;
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max-frequency = <192000000>;
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sd-uhs-sdr104;
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sd-uhs-sdr50;
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sd-uhs-ddr50;
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sd-uhs-sdr25;
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sd-uhs-sdr12;
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};
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mmc2: mmc@480b4000 {
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compatible = "ti,omap4-hsmmc";
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compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
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reg = <0x480b4000 0x400>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mmc2";
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@ -1079,10 +1084,14 @@
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dma-names = "tx", "rx";
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status = "disabled";
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max-frequency = <192000000>;
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sd-uhs-sdr25;
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sd-uhs-sdr12;
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mmc-hs200-1_8v;
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mmc-ddr-1_8v;
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};
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mmc3: mmc@480ad000 {
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compatible = "ti,omap4-hsmmc";
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compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
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reg = <0x480ad000 0x400>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mmc3";
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@ -1092,10 +1101,13 @@
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status = "disabled";
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/* Errata i887 limits max-frequency of MMC3 to 64 MHz */
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max-frequency = <64000000>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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};
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mmc4: mmc@480d1000 {
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compatible = "ti,omap4-hsmmc";
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compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
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reg = <0x480d1000 0x400>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mmc4";
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@ -1104,6 +1116,8 @@
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dma-names = "tx", "rx";
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status = "disabled";
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max-frequency = <192000000>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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};
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mmu0_dsp1: mmu@40d01000 {
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|
|
|
@ -135,7 +135,7 @@
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|||
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/* CM_L3INIT_HSMMCn_CLKCTRL */
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#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
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#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
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#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25)
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/* CM_L3INIT_SATA_CLKCTRL */
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#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
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|
|
|
@ -83,6 +83,9 @@
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void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
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struct iodelay_cfg_entry const *iodelay,
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int niodelays);
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void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
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struct iodelay_cfg_entry const *iodelay,
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int niodelays);
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int __recalibrate_iodelay_start(void);
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void __recalibrate_iodelay_end(int ret);
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|
|
|
@ -35,6 +35,12 @@ struct pad_conf_entry {
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u32 val;
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};
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struct mmc_platform_fixups {
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const char *hw_rev;
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u32 unsupported_caps;
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u32 max_freq;
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};
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|
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struct omap_sysinfo {
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char *board_string;
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};
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|
@ -71,6 +77,7 @@ void force_emif_self_refresh(void);
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void get_ioregs(const struct ctrl_ioregs **regs);
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void srcomp_enable(void);
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void setup_warmreset_time(void);
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const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr);
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static inline u32 div_round_up(u32 num, u32 den)
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{
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|
|
|
@ -39,7 +39,9 @@ struct hsmmc {
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unsigned int sysstatus; /* 0x14 */
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unsigned char res2[0x14];
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unsigned int con; /* 0x2C */
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unsigned char res3[0xD4];
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unsigned int pwcnt; /* 0x30 */
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unsigned int dll; /* 0x34 */
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unsigned char res3[0xcc];
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unsigned int blk; /* 0x104 */
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unsigned int arg; /* 0x108 */
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unsigned int cmd; /* 0x10C */
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|
@ -53,9 +55,11 @@ struct hsmmc {
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unsigned int sysctl; /* 0x12C */
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unsigned int stat; /* 0x130 */
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unsigned int ie; /* 0x134 */
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unsigned char res4[0x8];
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unsigned char res4[0x4];
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unsigned int ac12; /* 0x13C */
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unsigned int capa; /* 0x140 */
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unsigned char res5[0x10];
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unsigned int capa2; /* 0x144 */
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unsigned char res5[0xc];
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unsigned int admaes; /* 0x154 */
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unsigned int admasal; /* 0x158 */
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};
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@ -65,6 +69,8 @@ struct omap_hsmmc_plat {
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struct hsmmc *base_addr;
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struct mmc mmc;
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bool cd_inverted;
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u32 controller_flags;
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const char *hw_rev;
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};
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|
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/*
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||||
|
@ -87,6 +93,7 @@ struct omap_hsmmc_plat {
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#define WPP_ACTIVEHIGH (0x0 << 8)
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#define RESERVED_MASK (0x3 << 9)
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#define CTPL_MMC_SD (0x0 << 11)
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#define DDR (0x1 << 19)
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#define DMA_MASTER (0x1 << 20)
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#define BLEN_512BYTESLEN (0x200 << 0)
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#define NBLK_STPCNT (0x0 << 16)
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|
@ -124,8 +131,10 @@ struct omap_hsmmc_plat {
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|||
#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
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#define SDBP_PWROFF (0x0 << 8)
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#define SDBP_PWRON (0x1 << 8)
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#define SDVS_MASK (0x7 << 9)
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#define SDVS_1V8 (0x5 << 9)
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#define SDVS_3V0 (0x6 << 9)
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#define SDVS_3V3 (0x7 << 9)
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#define DMA_SELECT (0x2 << 3)
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#define ICE_MASK (0x1 << 0)
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#define ICE_STOP (0x0 << 0)
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@ -159,8 +168,20 @@ struct omap_hsmmc_plat {
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#define IE_CERR (0x01 << 28)
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#define IE_BADA (0x01 << 29)
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#define VS30_3V0SUP (1 << 25)
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#define VS18_1V8SUP (1 << 26)
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#define VS33_3V3SUP BIT(24)
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#define VS30_3V0SUP BIT(25)
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#define VS18_1V8SUP BIT(26)
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|
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#define AC12_ET BIT(22)
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#define AC12_V1V8_SIGEN BIT(19)
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#define AC12_SCLK_SEL BIT(23)
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#define AC12_UHSMC_MASK (7 << 16)
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#define AC12_UHSMC_DDR50 (4 << 16)
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#define AC12_UHSMC_SDR104 (3 << 16)
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#define AC12_UHSMC_SDR50 (2 << 16)
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#define AC12_UHSMC_SDR25 (1 << 16)
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#define AC12_UHSMC_SDR12 (0 << 16)
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#define AC12_UHSMC_RES (0x7 << 16)
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/* Driver definitions */
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#define MMCSD_SECTOR_SIZE 512
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|
@ -172,15 +193,43 @@ struct omap_hsmmc_plat {
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#define CLK_400KHZ 1
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#define CLK_MISC 2
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|
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#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
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|
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#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
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#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
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|
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/* Clock Configurations and Macros */
|
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#ifdef CONFIG_OMAP54XX
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#define MMC_CLOCK_REFERENCE 192 /* MHz */
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#else
|
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#define MMC_CLOCK_REFERENCE 96 /* MHz */
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#endif
|
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|
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/* DLL */
|
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#define DLL_SWT BIT(20)
|
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#define DLL_FORCE_SR_C_SHIFT 13
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#define DLL_FORCE_SR_C_MASK 0x7f
|
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#define DLL_FORCE_VALUE BIT(12)
|
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#define DLL_CALIB BIT(1)
|
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|
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#define MAX_PHASE_DELAY 0x7c
|
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|
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/* CAPA2 */
|
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#define CAPA2_TSDR50 BIT(13)
|
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|
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#define mmc_reg_out(addr, mask, val)\
|
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writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
|
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|
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#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\
|
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IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\
|
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IE_BRR | IE_BWR | IE_TC | IE_CC)
|
||||
|
||||
#define CON_CLKEXTFREE BIT(16)
|
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#define CON_PADEN BIT(15)
|
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#define PSTATE_CLEV BIT(24)
|
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#define PSTATE_DLEV (0xF << 20)
|
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#define PSTATE_DLEV_DAT0 (0x1 << 20)
|
||||
|
||||
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
|
||||
int wp_gpio);
|
||||
|
||||
|
|
|
@ -272,3 +272,33 @@ err:
|
|||
__recalibrate_iodelay_end(ret);
|
||||
|
||||
}
|
||||
|
||||
void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
|
||||
struct iodelay_cfg_entry const *iodelay,
|
||||
int niodelays)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
/* unlock IODELAY CONFIG registers */
|
||||
writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
|
||||
CFG_REG_8_OFFSET);
|
||||
|
||||
ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
|
||||
|
||||
/* Configure Mux settings */
|
||||
do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
|
||||
|
||||
/* Configure Manual IO timing modes */
|
||||
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
err:
|
||||
/* lock IODELAY CONFIG registers */
|
||||
writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
|
||||
CFG_REG_8_OFFSET);
|
||||
}
|
||||
|
|
|
@ -438,17 +438,17 @@ void enable_basic_clocks(void)
|
|||
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
|
||||
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
|
||||
|
||||
/* Enable 96 MHz clock for MMC1 & MMC2 */
|
||||
/* Enable 192 MHz clock for MMC1 & MMC2 */
|
||||
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
|
||||
HSMMC_CLKCTRL_CLKSEL_MASK);
|
||||
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
|
||||
HSMMC_CLKCTRL_CLKSEL_MASK);
|
||||
|
||||
/* Set the correct clock dividers for mmc */
|
||||
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
|
||||
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
|
||||
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
|
||||
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
|
||||
clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
|
||||
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
|
||||
clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
|
||||
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
|
||||
|
||||
/* Select 32KHz clock as the source of GPTIMER1 */
|
||||
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
|
||||
|
|
|
@ -30,6 +30,7 @@
|
|||
#include <dwc3-uboot.h>
|
||||
#include <dwc3-omap-uboot.h>
|
||||
#include <ti-usb-phy-uboot.h>
|
||||
#include <mmc.h>
|
||||
|
||||
#include "../common/board_detect.h"
|
||||
#include "mux_data.h"
|
||||
|
@ -815,6 +816,35 @@ int board_mmc_init(bd_t *bis)
|
|||
omap_mmc_init(1, 0, 0, -1, -1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
|
||||
.hw_rev = "rev11",
|
||||
.unsupported_caps = MMC_CAP(MMC_HS_200) |
|
||||
MMC_CAP(UHS_SDR104),
|
||||
.max_freq = 96000000,
|
||||
};
|
||||
|
||||
static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
|
||||
.hw_rev = "rev11",
|
||||
.unsupported_caps = MMC_CAP(MMC_HS_200) |
|
||||
MMC_CAP(UHS_SDR104) |
|
||||
MMC_CAP(UHS_SDR50),
|
||||
.max_freq = 48000000,
|
||||
};
|
||||
|
||||
const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
|
||||
{
|
||||
switch (omap_revision()) {
|
||||
case DRA752_ES1_0:
|
||||
case DRA752_ES1_1:
|
||||
if (addr == OMAP_HSMMC1_BASE)
|
||||
return &am57x_es1_1_mmc1_fixups;
|
||||
else
|
||||
return &am57x_es1_1_mmc23_fixups;
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
|
||||
|
|
|
@ -866,6 +866,35 @@ void board_mmc_poweron_ldo(uint voltage)
|
|||
palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
|
||||
.hw_rev = "rev11",
|
||||
.unsupported_caps = MMC_CAP(MMC_HS_200) |
|
||||
MMC_CAP(UHS_SDR104),
|
||||
.max_freq = 96000000,
|
||||
};
|
||||
|
||||
static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
|
||||
.hw_rev = "rev11",
|
||||
.unsupported_caps = MMC_CAP(MMC_HS_200) |
|
||||
MMC_CAP(UHS_SDR104) |
|
||||
MMC_CAP(UHS_SDR50),
|
||||
.max_freq = 48000000,
|
||||
};
|
||||
|
||||
const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
|
||||
{
|
||||
switch (omap_revision()) {
|
||||
case DRA752_ES1_0:
|
||||
case DRA752_ES1_1:
|
||||
if (addr == OMAP_HSMMC1_BASE)
|
||||
return &dra7x_es1_1_mmc1_fixups;
|
||||
else
|
||||
return &dra7x_es1_1_mmc23_fixups;
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_DWC3
|
||||
|
|
|
@ -49,6 +49,9 @@ CONFIG_DM_GPIO=y
|
|||
CONFIG_PCF8575_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
|
|
|
@ -51,6 +51,9 @@ CONFIG_DM_GPIO=y
|
|||
CONFIG_PCF8575_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
|
|
|
@ -213,8 +213,8 @@ static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
|
|||
mmc->selected_mode = mode;
|
||||
mmc->tran_speed = mmc_mode2freq(mmc, mode);
|
||||
mmc->ddr_mode = mmc_is_mode_ddr(mode);
|
||||
debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
|
||||
mmc->tran_speed / 1000000);
|
||||
pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
|
||||
mmc->tran_speed / 1000000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -457,7 +457,7 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
|
|||
}
|
||||
|
||||
if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
|
||||
debug("%s: Failed to set blocklen\n", __func__);
|
||||
pr_debug("%s: Failed to set blocklen\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -465,7 +465,7 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
|
|||
cur = (blocks_todo > mmc->cfg->b_max) ?
|
||||
mmc->cfg->b_max : blocks_todo;
|
||||
if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
|
||||
debug("%s: Failed to read blocks\n", __func__);
|
||||
pr_debug("%s: Failed to read blocks\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
blocks_todo -= cur;
|
||||
|
@ -900,11 +900,11 @@ static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
|
|||
forbidden = MMC_CAP(MMC_HS_200);
|
||||
|
||||
if (MMC_CAP(mmc->selected_mode) & forbidden) {
|
||||
debug("selected mode (%s) is forbidden for part %d\n",
|
||||
mmc_mode_name(mmc->selected_mode), part_num);
|
||||
pr_debug("selected mode (%s) is forbidden for part %d\n",
|
||||
mmc_mode_name(mmc->selected_mode), part_num);
|
||||
change = true;
|
||||
} else if (mmc->selected_mode != mmc->best_mode) {
|
||||
debug("selected mode is not optimal\n");
|
||||
pr_debug("selected mode is not optimal\n");
|
||||
change = true;
|
||||
}
|
||||
|
||||
|
@ -1333,7 +1333,7 @@ static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
|
||||
if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
|
||||
return -ENOTSUPP;
|
||||
|
||||
return 0;
|
||||
|
@ -1427,7 +1427,7 @@ retry_ssr:
|
|||
mmc->ssr.erase_offset = eo * 1000;
|
||||
}
|
||||
} else {
|
||||
debug("Invalid Allocation Unit Size.\n");
|
||||
pr_debug("Invalid Allocation Unit Size.\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -1532,18 +1532,18 @@ void mmc_dump_capabilities(const char *text, uint caps)
|
|||
{
|
||||
enum bus_mode mode;
|
||||
|
||||
printf("%s: widths [", text);
|
||||
pr_debug("%s: widths [", text);
|
||||
if (caps & MMC_MODE_8BIT)
|
||||
printf("8, ");
|
||||
pr_debug("8, ");
|
||||
if (caps & MMC_MODE_4BIT)
|
||||
printf("4, ");
|
||||
pr_debug("4, ");
|
||||
if (caps & MMC_MODE_1BIT)
|
||||
printf("1, ");
|
||||
printf("\b\b] modes [");
|
||||
pr_debug("1, ");
|
||||
pr_debug("\b\b] modes [");
|
||||
for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
|
||||
if (MMC_CAP(mode) & caps)
|
||||
printf("%s, ", mmc_mode_name(mode));
|
||||
printf("\b\b]\n");
|
||||
pr_debug("%s, ", mmc_mode_name(mode));
|
||||
pr_debug("\b\b]\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -1577,7 +1577,7 @@ static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
|
|||
mmc->signal_voltage = signal_voltage;
|
||||
err = mmc_set_ios(mmc);
|
||||
if (err)
|
||||
debug("unable to set voltage (err %d)\n", err);
|
||||
pr_debug("unable to set voltage (err %d)\n", err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
@ -1660,10 +1660,10 @@ static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
|
|||
|
||||
for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
|
||||
if (*w & caps & mwt->widths) {
|
||||
debug("trying mode %s width %d (at %d MHz)\n",
|
||||
mmc_mode_name(mwt->mode),
|
||||
bus_width(*w),
|
||||
mmc_mode2freq(mmc, mwt->mode) / 1000000);
|
||||
pr_debug("trying mode %s width %d (at %d MHz)\n",
|
||||
mmc_mode_name(mwt->mode),
|
||||
bus_width(*w),
|
||||
mmc_mode2freq(mmc, mwt->mode) / 1000000);
|
||||
|
||||
/* configure the bus width (card + host) */
|
||||
err = sd_select_bus_width(mmc, bus_width(*w));
|
||||
|
@ -1686,7 +1686,7 @@ static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
|
|||
err = mmc_execute_tuning(mmc,
|
||||
mwt->tuning);
|
||||
if (err) {
|
||||
debug("tuning failed\n");
|
||||
pr_debug("tuning failed\n");
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
@ -1708,7 +1708,7 @@ error:
|
|||
}
|
||||
}
|
||||
|
||||
printf("unable to select a mode\n");
|
||||
pr_err("unable to select a mode\n");
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
|
@ -1860,7 +1860,7 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
|
|||
return 0;
|
||||
|
||||
if (!mmc->ext_csd) {
|
||||
debug("No ext_csd found!\n"); /* this should enver happen */
|
||||
pr_debug("No ext_csd found!\n"); /* this should enver happen */
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
|
@ -1870,10 +1870,10 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
|
|||
for_each_supported_width(card_caps & mwt->widths,
|
||||
mmc_is_mode_ddr(mwt->mode), ecbw) {
|
||||
enum mmc_voltage old_voltage;
|
||||
debug("trying mode %s width %d (at %d MHz)\n",
|
||||
mmc_mode_name(mwt->mode),
|
||||
bus_width(ecbw->cap),
|
||||
mmc_mode2freq(mmc, mwt->mode) / 1000000);
|
||||
pr_debug("trying mode %s width %d (at %d MHz)\n",
|
||||
mmc_mode_name(mwt->mode),
|
||||
bus_width(ecbw->cap),
|
||||
mmc_mode2freq(mmc, mwt->mode) / 1000000);
|
||||
old_voltage = mmc->signal_voltage;
|
||||
err = mmc_set_lowest_voltage(mmc, mwt->mode,
|
||||
MMC_ALL_SIGNAL_VOLTAGE);
|
||||
|
@ -1914,7 +1914,7 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
|
|||
if (mwt->tuning) {
|
||||
err = mmc_execute_tuning(mmc, mwt->tuning);
|
||||
if (err) {
|
||||
debug("tuning failed\n");
|
||||
pr_debug("tuning failed\n");
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
@ -1950,6 +1950,7 @@ static int mmc_startup_v4(struct mmc *mmc)
|
|||
MMC_VERSION_4_1,
|
||||
MMC_VERSION_4_2,
|
||||
MMC_VERSION_4_3,
|
||||
MMC_VERSION_4_4,
|
||||
MMC_VERSION_4_41,
|
||||
MMC_VERSION_4_5,
|
||||
MMC_VERSION_5_0,
|
||||
|
@ -2396,12 +2397,12 @@ static int mmc_power_init(struct mmc *mmc)
|
|||
ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
|
||||
&mmc->vmmc_supply);
|
||||
if (ret)
|
||||
debug("%s: No vmmc supply\n", mmc->dev->name);
|
||||
pr_debug("%s: No vmmc supply\n", mmc->dev->name);
|
||||
|
||||
ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
|
||||
&mmc->vqmmc_supply);
|
||||
if (ret)
|
||||
debug("%s: No vqmmc supply\n", mmc->dev->name);
|
||||
pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
|
||||
#endif
|
||||
#else /* !CONFIG_DM_MMC */
|
||||
/*
|
||||
|
@ -2457,7 +2458,7 @@ static int mmc_power_off(struct mmc *mmc)
|
|||
int ret = regulator_set_enable(mmc->vmmc_supply, false);
|
||||
|
||||
if (ret) {
|
||||
debug("Error disabling VMMC supply\n");
|
||||
pr_debug("Error disabling VMMC supply\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
@ -2505,7 +2506,7 @@ int mmc_start_init(struct mmc *mmc)
|
|||
if (no_card) {
|
||||
mmc->has_init = 0;
|
||||
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
|
||||
printf("MMC: no card present\n");
|
||||
pr_err("MMC: no card present\n");
|
||||
#endif
|
||||
return -ENOMEDIUM;
|
||||
}
|
||||
|
@ -2532,7 +2533,7 @@ int mmc_start_init(struct mmc *mmc)
|
|||
* to use the UHS modes, because we wouldn't be able to
|
||||
* recover from an error during the UHS initialization.
|
||||
*/
|
||||
debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
|
||||
pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
|
||||
uhs_en = false;
|
||||
mmc->host_caps &= ~UHS_CAPS;
|
||||
err = mmc_power_on(mmc);
|
||||
|
@ -2629,7 +2630,7 @@ int mmc_init(struct mmc *mmc)
|
|||
if (!err)
|
||||
err = mmc_complete_init(mmc);
|
||||
if (err)
|
||||
printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
|
||||
pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -15,9 +15,7 @@
|
|||
#include <environment/ti/dfu.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_IODELAY_RECALIBRATION
|
||||
#endif
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 2
|
||||
|
||||
|
|
|
@ -14,9 +14,7 @@
|
|||
|
||||
#include <environment/ti/dfu.h>
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_IODELAY_RECALIBRATION
|
||||
#endif
|
||||
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_NR_DRAM_BANKS 2
|
||||
|
|
|
@ -54,6 +54,7 @@
|
|||
#define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
|
||||
#define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
|
||||
#define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
|
||||
#define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
|
||||
#define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
|
||||
#define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
|
||||
#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
|
||||
|
|
Loading…
Add table
Reference in a new issue