mirror of
https://github.com/Fishwaldo/u-boot.git
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* Patch by Hans-Joerg Frieden, 06 Dec 2002
Fix misc problems with AmigaOne support * Patch by Chris Hallinan, 3 Dec 2002: minor cleanup to the MPC8245 EPIC driver * Patch by Pierre Aubert , 28 Nov 2002 Add support for external (SIU) interrupts on MPC8xx * Patch by Pierre Aubert , 28 Nov 2002 Fix nested syscalls bug in standalone applications * Patch by David Mller, 27 Nov 2002: fix output of "pciinfo" command for CardBus bridge devices. * Fix bug in TQM8260 board detection - boards got stuck when board ID was not readable
This commit is contained in:
wdenk
parent
1f53a41603
commit
7c7a23bd5a
30 changed files with 589 additions and 262 deletions
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@ -177,7 +177,14 @@ SystemCall:
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add r11,r11,r0
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lwz r11,0(r11)
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li r12,0xd00-4*3 /* save LR & SRRx */
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li r20,0xd00-4 /* Get stack pointer */
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lwz r12,0(r20)
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subi r12,r12,12 /* Adjust stack pointer */
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li r0,0xc00+_end_back-SystemCall
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cmplw 0, r0, r12 /* Check stack overflow */
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bgt 1f
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stw r12,0(r20)
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mflr r0
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stw r0,0(r12)
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mfspr r0,SRR0
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@ -202,7 +209,9 @@ _back:
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mtmsr r11
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SYNC
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li r12,0xd00-4*3 /* restore regs */
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li r12,0xd00-4 /* restore regs */
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lwz r12,0(r12)
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lwz r11,0(r12)
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mtlr r11
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lwz r11,4(r12)
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@ -210,8 +219,13 @@ _back:
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lwz r11,8(r12)
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mtspr SRR1,r11
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addi r12,r12,12 /* Adjust stack pointer */
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li r20,0xd00-4
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stw r12,0(r20)
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SYNC
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rfi
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_end_back:
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STD_EXCEPTION(0xd00, SingleStep, UnknownException)
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@ -716,6 +730,9 @@ in_ram:
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bne 5b
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6:
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mr r3, r10 /* Destination Address */
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#ifdef CONFIG_AMIGAONEG3SE
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mr r4, r9 /* Use RAM copy of the global data */
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#endif
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bl after_reloc
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/* not reached - end relocate_code */
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@ -108,6 +108,9 @@
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#define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */
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#define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */
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#define EPIC_VEC_PRI_MASK 0x80000000 /* Mask Interrupt bit in IVPR */
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#define EPIC_VEC_PRI_DFLT_PRI 8 /* Interrupt Priority in IVPR */
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/* Error code */
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#define OK 0
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@ -70,6 +70,10 @@ void epicInit
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tmp = sysEUMBBARRead(EPIC_GLOBAL_REG);
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tmp |= 0xa0000000; /* Set the Global Conf. register */
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sysEUMBBARWrite(EPIC_GLOBAL_REG, tmp);
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/*
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* Wait for EPIC to reset - CLH
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*/
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while( (sysEUMBBARRead(EPIC_GLOBAL_REG) & 0x80000000) == 1);
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sysEUMBBARWrite(EPIC_GLOBAL_REG, 0x20000000);
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tmp = sysEUMBBARRead(EPIC_INT_CONF_REG); /* Read interrupt conf. reg */
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@ -81,7 +85,8 @@ void epicInit
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sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp);
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}
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while (epicIntAck() != 0xff); /* Clear all pending interrupts */
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while (epicIntAck() != 0xff) /* Clear all pending interrupts */
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epicEOI();
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}
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/****************************************************************************
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@ -92,18 +97,18 @@ void epicInit
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*
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* RETURNS: None
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*/
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void epicIntEnable
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(
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int intVec /* Interrupt Vector Number */
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)
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{
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void epicIntEnable(int intVec)
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{
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ULONG tmp;
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ULONG srAddr;
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srAddr = SrcVecTable[intVec].srcAddr; /* Retrieve src Vec/Prio register */
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tmp = sysEUMBBARRead(srAddr);
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tmp &= 0x7fffffff; /* Clear the mask bit */
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tmp &= ~EPIC_VEC_PRI_MASK; /* Clear the mask bit */
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tmp |= (EPIC_VEC_PRI_DFLT_PRI << 16); /* Set priority to Default - CLH */
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tmp |= intVec; /* Set Vector number */
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sysEUMBBARWrite(srAddr, tmp);
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return;
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}
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@ -92,6 +92,8 @@ int interrupt_init (void)
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*/
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epicInit (EPIC_DIRECT_IRQ, 0);
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/* EPIC won't generate INT unless Current Task Pri < 15 */
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epicCurTaskPrioSet(0);
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set_dec (decrementer_count);
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@ -278,7 +278,14 @@ SystemCall:
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add r11,r11,r0
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lwz r11,0(r11)
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li r12,0xd00-4*3 /* save LR & SRRx */
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li r20,0xd00-4 /* Get stack pointer */
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lwz r12,0(r20)
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subi r12,r12,12 /* Adjust stack pointer */
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li r0,0xc00+_end_back-SystemCall
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cmplw 0, r0, r12 /* Check stack overflow */
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bgt 1f
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stw r12,0(r20)
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mflr r0
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stw r0,0(r12)
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mfspr r0,SRR0
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@ -303,7 +310,9 @@ _back:
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mtmsr r11
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SYNC
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li r12,0xd00-4*3 /* restore regs */
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li r12,0xd00-4 /* restore regs */
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lwz r12,0(r12)
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lwz r11,0(r12)
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mtlr r11
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lwz r11,4(r12)
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@ -311,8 +320,13 @@ _back:
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lwz r11,8(r12)
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mtspr SRR1,r11
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addi r12,r12,12 /* Adjust stack pointer */
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li r20,0xd00-4
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stw r12,0(r20)
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SYNC
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rfi
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_end_back:
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STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException)
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@ -324,7 +324,14 @@ SystemCall:
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add r11,r11,r0
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lwz r11,0(r11)
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li r12,0xd00-4*3 /* save LR & SRRx */
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li r20,0xd00-4 /* Get stack pointer */
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lwz r12,0(r20)
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subi r12,r12,12 /* Adjust stack pointer */
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li r0,0xc00+_end_back-SystemCall
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cmplw 0, r0, r12 /* Check stack overflow */
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bgt 1f
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stw r12,0(r20)
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mflr r0
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stw r0,0(r12)
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mfspr r0,SRR0
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@ -349,7 +356,9 @@ _back:
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mtmsr r11
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SYNC
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li r12,0xd00-4*3 /* restore regs */
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li r12,0xd00-4 /* restore regs */
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lwz r12,0(r12)
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lwz r11,0(r12)
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mtlr r11
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lwz r11,4(r12)
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@ -357,8 +366,13 @@ _back:
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lwz r11,8(r12)
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mtspr SRR1,r11
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addi r12,r12,12 /* Adjust stack pointer */
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li r20,0xd00-4
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stw r12,0(r20)
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SYNC
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rfi
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_end_back:
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STD_EXCEPTION(0xd00, SingleStep, UnknownException)
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@ -28,99 +28,104 @@
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#include <asm/processor.h>
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#include <commproc.h>
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/****************************************************************************/
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/************************************************************************/
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unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
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unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
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/****************************************************************************/
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/************************************************************************/
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/*
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* CPM interrupt vector functions.
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*/
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struct cpm_action {
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interrupt_handler_t *handler;
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void *arg;
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struct interrupt_action {
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interrupt_handler_t *handler;
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void *arg;
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};
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static struct cpm_action cpm_vecs[CPMVEC_NR];
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static struct interrupt_action cpm_vecs[CPMVEC_NR];
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static struct interrupt_action irq_vecs[NR_IRQS];
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static void cpm_interrupt_init (void);
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static void cpm_interrupt(int irq, struct pt_regs * regs);
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static void cpm_interrupt (void *regs);
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/****************************************************************************/
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/************************************************************************/
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static __inline__ unsigned long get_msr(void)
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static __inline__ unsigned long get_msr (void)
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{
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unsigned long msr;
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unsigned long msr;
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asm volatile("mfmsr %0" : "=r" (msr) :);
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return msr;
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asm volatile ("mfmsr %0":"=r" (msr):);
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return msr;
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}
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static __inline__ void set_msr(unsigned long msr)
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static __inline__ void set_msr (unsigned long msr)
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{
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asm volatile("mtmsr %0" : : "r" (msr));
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asm volatile ("mtmsr %0"::"r" (msr));
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}
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static __inline__ unsigned long get_dec(void)
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static __inline__ unsigned long get_dec (void)
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{
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unsigned long val;
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unsigned long val;
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asm volatile("mfdec %0" : "=r" (val) :);
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return val;
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asm volatile ("mfdec %0":"=r" (val):);
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return val;
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}
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static __inline__ void set_dec(unsigned long val)
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static __inline__ void set_dec (unsigned long val)
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{
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asm volatile("mtdec %0" : : "r" (val));
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asm volatile ("mtdec %0"::"r" (val));
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}
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void enable_interrupts (void)
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{
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set_msr (get_msr() | MSR_EE);
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set_msr (get_msr () | MSR_EE);
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}
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/* returns flag if MSR_EE was set before */
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int disable_interrupts (void)
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{
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ulong msr = get_msr();
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ulong msr = get_msr ();
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set_msr (msr & ~MSR_EE);
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return ((msr & MSR_EE) != 0);
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}
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/****************************************************************************/
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/************************************************************************/
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int interrupt_init(void)
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int interrupt_init (void)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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decrementer_count = get_tbclk() / CFG_HZ;
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decrementer_count = get_tbclk () / CFG_HZ;
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cpm_interrupt_init();
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/* disable all interrupts */
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immr->im_siu_conf.sc_simask = 0;
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/* disable all interrupts except for the CPM interrupt */
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immr->im_siu_conf.sc_simask = 1 << (31-CPM_INTERRUPT);
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/* Configure CPM interrupts */
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cpm_interrupt_init ();
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set_dec (decrementer_count);
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set_msr (get_msr() | MSR_EE);
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set_msr (get_msr () | MSR_EE);
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return (0);
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}
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/****************************************************************************/
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/************************************************************************/
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/*
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* Handle external interrupts
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*/
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void external_interrupt(struct pt_regs *regs)
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void external_interrupt (struct pt_regs *regs)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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int irq;
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ulong simask, newmask;
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ulong vec, v_bit;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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int irq;
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ulong simask, newmask;
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ulong vec, v_bit;
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/*
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* read the SIVEC register and shift the bits down
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@ -137,14 +142,15 @@ void external_interrupt(struct pt_regs *regs)
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newmask = simask & (~(0xFFFF0000 >> irq));
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immr->im_siu_conf.sc_simask = newmask;
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if (!(irq & 0x1)) { /* External Interrupt ? */
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if (!(irq & 0x1)) { /* External Interrupt ? */
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ulong siel;
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/*
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* Read Interrupt Edge/Level Register
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*/
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siel = immr->im_siu_conf.sc_siel;
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if (siel & v_bit) { /* edge triggered interrupt ? */
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if (siel & v_bit) { /* edge triggered interrupt ? */
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/*
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* Rewrite SIPEND Register to clear interrupt
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*/
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@ -152,34 +158,29 @@ void external_interrupt(struct pt_regs *regs)
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}
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}
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switch (irq) {
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case CPM_INTERRUPT:
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cpm_interrupt (irq, regs);
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break;
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default:
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if (irq_vecs[irq].handler != NULL) {
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irq_vecs[irq].handler (irq_vecs[irq].arg);
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} else {
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printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
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irq, vec);
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irq, vec);
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/* turn off the bogus interrupt to avoid it from now */
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simask &= ~v_bit;
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break;
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}
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/*
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* Re-Enable old Interrupt Mask
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*/
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immr->im_siu_conf.sc_simask = simask;
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}
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/****************************************************************************/
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/************************************************************************/
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/*
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* CPM interrupt handler
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*/
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static void
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cpm_interrupt(int irq, struct pt_regs * regs)
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static void cpm_interrupt (void *regs)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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uint vec;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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uint vec;
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/*
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* Get the vector by setting the ACK bit
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@ -190,13 +191,14 @@ cpm_interrupt(int irq, struct pt_regs * regs)
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vec >>= 11;
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if (cpm_vecs[vec].handler != NULL) {
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(*cpm_vecs[vec].handler)(cpm_vecs[vec].arg);
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(*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
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} else {
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immr->im_cpic.cpic_cimr &= ~(1 << vec);
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printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
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}
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/*
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* After servicing the interrupt, we have to remove the status indicator.
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* After servicing the interrupt,
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* we have to remove the status indicator.
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*/
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immr->im_cpic.cpic_cisr |= (1 << vec);
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}
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@ -207,75 +209,110 @@ cpm_interrupt(int irq, struct pt_regs * regs)
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* to do is ACK it and return. This is a no-op function so we don't
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* need any special tests in the interrupt handler.
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*/
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static void
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cpm_error_interrupt (void *dummy)
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static void cpm_error_interrupt (void *dummy)
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{
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}
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/****************************************************************************/
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/************************************************************************/
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/*
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* Install and free a CPM interrupt handler.
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* Install and free an interrupt handler
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*/
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void
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irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
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void irq_install_handler (int vec, interrupt_handler_t * handler,
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void *arg)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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if (cpm_vecs[vec].handler != NULL) {
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printf ("CPM interrupt 0x%x replacing 0x%x\n",
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(uint)handler, (uint)cpm_vecs[vec].handler);
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if ((vec & CPMVEC_OFFSET) != 0) {
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/* CPM interrupt */
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vec &= 0xffff;
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if (cpm_vecs[vec].handler != NULL) {
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printf ("CPM interrupt 0x%x replacing 0x%x\n",
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(uint) handler,
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(uint) cpm_vecs[vec].handler);
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}
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cpm_vecs[vec].handler = handler;
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cpm_vecs[vec].arg = arg;
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immr->im_cpic.cpic_cimr |= (1 << vec);
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#if 0
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printf ("Install CPM interrupt for vector %d ==> %p\n",
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vec, handler);
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#endif
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} else {
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/* SIU interrupt */
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if (irq_vecs[vec].handler != NULL) {
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printf ("SIU interrupt %d 0x%x replacing 0x%x\n",
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vec,
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(uint) handler,
|
||||
(uint) cpm_vecs[vec].handler);
|
||||
}
|
||||
irq_vecs[vec].handler = handler;
|
||||
irq_vecs[vec].arg = arg;
|
||||
immr->im_siu_conf.sc_simask |= 1 << (31 - vec);
|
||||
#if 0
|
||||
printf ("Install SIU interrupt for vector %d ==> %p\n",
|
||||
vec, handler);
|
||||
#endif
|
||||
}
|
||||
cpm_vecs[vec].handler = handler;
|
||||
cpm_vecs[vec].arg = arg;
|
||||
immr->im_cpic.cpic_cimr |= (1 << vec);
|
||||
#if 0
|
||||
printf ("Install CPM interrupt for vector %d ==> %p\n", vec, handler);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
irq_free_handler(int vec)
|
||||
void irq_free_handler (int vec)
|
||||
{
|
||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
||||
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||
|
||||
if ((vec & CPMVEC_OFFSET) != 0) {
|
||||
/* CPM interrupt */
|
||||
vec &= 0xffff;
|
||||
#if 0
|
||||
printf ("Free CPM interrupt for vector %d ==> %p\n",
|
||||
vec, cpm_vecs[vec].handler);
|
||||
printf ("Free CPM interrupt for vector %d ==> %p\n",
|
||||
vec, cpm_vecs[vec].handler);
|
||||
#endif
|
||||
immr->im_cpic.cpic_cimr &= ~(1 << vec);
|
||||
cpm_vecs[vec].handler = NULL;
|
||||
cpm_vecs[vec].arg = NULL;
|
||||
immr->im_cpic.cpic_cimr &= ~(1 << vec);
|
||||
cpm_vecs[vec].handler = NULL;
|
||||
cpm_vecs[vec].arg = NULL;
|
||||
} else {
|
||||
/* SIU interrupt */
|
||||
#if 0
|
||||
printf ("Free CPM interrupt for vector %d ==> %p\n",
|
||||
vec, cpm_vecs[vec].handler);
|
||||
#endif
|
||||
immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec));
|
||||
irq_vecs[vec].handler = NULL;
|
||||
irq_vecs[vec].arg = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/************************************************************************/
|
||||
|
||||
static void
|
||||
cpm_interrupt_init (void)
|
||||
static void cpm_interrupt_init (void)
|
||||
{
|
||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
||||
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||
|
||||
/*
|
||||
* Initialize the CPM interrupt controller.
|
||||
*/
|
||||
|
||||
immr->im_cpic.cpic_cicr =
|
||||
( CICR_SCD_SCC4 |
|
||||
CICR_SCC_SCC3 |
|
||||
CICR_SCB_SCC2 |
|
||||
CICR_SCA_SCC1 ) | ((CPM_INTERRUPT/2) << 13) | CICR_HP_MASK;
|
||||
(CICR_SCD_SCC4 |
|
||||
CICR_SCC_SCC3 |
|
||||
CICR_SCB_SCC2 |
|
||||
CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
|
||||
|
||||
immr->im_cpic.cpic_cimr = 0;
|
||||
|
||||
/*
|
||||
* Install the error handler.
|
||||
*/
|
||||
irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
|
||||
irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
|
||||
|
||||
immr->im_cpic.cpic_cicr |= CICR_IEN;
|
||||
|
||||
/*
|
||||
* Install the cpm interrupt handler
|
||||
*/
|
||||
irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL);
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/************************************************************************/
|
||||
|
||||
volatile ulong timestamp = 0;
|
||||
|
||||
|
|
@ -284,18 +321,19 @@ volatile ulong timestamp = 0;
|
|||
* with interrupts disabled.
|
||||
* Trivial implementation - no need to be really accurate.
|
||||
*/
|
||||
void timer_interrupt(struct pt_regs *regs)
|
||||
void timer_interrupt (struct pt_regs *regs)
|
||||
{
|
||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
||||
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||
|
||||
#ifdef CONFIG_STATUS_LED
|
||||
extern void status_led_tick (ulong);
|
||||
extern void status_led_tick (ulong);
|
||||
#endif
|
||||
#if 0
|
||||
printf ("*** Timer Interrupt *** ");
|
||||
#endif
|
||||
/* Reset Timer Expired and Timers Interrupt Status */
|
||||
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
|
||||
__asm__("nop");
|
||||
__asm__ ("nop");
|
||||
immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST;
|
||||
/* Restore Decrementer Count */
|
||||
set_dec (decrementer_count);
|
||||
|
|
@ -304,11 +342,10 @@ void timer_interrupt(struct pt_regs *regs)
|
|||
|
||||
#ifdef CONFIG_STATUS_LED
|
||||
status_led_tick (timestamp);
|
||||
#endif /* CONFIG_STATUS_LED */
|
||||
#endif /* CONFIG_STATUS_LED */
|
||||
|
||||
#if defined(CONFIG_WATCHDOG) || defined(CFG_CMA_LCD_HEARTBEAT)
|
||||
|
||||
|
||||
/*
|
||||
* The shortest watchdog period of all boards (except LWMON)
|
||||
* is approx. 1 sec, thus re-trigger watchdog at least
|
||||
|
|
@ -321,20 +358,20 @@ void timer_interrupt(struct pt_regs *regs)
|
|||
#endif
|
||||
|
||||
#if defined(CFG_CMA_LCD_HEARTBEAT)
|
||||
extern void lcd_heartbeat(void);
|
||||
lcd_heartbeat();
|
||||
extern void lcd_heartbeat (void);
|
||||
|
||||
lcd_heartbeat ();
|
||||
#endif /* CFG_CMA_LCD_HEARTBEAT */
|
||||
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
reset_8xx_watchdog(immr);
|
||||
reset_8xx_watchdog (immr);
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
|
||||
}
|
||||
|
||||
#endif /* CONFIG_WATCHDOG || CFG_CMA_LCD_HEARTBEAT */
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/************************************************************************/
|
||||
|
||||
void reset_timer (void)
|
||||
{
|
||||
|
|
@ -351,4 +388,4 @@ void set_timer (ulong t)
|
|||
timestamp = t;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/************************************************************************/
|
||||
|
|
|
|||
|
|
@ -285,7 +285,14 @@ SystemCall:
|
|||
add r11,r11,r0
|
||||
lwz r11,0(r11)
|
||||
|
||||
li r12,0xd00-4*3 /* save LR & SRRx */
|
||||
li r20,0xd00-4 /* Get stack pointer */
|
||||
lwz r12,0(r20)
|
||||
subi r12,r12,12 /* Adjust stack pointer */
|
||||
li r0,0xc00+_end_back-SystemCall
|
||||
cmplw 0, r0, r12 /* Check stack overflow */
|
||||
bgt 1f
|
||||
stw r12,0(r20)
|
||||
|
||||
mflr r0
|
||||
stw r0,0(r12)
|
||||
mfspr r0,SRR0
|
||||
|
|
@ -310,7 +317,9 @@ _back:
|
|||
mtmsr r11
|
||||
SYNC
|
||||
|
||||
li r12,0xd00-4*3 /* restore regs */
|
||||
li r12,0xd00-4 /* restore regs */
|
||||
lwz r12,0(r12)
|
||||
|
||||
lwz r11,0(r12)
|
||||
mtlr r11
|
||||
lwz r11,4(r12)
|
||||
|
|
@ -318,8 +327,13 @@ _back:
|
|||
lwz r11,8(r12)
|
||||
mtspr SRR1,r11
|
||||
|
||||
addi r12,r12,12 /* Adjust stack pointer */
|
||||
li r20,0xd00-4
|
||||
stw r12,0(r20)
|
||||
|
||||
SYNC
|
||||
rfi
|
||||
_end_back:
|
||||
|
||||
STD_EXCEPTION(0xd00, SingleStep, UnknownException)
|
||||
|
||||
|
|
|
|||
|
|
@ -775,7 +775,14 @@ SystemCall:
|
|||
add r11,r11,r0
|
||||
lwz r11,0(r11)
|
||||
|
||||
li r12,0xd00-4*3 /* save LR & SRRx */
|
||||
li r20,0xd00-4 /* Get stack pointer */
|
||||
lwz r12,0(r20)
|
||||
subi r12,r12,12 /* Adjust stack pointer */
|
||||
li r0,0xc00+_end_back-SystemCall
|
||||
cmplw 0, r0, r12 /* Check stack overflow */
|
||||
bgt 1f
|
||||
stw r12,0(r20)
|
||||
|
||||
mflr r0
|
||||
stw r0,0(r12)
|
||||
mfspr r0,SRR0
|
||||
|
|
@ -800,7 +807,9 @@ _back:
|
|||
mtmsr r11
|
||||
SYNC
|
||||
|
||||
li r12,0xd00-4*3 /* restore regs */
|
||||
li r12,0xd00-4 /* restore regs */
|
||||
lwz r12,0(r12)
|
||||
|
||||
lwz r11,0(r12)
|
||||
mtlr r11
|
||||
lwz r11,4(r12)
|
||||
|
|
@ -808,8 +817,13 @@ _back:
|
|||
lwz r11,8(r12)
|
||||
mtspr SRR1,r11
|
||||
|
||||
addi r12,r12,12 /* Adjust stack pointer */
|
||||
li r20,0xd00-4
|
||||
stw r12,0(r20)
|
||||
|
||||
SYNC
|
||||
rfi
|
||||
_end_back:
|
||||
|
||||
STD_EXCEPTION(0xd00, SingleStep, UnknownException)
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue