ARM change name of defines for AT91 arm926ejs

Configuration defines should be preceeded with CONFIG_SYS_. Renamed
some at91 specific defines to conform to this naming convention:

AT91_CPU_NAME to CONFIG_SYS_AT91_CPU_NAME
AT91_MAIN_CLOCK to CONFIG_SYS_AT91_MAIN_CLOCK

Signed-off-by: Achim Ehrlich <aehrlich@taskit.de>
This commit is contained in:
Achim Ehrlich 2010-02-24 10:29:16 +01:00 committed by Tom Rix
parent 5c97a1de19
commit 7c966a8bdf
29 changed files with 34 additions and 34 deletions

View file

@ -282,7 +282,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n"); lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n", lcd_printf ("%s CPU at %s MHz\n",
AT91_CPU_NAME, CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate())); strmhz(temp, get_cpu_clk_rate()));
dram_size = 0; dram_size = 0;

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@ -217,7 +217,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n"); lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n", lcd_printf ("%s CPU at %s MHz\n",
AT91_CPU_NAME, CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate())); strmhz(temp, get_cpu_clk_rate()));
dram_size = 0; dram_size = 0;

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@ -218,7 +218,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n"); lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n", lcd_printf ("%s CPU at %s MHz\n",
AT91_CPU_NAME, CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate())); strmhz(temp, get_cpu_clk_rate()));
dram_size = 0; dram_size = 0;

View file

@ -217,7 +217,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n"); lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n", lcd_printf ("%s CPU at %s MHz\n",
AT91_CPU_NAME, CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate())); strmhz(temp, get_cpu_clk_rate()));
dram_size = 0; dram_size = 0;

View file

@ -157,7 +157,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n"); lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n", lcd_printf ("%s CPU at %s MHz\n",
AT91_CPU_NAME, CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate())); strmhz(temp, get_cpu_clk_rate()));
dram_size = 0; dram_size = 0;

View file

@ -219,7 +219,7 @@ void lcd_show_board_info(void)
nand_size += nand_info[i].size; nand_size += nand_info[i].size;
lcd_printf("\n%s\n", U_BOOT_VERSION); lcd_printf("\n%s\n", U_BOOT_VERSION);
lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME, lcd_printf("%s CPU at %s MHz\n", CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate())); strmhz(temp, get_cpu_clk_rate()));
lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20, dram_size >> 20,

View file

@ -189,7 +189,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2009 Ronetix GmbH\n"); lcd_printf ("(C) 2009 Ronetix GmbH\n");
lcd_printf ("support@ronetix.at\n"); lcd_printf ("support@ronetix.at\n");
lcd_printf ("%s CPU at %s MHz", lcd_printf ("%s CPU at %s MHz",
AT91_CPU_NAME, CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate())); strmhz(temp, get_cpu_clk_rate()));
dram_size = 0; dram_size = 0;

View file

@ -304,7 +304,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2009 Ronetix GmbH\n"); lcd_printf ("(C) 2009 Ronetix GmbH\n");
lcd_printf ("support@ronetix.at\n"); lcd_printf ("support@ronetix.at\n");
lcd_printf ("%s CPU at %s MHz", lcd_printf ("%s CPU at %s MHz",
AT91_CPU_NAME, CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate())); strmhz(temp, get_cpu_clk_rate()));
dram_size = 0; dram_size = 0;

View file

@ -147,7 +147,7 @@ int at91_clock_init(unsigned long main_clock)
{ {
unsigned freq, mckr; unsigned freq, mckr;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
#ifndef AT91_MAIN_CLOCK #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
unsigned tmp; unsigned tmp;
/* /*
* When the bootloader initialized the main oscillator correctly, * When the bootloader initialized the main oscillator correctly,

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@ -31,13 +31,13 @@
#include <asm/arch/clk.h> #include <asm/arch/clk.h>
#include <asm/arch/io.h> #include <asm/arch/io.h>
#ifndef AT91_MAIN_CLOCK #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
#define AT91_MAIN_CLOCK 0 #define CONFIG_SYS_AT91_MAIN_CLOCK 0
#endif #endif
int arch_cpu_init(void) int arch_cpu_init(void)
{ {
return at91_clock_init(AT91_MAIN_CLOCK); return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
} }
#if defined(CONFIG_DISPLAY_CPUINFO) #if defined(CONFIG_DISPLAY_CPUINFO)
@ -45,7 +45,7 @@ int print_cpuinfo(void)
{ {
char buf[32]; char buf[32];
printf("CPU: %s\n", AT91_CPU_NAME); printf("CPU: %s\n", CONFIG_SYS_AT91_CPU_NAME);
printf("Crystal frequency: %8s MHz\n", printf("Crystal frequency: %8s MHz\n",
strmhz(buf, get_main_clk_rate())); strmhz(buf, get_main_clk_rate()));
printf("CPU clock : %8s MHz\n", printf("CPU clock : %8s MHz\n",

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@ -145,6 +145,6 @@
/* /*
* Cpu Name * Cpu Name
*/ */
#define AT91_CPU_NAME "AT91CAP9" #define CONFIG_SYS_AT91_CPU_NAME "AT91CAP9"
#endif #endif

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@ -130,6 +130,6 @@
#define AT91_PMX_CA_NCS7 0x00002000 #define AT91_PMX_CA_NCS7 0x00002000
#define AT91_PMX_CA_D16_31 0xFFFF0000 #define AT91_PMX_CA_D16_31 0xFFFF0000
#define AT91_CPU_NAME "AT91RM9200" #define CONFIG_SYS_AT91_CPU_NAME "AT91RM9200"
#endif #endif

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@ -139,9 +139,9 @@
* Cpu Name * Cpu Name
*/ */
#if defined(CONFIG_AT91SAM9260) #if defined(CONFIG_AT91SAM9260)
#define AT91_CPU_NAME "AT91SAM9260" #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260"
#elif defined(CONFIG_AT91SAM9G20) #elif defined(CONFIG_AT91SAM9G20)
#define AT91_CPU_NAME "AT91SAM9G20" #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20"
#endif #endif
#endif #endif

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@ -114,6 +114,6 @@
/* /*
* Cpu Name * Cpu Name
*/ */
#define AT91_CPU_NAME "AT91SAM9261" #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
#endif #endif

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@ -147,6 +147,6 @@
/* /*
* Cpu Name * Cpu Name
*/ */
#define AT91_CPU_NAME "AT91SAM9263" #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
#endif #endif

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@ -147,6 +147,6 @@
/* /*
* Cpu Name * Cpu Name
*/ */
#define AT91_CPU_NAME "AT91SAM9G45" #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45"
#endif #endif

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@ -125,6 +125,6 @@
/* /*
* Cpu Name * Cpu Name
*/ */
#define AT91_CPU_NAME "AT91SAM9RL" #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9RL"
#endif #endif

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@ -29,7 +29,7 @@
#define CONFIG_AT91_LEGACY #define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */ /* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ #define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/

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@ -30,7 +30,7 @@
#define CONFIG_AT91_LEGACY #define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */ /* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */

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@ -30,7 +30,7 @@
#define CONFIG_AT91_LEGACY #define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */ /* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */

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@ -30,7 +30,7 @@
#define CONFIG_AT91_LEGACY #define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */ /* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */

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@ -28,7 +28,7 @@
#define __CONFIG_H #define __CONFIG_H
/* ARM asynchronous clock */ /* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */

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@ -30,7 +30,7 @@
#define CONFIG_AT91_LEGACY #define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */ /* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */

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@ -30,7 +30,7 @@
#define CONFIG_AT91_LEGACY #define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */ /* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */

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@ -35,7 +35,7 @@
#define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_CPUINFO 1
#define AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 #define CONFIG_ARM926EJS 1

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@ -31,14 +31,14 @@
#define CONFIG_AT91_LEGACY #define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */ /* ARM asynchronous clock */
#define AT91_CPU_NAME "AT91SAM9261" #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_DISPLAY_BOARDINFO
#define MASTER_PLL_DIV 15 #define MASTER_PLL_DIV 15
#define MASTER_PLL_MUL 162 #define MASTER_PLL_MUL 162
#define MAIN_PLL_DIV 2 #define MAIN_PLL_DIV 2
#define AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000

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@ -37,7 +37,7 @@
#define MASTER_PLL_DIV 6 #define MASTER_PLL_DIV 6
#define MASTER_PLL_MUL 65 #define MASTER_PLL_MUL 65
#define MAIN_PLL_DIV 2 /* 2 or 4 */ #define MAIN_PLL_DIV 2 /* 2 or 4 */
#define AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000

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@ -41,7 +41,7 @@
#endif #endif
/* ARM asynchronous clock */ /* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */

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@ -51,7 +51,7 @@
#endif #endif
/* ARM asynchronous clock */ /* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */