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clk: rockchip: Add rk3328 gamc clock support
The rk3328 soc has two gmac controllers, one is gmac2io, the other is gmac2phy. We use the gmac2io rgmii interface for 1000M phy here. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
David Wu
Philipp Tomsich
parent
dfb886d4f2
commit
7cd4ebab2b
2 changed files with 181 additions and 3 deletions
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@ -13,6 +13,7 @@
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3328.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rk3328.h>
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#include <asm/io.h>
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#include <dm/lists.h>
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#include <dt-bindings/clock/rk3328-cru.h>
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@ -94,6 +95,14 @@ enum {
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PCLK_DBG_DIV_SHIFT = 0,
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PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
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/* CLKSEL_CON27 */
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GMAC2IO_PLL_SEL_SHIFT = 7,
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GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT,
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GMAC2IO_PLL_SEL_CPLL = 0,
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GMAC2IO_PLL_SEL_GPLL = 1,
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GMAC2IO_CLK_DIV_MASK = 0x1f,
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GMAC2IO_CLK_DIV_SHIFT = 0,
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/* CLKSEL_CON28 */
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ACLK_PERIHP_PLL_SEL_CPLL = 0,
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ACLK_PERIHP_PLL_SEL_GPLL,
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@ -393,6 +402,44 @@ static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz)
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return DIV_TO_RATE(GPLL_HZ, src_clk_div);
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}
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static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
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{
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struct rk3328_grf_regs *grf;
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ulong ret;
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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/*
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* The RGMII CLK can be derived either from an external "clkin"
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* or can be generated from internally by a divider from SCLK_MAC.
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*/
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if (readl(&grf->mac_con[1]) & BIT(10) &&
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readl(&grf->soc_con[4]) & BIT(14)) {
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/* An external clock will always generate the right rate... */
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ret = rate;
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} else {
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u32 con = readl(&cru->clksel_con[27]);
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ulong pll_rate;
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u8 div;
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if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
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pll_rate = GPLL_HZ;
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else
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pll_rate = CPLL_HZ;
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div = DIV_ROUND_UP(pll_rate, rate) - 1;
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if (div <= 0x1f)
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rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK,
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div << GMAC2IO_CLK_DIV_SHIFT);
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else
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debug("Unsupported div for gmac:%d\n", div);
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return DIV_TO_RATE(pll_rate, div);
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}
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return ret;
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}
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static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
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{
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u32 div, con, con_id;
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@ -558,12 +605,48 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
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case SCLK_I2C3:
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ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
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break;
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case SCLK_MAC2IO:
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ret = rk3328_gmac2io_set_clk(priv->cru, rate);
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break;
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case SCLK_PWM:
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ret = rk3328_pwm_set_clk(priv->cru, rate);
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break;
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case SCLK_SARADC:
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ret = rk3328_saradc_set_clk(priv->cru, rate);
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break;
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case DCLK_LCDC:
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case SCLK_PDM:
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case SCLK_RTC32K:
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case SCLK_UART0:
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case SCLK_UART1:
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case SCLK_UART2:
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case SCLK_SDIO:
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case SCLK_TSP:
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case SCLK_WIFI:
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case ACLK_BUS_PRE:
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case HCLK_BUS_PRE:
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case PCLK_BUS_PRE:
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case ACLK_PERI_PRE:
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case HCLK_PERI:
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case PCLK_PERI:
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case ACLK_VIO_PRE:
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case HCLK_VIO_PRE:
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case ACLK_RGA_PRE:
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case SCLK_RGA:
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case ACLK_VOP_PRE:
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case ACLK_RKVDEC_PRE:
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case ACLK_RKVENC:
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case ACLK_VPU_PRE:
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case SCLK_VDEC_CABAC:
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case SCLK_VDEC_CORE:
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case SCLK_VENC_CORE:
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case SCLK_VENC_DSP:
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case SCLK_EFUSE:
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case PCLK_DDR:
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case ACLK_GMAC:
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case PCLK_GMAC:
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case SCLK_USB3OTG_SUSPEND:
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return 0;
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default:
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return -ENOENT;
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}
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@ -571,9 +654,104 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
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return ret;
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}
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static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
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{
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struct rk3328_grf_regs *grf;
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const char *clock_output_name;
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int ret;
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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/*
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* If the requested parent is in the same clock-controller and the id
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* is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
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*/
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if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) {
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debug("%s: switching RGMII to SCLK_MAC2IO_SRC\n", __func__);
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rk_clrreg(&grf->mac_con[1], BIT(10));
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return 0;
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}
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/*
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* Otherwise, we need to check the clock-output-names of the
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* requested parent to see if the requested id is "gmac_clkin".
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*/
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ret = dev_read_string_index(parent->dev, "clock-output-names",
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parent->id, &clock_output_name);
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if (ret < 0)
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return -ENODATA;
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/* If this is "gmac_clkin", switch to the external clock input */
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if (!strcmp(clock_output_name, "gmac_clkin")) {
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debug("%s: switching RGMII to CLKIN\n", __func__);
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rk_setreg(&grf->mac_con[1], BIT(10));
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return 0;
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}
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return -EINVAL;
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}
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static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
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{
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struct rk3328_grf_regs *grf;
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const char *clock_output_name;
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int ret;
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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/*
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* If the requested parent is in the same clock-controller and the id
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* is SCLK_MAC2IO ("clk_mac2io"), switch to the internal clock.
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*/
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if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO)) {
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debug("%s: switching RGMII to SCLK_MAC2IO\n", __func__);
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rk_clrreg(&grf->soc_con[4], BIT(14));
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return 0;
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}
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/*
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* Otherwise, we need to check the clock-output-names of the
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* requested parent to see if the requested id is "gmac_clkin".
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*/
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ret = dev_read_string_index(parent->dev, "clock-output-names",
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parent->id, &clock_output_name);
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if (ret < 0)
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return -ENODATA;
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/* If this is "gmac_clkin", switch to the external clock input */
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if (!strcmp(clock_output_name, "gmac_clkin")) {
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debug("%s: switching RGMII to CLKIN\n", __func__);
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rk_setreg(&grf->soc_con[4], BIT(14));
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return 0;
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}
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return -EINVAL;
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}
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static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
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{
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switch (clk->id) {
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case SCLK_MAC2IO:
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return rk3328_gmac2io_set_parent(clk, parent);
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case SCLK_MAC2IO_EXT:
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return rk3328_gmac2io_ext_set_parent(clk, parent);
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case DCLK_LCDC:
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case SCLK_PDM:
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case SCLK_RTC32K:
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case SCLK_UART0:
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case SCLK_UART1:
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case SCLK_UART2:
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return 0;
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}
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debug("%s: unsupported clk %ld\n", __func__, clk->id);
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return -ENOENT;
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}
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static struct clk_ops rk3328_clk_ops = {
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.get_rate = rk3328_clk_get_rate,
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.set_rate = rk3328_clk_set_rate,
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.set_parent = rk3328_clk_set_parent,
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};
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static int rk3328_clk_probe(struct udevice *dev)
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@ -86,6 +86,9 @@
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#define SCLK_USB3OTG_SUSPEND 97
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#define SCLK_REF_USB3OTG_SRC 98
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#define SCLK_MAC2IO_SRC 99
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#define SCLK_MAC2IO 100
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#define SCLK_MAC2PHY 101
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#define SCLK_MAC2IO_EXT 102
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/* dclk gates */
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#define DCLK_LCDC 180
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@ -199,9 +202,6 @@
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#define CLK_NR_CLKS (HCLK_HDCP + 1)
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#define SCLK_MAC2IO 0
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#define SCLK_MAC2PHY 1
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#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
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/* soft-reset indices */
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