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sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD

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DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't
let PLL_VIDEO be high enough for them.

Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Icenowy Zheng 2018-10-28 14:26:12 -07:00 • committed by Jagan Teki
parent e6b16e7852
commit 7d121a8ea4
2 changed files with 18 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/mach-sunxi/clock_sun6i.c
View file

@ -149,7 +149,11 @@ void clock_set_pll3(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
#ifdef CONFIG_SUNXI_DE2
const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */
#else
const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
#endif
if (clk == 0) {
clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);

22
drivers/video/sunxi/lcdc.c
View file

@ -211,11 +211,17 @@ void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
int *clk_div, int *clk_double, bool is_composite)
{
int value, n, m, min_m, max_m, diff;
int value, n, m, min_m, max_m, diff, step;
int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
int best_double = 0;
bool use_mipi_pll = false;
#ifdef CONFIG_SUNXI_DE2
step = 6000;
#else
step = 3000;
#endif
if (tcon == 0) {
#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2)
min_m = 6;
@ -237,10 +243,10 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
*/
for (m = min_m; m <= max_m; m++) {
#ifndef CONFIG_SUNXI_DE2
n = (m * dotclock) / 3000;
n = (m * dotclock) / step;
if ((n >= 9) && (n <= 127)) {
value = (3000 * n) / m;
value = (step * n) / m;
diff = dotclock - value;
if (diff < best_diff) {
best_diff = diff;
@ -256,9 +262,9 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
#endif
/* No double clock on DE2 */
n = (m * dotclock) / 6000;
n = (m * dotclock) / (step * 2);
if ((n >= 9) && (n <= 127)) {
value = (6000 * n) / m;
value = (step * 2 * n) / m;
diff = dotclock - value;
if (diff < best_diff) {
best_diff = diff;
@ -287,11 +293,11 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
} else
#endif
{
clock_set_pll3(best_n * 3000000);
debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
clock_set_pll3(best_n * step * 1000);
debug("dotclock: %dkHz = %dkHz: (%d * %dkHz * %d) / %d\n",
dotclock,
(best_double + 1) * clock_get_pll3() / best_m / 1000,
best_double + 1, best_n, best_m);
best_double + 1, step, best_n, best_m);
}
if (tcon == 0) {