From ac12c61909273be0806afae42963f426925ad111 Mon Sep 17 00:00:00 2001 From: David Abdurachmanov Date: Tue, 9 Apr 2019 12:42:46 +0200 Subject: [PATCH 1/9] riscv: set CONFIG_SYS_BOOTM_LEN to SZ_64M After updating Fedora/RISCV kernel to 5.1-rc3+ the size increased above the current threshold. Looking into HiKey, Dragonboards, etc. seems that SZ_64M is a popular option. This sucessfully boots Fedora/RISCV with 5.1-rc3+ kernel on QEMU 4.0 (master) with OpenSBI -> U-Boot (S-mode) [extlinux] -> Kernel setup. Signed-off-by: David Abdurachmanov Reviewed-by: Anup Patel Reviewed-by: Lukas Auer Reviewed-by: Bin Meng --- include/configs/qemu-riscv.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 2588c5a0b2..22a5cd7365 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -15,7 +15,7 @@ #define CONFIG_SYS_MALLOC_LEN SZ_8M -#define CONFIG_SYS_BOOTM_LEN SZ_16M +#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 @@ -41,11 +41,11 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x82000000\0" \ - "scriptaddr=0x82100000\0" \ - "pxefile_addr_r=0x82200000\0" \ - "ramdisk_addr_r=0x82300000\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ BOOTENV #endif /* __CONFIG_H */ From 081c660201f7567c4fc000e4d758b5ab9f0e8db4 Mon Sep 17 00:00:00 2001 From: David Abdurachmanov Date: Tue, 9 Apr 2019 12:42:47 +0200 Subject: [PATCH 2/9] riscv: qemu-riscv.h: define CONFIG_PREBOOT (enables extlinux) - Set fdt_addr variable, which is needed for extlinux to find FDT. Otherwise booting kernel using extlinux results in missing FDT. - Also run fdt addr with FDT address so that fdt commands would work out of the box in U-Boot prompt. This is successfully used by Fedora/RISCV with 5.1-rc3+ kernel using OpenSBI -> U-Boot (S-mode) [extlinux] -> Kernel setup. Signed-off-by: David Abdurachmanov Reviewed-by: Anup Patel Reviewed-by: Lukas Auer Reviewed-by: Bin Meng --- include/configs/qemu-riscv.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 22a5cd7365..b7110edebc 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -48,4 +48,8 @@ "ramdisk_addr_r=0x88300000\0" \ BOOTENV +#define CONFIG_PREBOOT \ + "setenv fdt_addr ${fdtcontroladdr};" \ + "fdt addr ${fdtcontroladdr};" + #endif /* __CONFIG_H */ From 8aa278df0a338dfc05c731589051ab80373925c5 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Thu, 11 Apr 2019 06:52:12 +0000 Subject: [PATCH 3/9] riscv: qemu: Use correct SYS_TEXT_BASE for S-mode on 32bit system For 32bit system, the OpenSBI (or BBL) will jump to 0x80400000 address in S-mode whereas for 64bit system it will jump to 0x80200000 address in S-mode. Currently, the S-mode U-Boot sets SYS_TEXT_BASE to 0x80200000 for both 32bit and 64bit system. This breaks S-mode U-Boot for 32bit system. This patch sets different SYS_TEXT_BASE for 32bit and 64bit system so that S-mode U-Boot works fine for both. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Lukas Auer Tested-by: Karsten Merker --- board/emulation/qemu-riscv/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index cf057e7de6..20ea6dc59b 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -14,7 +14,8 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0x80000000 if !RISCV_SMODE - default 0x80200000 if RISCV_SMODE + default 0x80200000 if RISCV_SMODE && ARCH_RV64I + default 0x80400000 if RISCV_SMODE && ARCH_RV32I config BOARD_SPECIFIC_OPTIONS # dummy def_bool y From bdce38965e79143ed58bf1c6d39c650ff3dfefd1 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Tue, 30 Apr 2019 13:49:33 +0800 Subject: [PATCH 4/9] riscv: Introduce CONFIG_XIP to support booting from flash When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Lukas Auer Reviewed-by: Bin Meng --- arch/riscv/Kconfig | 7 +++++++ arch/riscv/cpu/cpu.c | 2 ++ arch/riscv/cpu/start.S | 6 ++++++ arch/riscv/include/asm/global_data.h | 2 ++ arch/riscv/lib/asm-offsets.c | 2 ++ arch/riscv/lib/smp.c | 2 ++ 6 files changed, 21 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ae8ff7b765..362f3cdc65 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -162,6 +162,13 @@ config SBI_IPI default y if RISCV_SMODE depends on SMP +config XIP + bool "XIP mode" + help + XIP (eXecute In Place) is a method for executing code directly + from a NOR flash memory without copying the code to ram. + Say yes here if U-Boot boots from flash directly. + config STACK_SIZE_SHIFT int default 13 diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c32de8a4c3..0cfd7d61a7 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -16,6 +16,7 @@ * before the bss section is available. */ phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; /* @@ -23,6 +24,7 @@ u32 hart_lottery __attribute__((section(".data"))) = 0; * finished initialization of global data. */ u32 available_harts_lock = 1; +#endif static inline bool supports_extension(char ext) { diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a4433fbd6b..3402d09a05 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -98,6 +98,7 @@ call_board_init_f_0: mv sp, a0 #endif +#ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts * wait for initialization to complete. @@ -106,6 +107,9 @@ call_board_init_f_0: li s2, 1 amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init +#else + bnez tp, secondary_hart_loop +#endif la t0, prior_stage_fdt_address SREG s1, 0(t0) @@ -115,6 +119,7 @@ call_board_init_f_0: /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp) +#ifndef CONFIG_XIP la t0, available_harts_lock fence rw, w amoswap.w zero, zero, 0(t0) @@ -141,6 +146,7 @@ wait_for_gd_init: * secondary_hart_loop. */ bnez s2, secondary_hart_loop +#endif /* Enable cache */ jal icache_enable diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index dffcd45bf0..b74bd7e738 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -27,7 +27,9 @@ struct arch_global_data { #ifdef CONFIG_SMP struct ipi_data ipi[CONFIG_NR_CPUS]; #endif +#ifndef CONFIG_XIP ulong available_harts; +#endif }; #include diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index f998402bd1..4fa4fd3714 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -14,7 +14,9 @@ int main(void) { DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); +#ifndef CONFIG_XIP DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); +#endif return 0; } diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index caa292ccd2..cc66f15567 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi) continue; } +#ifndef CONFIG_XIP /* skip if hart is not available */ if (!(gd->arch.available_harts & (1 << reg))) continue; +#endif gd->arch.ipi[reg].addr = ipi->addr; gd->arch.ipi[reg].arg0 = ipi->arg0; From e7e47f6391d13bd7e6d5dd705c548d0260a88c55 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Thu, 9 May 2019 10:20:19 +0800 Subject: [PATCH 5/9] riscv: configs: Support AE350 SMP booting from flash flow Add two defconfigs to support AE350 SMP booting from flash. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- board/AndesTech/ax25-ae350/MAINTAINERS | 2 ++ configs/ae350_rv32_xip_defconfig | 37 +++++++++++++++++++++++++ configs/ae350_rv64_xip_defconfig | 38 ++++++++++++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 configs/ae350_rv32_xip_defconfig create mode 100644 configs/ae350_rv64_xip_defconfig diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS b/board/AndesTech/ax25-ae350/MAINTAINERS index b0a99e4ac4..feed5d1298 100644 --- a/board/AndesTech/ax25-ae350/MAINTAINERS +++ b/board/AndesTech/ax25-ae350/MAINTAINERS @@ -5,3 +5,5 @@ F: board/AndesTech/ax25-ae350/ F: include/configs/ax25-ae350.h F: configs/ae350_rv32_defconfig F: configs/ae350_rv64_defconfig +F: configs/ae350_rv32_xip_defconfig +F: configs/ae350_rv64_xip_defconfig diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig new file mode 100644 index 0000000000..76534f2eef --- /dev/null +++ b/configs/ae350_rv32_xip_defconfig @@ -0,0 +1,37 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_XIP=y +CONFIG_TARGET_AX25_AE350=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig new file mode 100644 index 0000000000..f7f2925f3a --- /dev/null +++ b/configs/ae350_rv64_xip_defconfig @@ -0,0 +1,38 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_XIP=y +CONFIG_TARGET_AX25_AE350=y +CONFIG_ARCH_RV64I=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_64" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y From f9281b8905d50d1f284df92f53534ffb8d2558a8 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Tue, 30 Apr 2019 13:49:35 +0800 Subject: [PATCH 6/9] riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled This patch will fix prior_stage_fdt_address write failure problem, when AE350 boots from flash. When AE350 boots from flash, prior_stage_fdt_address will be flash address, we shall avoid it to be written. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/cpu/cpu.c | 2 ++ arch/riscv/cpu/start.S | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 0cfd7d61a7..e9a8b437ed 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -15,7 +15,9 @@ * The variables here must be stored in the data section since they are used * before the bss section is available. */ +#ifdef CONFIG_OF_PRIOR_STAGE phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#endif #ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 3402d09a05..60ac8c621e 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -111,8 +111,10 @@ call_board_init_f_0: bnez tp, secondary_hart_loop #endif +#ifdef CONFIG_OF_PRIOR_STAGE la t0, prior_stage_fdt_address SREG s1, 0(t0) +#endif jal board_init_f_init_reserve From a3caa846278c15fba4fe93c4f1d53c13b49a6aa0 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Tue, 30 Apr 2019 13:49:36 +0800 Subject: [PATCH 7/9] riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when boots from ram When AE350 boots from ram, use CONFIG_OF_PRIOR_STAGE instead of CONFIG_OF_BOARD. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 2f759e4d2c..a31027016b 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_BOARD=y +CONFIG_OF_PRIOR_STAGE=y CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 287769d5b1..d425252ec8 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_BOARD=y +CONFIG_OF_PRIOR_STAGE=y CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y From d8fc1ef2f0b4b759181fe5fa3c5c64af538cef85 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Tue, 30 Apr 2019 13:49:37 +0800 Subject: [PATCH 8/9] riscv: configs: AE350 will use CONFIG_OF_SEPARATE when boots from flash When AE350 boots from flash, use CONFIG_OF_SEPARATE instead of CONFIG_OF_BOARD. Also remove unused code about prior_stage_fdt_address. And modify CONFIG_SYS_FDT_BASE as flash address. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- board/AndesTech/ax25-ae350/ax25-ae350.c | 4 ---- configs/ae350_rv32_xip_defconfig | 2 +- configs/ae350_rv64_xip_defconfig | 2 +- include/configs/ax25-ae350.h | 2 +- 4 files changed, 3 insertions(+), 7 deletions(-) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index d343453f22..3d65ce7b75 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -67,10 +67,6 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) void *board_fdt_blob_setup(void) { - void **ptr = (void *)&prior_stage_fdt_address; - if (fdt_magic(*ptr) == FDT_MAGIC) - return (void *)*ptr; - return (void *)CONFIG_SYS_FDT_BASE; } diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 76534f2eef..07f1ecc2fc 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_BOARD=y +CONFIG_OF_SEPARATE=y CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index f7f2925f3a..28afd81fc8 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -16,7 +16,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_BOARD=y +CONFIG_OF_SEPARATE=y CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index 395f3a442d..a4037f33dd 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -40,7 +40,7 @@ #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* DT blob (fdt) address */ -#define CONFIG_SYS_FDT_BASE 0x000f0000 +#define CONFIG_SYS_FDT_BASE 0x800f0000 /* * Physical Memory Map From 3cedc97479ff44cdc00485de7517a833e3dfb630 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Mon, 6 May 2019 17:49:39 -0700 Subject: [PATCH 9/9] RISCV: image: Add booti support This patch adds booti support for RISC-V Linux kernel. The existing bootm method will also continue to work as it is. It depends on the following kernel patch which adds the header to the flat Image. Gzip compressed Image (Image.gz) support is not enabled with this patch. https://patchwork.kernel.org/patch/10925543/ Tested on HiFive Unleashed and QEMU. Signed-off-by: Atish Patra Reviewed-by: Tom Rini Tested-by: Karsten Merker Reviewed-by: Marek Vasut --- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/image.c | 55 +++++++++++++++++++++++++++++++++++++++++ cmd/Kconfig | 2 +- cmd/booti.c | 8 ++++-- 4 files changed, 63 insertions(+), 3 deletions(-) create mode 100644 arch/riscv/lib/image.c diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 1c332db436..6ae6ebbeaf 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -7,6 +7,7 @@ # Rick Chen, Andes Technology Corporation obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-$(CONFIG_RISCV_RDTIME) += rdtime.o diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c new file mode 100644 index 0000000000..d063beb7df --- /dev/null +++ b/arch/riscv/lib/image.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * Authors: + * Atish Patra + * Based on arm/lib/image.c + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* ASCII version of "RISCV" defined in Linux kernel */ +#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952 + +struct linux_image_h { + uint32_t code0; /* Executable code */ + uint32_t code1; /* Executable code */ + uint64_t text_offset; /* Image load offset */ + uint64_t image_size; /* Effective Image size */ + uint64_t res1; /* reserved */ + uint64_t res2; /* reserved */ + uint64_t res3; /* reserved */ + uint64_t magic; /* Magic number */ + uint32_t res4; /* reserved */ + uint32_t res5; /* reserved */ +}; + +int booti_setup(ulong image, ulong *relocated_addr, ulong *size, + bool force_reloc) +{ + struct linux_image_h *lhdr; + + lhdr = (struct linux_image_h *)map_sysmem(image, 0); + + if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) { + puts("Bad Linux RISCV Image magic!\n"); + return -EINVAL; + } + + if (lhdr->image_size == 0) { + puts("Image lacks image_size field, error!\n"); + return -EINVAL; + } + *size = lhdr->image_size; + *relocated_addr = gd->ram_base + lhdr->text_offset; + + unmap_sysmem(lhdr); + + return 0; +} diff --git a/cmd/Kconfig b/cmd/Kconfig index 069e0ea730..4e11e0f404 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -223,7 +223,7 @@ config CMD_BOOTZ config CMD_BOOTI bool "booti" - depends on ARM64 + depends on ARM64 || RISCV default y help Boot an AArch64 Linux Kernel image from memory. diff --git a/cmd/booti.c b/cmd/booti.c index 04353b68ec..c36b0235df 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -77,7 +77,11 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) bootm_disable_interrupts(); images.os.os = IH_OS_LINUX; +#ifdef CONFIG_RISCV_SMODE + images.os.arch = IH_ARCH_RISCV; +#elif CONFIG_ARM64 images.os.arch = IH_ARCH_ARM64; +#endif ret = do_bootm_states(cmdtp, flag, argc, argv, #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH BOOTM_STATE_RAMDISK | @@ -92,7 +96,7 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_LONGHELP static char booti_help_text[] = "[addr [initrd[:size]] [fdt]]\n" - " - boot arm64 Linux Image stored in memory\n" + " - boot Linux 'Image' stored at 'addr'\n" "\tThe argument 'initrd' is optional and specifies the address\n" "\tof an initrd in memory. The optional parameter ':size' allows\n" "\tspecifying the size of a RAW initrd.\n" @@ -107,5 +111,5 @@ static char booti_help_text[] = U_BOOT_CMD( booti, CONFIG_SYS_MAXARGS, 1, do_booti, - "boot arm64 Linux Image image from memory", booti_help_text + "boot Linux kernel 'Image' format from memory", booti_help_text );