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board: freescale: ls1012a: Enable secure DDR on LS1012A platforms
PPA binary needs to be relocated on secure DDR, hence marking out a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag is set Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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5 changed files with 91 additions and 0 deletions
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@ -192,6 +192,9 @@
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#define GICD_BASE 0x01401000
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#define GICC_BASE 0x01402000
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#elif defined(CONFIG_ARCH_LS1046A)
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#define CONFIG_SYS_FMAN_V3
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#define CONFIG_SYS_NUM_FMAN 1
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@ -85,3 +85,32 @@ int ft_board_setup(void *blob, bd_t *bd)
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return 0;
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}
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void dram_init_banksize(void)
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{
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/*
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* gd->arch.secure_ram tracks the location of secure memory.
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* It was set as if the memory starts from 0.
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* The address needs to add the offset of its bank.
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*/
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
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gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
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gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
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gd->bd->bi_dram[1].size = gd->ram_size -
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CONFIG_SYS_DDR_BLOCK1_SIZE;
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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gd->arch.secure_ram = gd->bd->bi_dram[1].start +
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gd->arch.secure_ram -
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CONFIG_SYS_DDR_BLOCK1_SIZE;
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gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
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#endif
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} else {
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gd->bd->bi_dram[0].size = gd->ram_size;
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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gd->arch.secure_ram = gd->bd->bi_dram[0].start +
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gd->arch.secure_ram;
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gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
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#endif
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}
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}
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@ -159,3 +159,32 @@ int ft_board_setup(void *blob, bd_t *bd)
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return 0;
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}
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#endif
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void dram_init_banksize(void)
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{
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/*
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* gd->arch.secure_ram tracks the location of secure memory.
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* It was set as if the memory starts from 0.
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* The address needs to add the offset of its bank.
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*/
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
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gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
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gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
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gd->bd->bi_dram[1].size = gd->ram_size -
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CONFIG_SYS_DDR_BLOCK1_SIZE;
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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gd->arch.secure_ram = gd->bd->bi_dram[1].start +
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gd->arch.secure_ram -
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CONFIG_SYS_DDR_BLOCK1_SIZE;
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gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
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#endif
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} else {
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gd->bd->bi_dram[0].size = gd->ram_size;
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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gd->arch.secure_ram = gd->bd->bi_dram[0].start +
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gd->arch.secure_ram;
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gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
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#endif
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}
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}
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@ -159,3 +159,32 @@ int ft_board_setup(void *blob, bd_t *bd)
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return 0;
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}
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void dram_init_banksize(void)
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{
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/*
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* gd->secure_ram tracks the location of secure memory.
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* It was set as if the memory starts from 0.
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* The address needs to add the offset of its bank.
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*/
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
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gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
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gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
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gd->bd->bi_dram[1].size = gd->ram_size -
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CONFIG_SYS_DDR_BLOCK1_SIZE;
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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gd->arch.secure_ram = gd->bd->bi_dram[1].start +
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gd->arch.secure_ram -
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CONFIG_SYS_DDR_BLOCK1_SIZE;
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gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
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#endif
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} else {
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gd->bd->bi_dram[0].size = gd->ram_size;
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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gd->arch.secure_ram = gd->bd->bi_dram[0].start +
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gd->arch.secure_ram;
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gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
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#endif
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}
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}
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@ -29,6 +29,7 @@
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */
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