mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 21:21:37 +00:00
mpc83xx: Cleanup usage of LBC constants
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
parent
2fef402097
commit
7d6a098219
26 changed files with 543 additions and 401 deletions
|
@ -50,8 +50,10 @@ void lbc_sdram_init(void);
|
|||
#define BR_MSEL 0x000000E0
|
||||
#define BR_MSEL_SHIFT 5
|
||||
#define BR_MS_GPCM 0x00000000 /* GPCM */
|
||||
#if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360)
|
||||
#define BR_MS_FCM 0x00000020 /* FCM */
|
||||
#ifdef CONFIG_MPC83xx
|
||||
#endif
|
||||
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360)
|
||||
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
|
||||
#elif defined(CONFIG_MPC85xx)
|
||||
#define BR_MS_SDRAM 0x00000000 /* SDRAM */
|
||||
|
@ -138,8 +140,10 @@ void lbc_sdram_init(void);
|
|||
#define OR_GPCM_EHTR_SHIFT 1
|
||||
#define OR_GPCM_EHTR_CLEAR 0x00000000
|
||||
#define OR_GPCM_EHTR_SET 0x00000002
|
||||
#if !defined(CONFIG_MPC8308)
|
||||
#define OR_GPCM_EAD 0x00000001
|
||||
#define OR_GPCM_EAD_SHIFT 0
|
||||
#endif
|
||||
|
||||
/* helpers to convert values into an OR address mask (GPCM mode) */
|
||||
#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
|
||||
|
@ -196,8 +200,10 @@ void lbc_sdram_init(void);
|
|||
#define OR_SDRAM_XAM_SHIFT 13
|
||||
#define OR_SDRAM_COLS 0x00001C00
|
||||
#define OR_SDRAM_COLS_SHIFT 10
|
||||
#define OR_SDRAM_MIN_COLS 7
|
||||
#define OR_SDRAM_ROWS 0x000001C0
|
||||
#define OR_SDRAM_ROWS_SHIFT 6
|
||||
#define OR_SDRAM_MIN_ROWS 9
|
||||
#define OR_SDRAM_PMSEL 0x00000020
|
||||
#define OR_SDRAM_PMSEL_SHIFT 5
|
||||
#define OR_SDRAM_EAD 0x00000001
|
||||
|
|
|
@ -159,11 +159,13 @@
|
|||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
|
||||
BR_MS_GPCM | BR_V)
|
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
|
||||
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
|
||||
OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX |\
|
||||
OR_GPCM_EHTR | OR_GPCM_EAD)
|
||||
OR_GPCM_XACS | OR_GPCM_SCY_15 |\
|
||||
OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
|
||||
OR_GPCM_EAD)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512
|
||||
|
@ -180,14 +182,14 @@
|
|||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE 0xE0600000
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | (2<<BR_DECC_SHIFT) |\
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
|
||||
BR_PS_8 | BR_MS_FCM | BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | OR_FCM_BCTLD | OR_FCM_CST |\
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
|
||||
OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
|
||||
OR_FCM_TRLX | OR_FCM_EHTR)
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
|
|
|
@ -239,19 +239,18 @@
|
|||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (\
|
||||
CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\
|
||||
(2 << BR_PS_SHIFT) /* 16 bit port size */ |\
|
||||
BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD)
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
/* 127 64KB sectors and 8 8KB top sectors per device */
|
||||
|
@ -264,12 +263,13 @@
|
|||
* NAND Flash on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
|
||||
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* 8 bit port */ \
|
||||
| BR_DECC_CHK_GEN /* Use HW ECC */ \
|
||||
| BR_PS_8 /* 8 bit Port */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* length 32K */ \
|
||||
#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
|
@ -283,9 +283,22 @@
|
|||
|
||||
#ifdef CONFIG_VSC7385_ENET
|
||||
#define CONFIG_TSEC2
|
||||
/* VSC7385 Base address on CS2 */
|
||||
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
|
||||
#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
|
||||
#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
|
||||
| BR_PS_8 /* 8-bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
/* 0xF0000801 */
|
||||
#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_SETA \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET)
|
||||
/* 0xFFFE09FF */
|
||||
/* Access window base at VSC7385 base */
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
|
||||
/* Access window size 128K */
|
||||
|
|
|
@ -205,9 +205,10 @@
|
|||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
|
||||
|
||||
#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit port */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_NOR_OR_PRELIM (0xFF800000 /* 8 MByte */ \
|
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_9 \
|
||||
| OR_GPCM_EHTR \
|
||||
|
@ -215,7 +216,8 @@
|
|||
/* 0xFF006FF7 TODO SLOW 16 MB flash size */
|
||||
/* window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */
|
||||
/* 16 MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
|
||||
|
@ -271,14 +273,16 @@
|
|||
#define CONFIG_CMD_NAND 1
|
||||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
|
||||
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
|
||||
|
||||
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_DECC_CHK_GEN /* Use HW ECC */ \
|
||||
| BR_PS_8 /* 8 bit port */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM \
|
||||
(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
|
@ -300,31 +304,57 @@
|
|||
#endif
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
|
||||
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
|
||||
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
|
||||
|
||||
/* local bus read write buffer mapping */
|
||||
#define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
|
||||
/* local bus write LED / read status buffer (BCSR) mapping */
|
||||
#define CONFIG_SYS_BCSR_ADDR 0xFA000000
|
||||
#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
|
||||
/* map at 0xFA000000 on LCS3 */
|
||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
|
||||
| BR_PS_8 /* 8 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
/* 0xFA000801 */
|
||||
#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xFFFF8FF7 */
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
|
||||
/* Vitesse 7385 */
|
||||
|
||||
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
|
||||
|
||||
#ifdef CONFIG_VSC7385_ENET
|
||||
|
||||
/* VSC7385 Base address */
|
||||
#define CONFIG_SYS_BR2_PRELIM 0xf0000801
|
||||
/* VSC7385, 128K bytes*/
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff
|
||||
/* VSC7385 Base address on LCS2 */
|
||||
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
|
||||
#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
|
||||
| BR_PS_8 /* 8 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_SETA \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xFFFE09FF */
|
||||
|
||||
/* Access window base at VSC7385 base */
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
|
||||
/* Access window size 128K */
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
@ -229,20 +229,21 @@
|
|||
|
||||
/* Window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
|
||||
|
||||
#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit port */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
|
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD)
|
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
/* 127 64KB sectors and 8 8KB top sectors per device */
|
||||
|
@ -273,7 +274,8 @@
|
|||
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
|
||||
#define CONFIG_CMD_NAND 1
|
||||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
|
||||
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
|
||||
|
@ -282,11 +284,12 @@
|
|||
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
|
||||
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_DECC_CHK_GEN /* Use HW ECC */ \
|
||||
| BR_PS_8 /* 8 bit port */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM \
|
||||
(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
|
@ -308,7 +311,7 @@
|
|||
#endif
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
|
||||
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
|
||||
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
|
||||
|
|
|
@ -185,84 +185,28 @@
|
|||
|
||||
/* Window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit port */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
|
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xFE006FF7 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
|
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus
|
||||
*/
|
||||
#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
|
||||
|
||||
#ifdef CONFIG_SYS_LB_SDRAM
|
||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base addr */
|
||||
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
|
||||
|
||||
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
|
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM.
|
||||
* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
|
||||
*
|
||||
* For BR2, need:
|
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
|
||||
* port size = 32-bits = BR2[19:20] = 11
|
||||
* no parity checking = BR2[21:22] = 00
|
||||
* SDRAM for MSEL = BR2[24:26] = 011
|
||||
* Valid = BR[31] = 1
|
||||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
|
||||
*
|
||||
* CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
|
||||
* the top 17 bits of BR2.
|
||||
*/
|
||||
|
||||
/*Port size=32bit, MSEL=SDRAM */
|
||||
#define CONFIG_SYS_BR2_PRELIM 0xf0001861
|
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
|
||||
*
|
||||
* For OR2, need:
|
||||
* 64MB mask for AM, OR2[0:7] = 1111 1100
|
||||
* XAM, OR2[17:18] = 11
|
||||
* 9 columns OR2[19-21] = 010
|
||||
* 13 rows OR2[23-25] = 100
|
||||
* EAD set for extra time OR[31] = 1
|
||||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xfc006901
|
||||
|
||||
/* LB sdram refresh timer, about 6us */
|
||||
#define CONFIG_SYS_LBC_LSRT 0x32000000
|
||||
/* LB refresh timer prescal, 266MHz/32 */
|
||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000
|
||||
|
||||
#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Windows to access PIB via local bus
|
||||
*/
|
||||
/* windows base 0xf8008000 */
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
|
|
|
@ -210,12 +210,22 @@
|
|||
|
||||
/* Window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit port */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
|
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xfe006ff7 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
|
||||
|
@ -228,94 +238,67 @@
|
|||
#define CONFIG_SYS_BCSR 0xF8000000
|
||||
/* Access window base at BCSR base */
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
|
||||
/* Access window size 32K */
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
|
||||
/* Port size=8bit, MSEL=GPCM */
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801)
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
|
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus
|
||||
*/
|
||||
#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
|
||||
|
||||
#ifdef CONFIG_SYS_LB_SDRAM
|
||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
|
||||
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
|
||||
|
||||
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
|
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM.
|
||||
* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
|
||||
*
|
||||
* For BR2, need:
|
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
|
||||
* port size = 32-bits = BR2[19:20] = 11
|
||||
* no parity checking = BR2[21:22] = 00
|
||||
* SDRAM for MSEL = BR2[24:26] = 011
|
||||
* Valid = BR[31] = 1
|
||||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
|
||||
*
|
||||
* CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
|
||||
* the top 17 bits of BR2.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
|
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
|
||||
*
|
||||
* For OR2, need:
|
||||
* 64MB mask for AM, OR2[0:7] = 1111 1100
|
||||
* XAM, OR2[17:18] = 11
|
||||
* 9 columns OR2[19-21] = 010
|
||||
* 13 rows OR2[23-25] = 100
|
||||
* EAD set for extra time OR[31] = 1
|
||||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xfc006901
|
||||
|
||||
/* LB sdram refresh timer, about 6us */
|
||||
#define CONFIG_SYS_LBC_LSRT 0x32000000
|
||||
/* LB refresh timer prescal, 266MHz/32 */
|
||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000
|
||||
|
||||
#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
|
||||
|
||||
#endif
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xFFFFE9F7 */
|
||||
|
||||
/*
|
||||
* Windows to access PIB via local bus
|
||||
*/
|
||||
/* windows base 0xf8008000 */
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000
|
||||
/* windows size 64KB */
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f
|
||||
/* PIB window base 0xF8008000 */
|
||||
#define CONFIG_SYS_PIB_BASE 0xF8008000
|
||||
#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
|
||||
|
||||
/*
|
||||
* CS2 on Local Bus, to PIB
|
||||
*/
|
||||
/* CS2 base address at 0xf8008000 */
|
||||
#define CONFIG_SYS_BR2_PRELIM 0xf8008801
|
||||
/* size 32KB, port size 8bit, GPCM */
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xffffe9f7
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
/* 0xF8008801 */
|
||||
#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xffffe9f7 */
|
||||
|
||||
/*
|
||||
* CS3 on Local Bus, to PIB
|
||||
*/
|
||||
/* CS3 base address at 0xf8010000 */
|
||||
#define CONFIG_SYS_BR3_PRELIM 0xf8010801
|
||||
/* size 32KB, port size 8bit, GPCM */
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xffffe9f7
|
||||
#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
|
||||
CONFIG_SYS_PIB_WINDOW_SIZE) \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
/* 0xF8010801 */
|
||||
#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xffffe9f7 */
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
|
|
|
@ -178,21 +178,23 @@
|
|||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
|
||||
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
||||
(2 << BR_PS_SHIFT) | /* 16 bit port */ \
|
||||
BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
|
||||
/* window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
|
||||
|
@ -215,11 +217,19 @@
|
|||
#define CONFIG_SYS_BCSR 0xE2400000
|
||||
/* Access window base at BCSR base */
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
|
||||
/* Access window size 32K */
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
|
||||
/* Port-size=8bit, MSEL=GPCM */
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801)
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
/* 0x00000801 */
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_CLEAR \
|
||||
| OR_GPCM_EHTR_CLEAR)
|
||||
/* 0xFFFFE8F0 */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
|
||||
|
@ -263,15 +273,15 @@
|
|||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
|
||||
*
|
||||
* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
|
||||
* FIXME: the top 17 bits of BR2.
|
||||
*/
|
||||
|
||||
/* Port-size=32bit, MSEL=SDRAM */
|
||||
#define CONFIG_SYS_BR2_PRELIM 0xF0001861
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
|
||||
| BR_PS_32 /* 32-bit port */ \
|
||||
| BR_MS_SDRAM /* MSEL = SDRAM */ \
|
||||
| BR_V) /* Valid */
|
||||
/* 0xF0001861 */
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
|
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
|
||||
|
@ -287,7 +297,12 @@
|
|||
* 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xFC006901
|
||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
|
||||
| OR_SDRAM_XAM \
|
||||
| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
|
||||
| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
|
||||
| OR_SDRAM_EAD)
|
||||
/* 0xFC006901 */
|
||||
|
||||
/* LB sdram refresh timer, about 6us */
|
||||
#define CONFIG_SYS_LBC_LSRT 0x32000000
|
||||
|
|
|
@ -235,7 +235,6 @@ boards, we say we have two, but don't display a message if we find only one. */
|
|||
#define CONFIG_SYS_FLASH_BANKS_LIST \
|
||||
{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
|
||||
#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
|
||||
#define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
|
||||
|
||||
/* Vitesse 7385 */
|
||||
|
@ -256,19 +255,21 @@ boards, we say we have two, but don't display a message if we find only one. */
|
|||
|
||||
/* Flash */
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| BR_PS_16 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \
|
||||
| (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
|
||||
|
||||
/* Vitesse 7385 */
|
||||
|
||||
|
@ -276,14 +277,17 @@ boards, we say we have two, but don't display a message if we find only one. */
|
|||
|
||||
#ifdef CONFIG_VSC7385_ENET
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_SETA \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
|
||||
|
@ -294,14 +298,17 @@ boards, we say we have two, but don't display a message if we find only one. */
|
|||
/* LED */
|
||||
|
||||
#define CONFIG_SYS_LED_BASE 0xF9000000
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_9 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
|
||||
/* Compact Flash */
|
||||
|
|
|
@ -207,19 +207,20 @@
|
|||
|
||||
/* Window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit port */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
|
||||
| OR_UPM_XAM \
|
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
|
@ -233,11 +234,21 @@
|
|||
#define CONFIG_SYS_BCSR 0xF8000000
|
||||
/* Access window base at BCSR base */
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
|
||||
|
||||
/* Port size=8bit, MSEL=GPCM */
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801)
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xFFFFE9F7 */
|
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus
|
||||
|
@ -249,7 +260,7 @@
|
|||
|
||||
#ifdef CONFIG_SYS_LB_SDRAM
|
||||
#define CONFIG_SYS_LBLAWBAR2 0
|
||||
#define CONFIG_SYS_LBLAWAR2 0x80000019 /* 64MB */
|
||||
#define CONFIG_SYS_LBLAWAR2 (LBLAWAR_EN | LBLAWAR_64MB)
|
||||
|
||||
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
|
||||
/*
|
||||
|
@ -266,7 +277,8 @@
|
|||
* xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_BR2 0x00001861 /*Port size=32bit, MSEL=SDRAM */
|
||||
/* Port size=32bit, MSEL=DRAM */
|
||||
#define CONFIG_SYS_BR2 (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */
|
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
|
||||
|
@ -282,7 +294,12 @@
|
|||
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_OR2 0xfc006901
|
||||
#define CONFIG_SYS_OR2 (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
|
||||
| OR_SDRAM_XAM \
|
||||
| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
|
||||
| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
|
||||
| OR_SDRAM_EAD)
|
||||
/* 0xFC006901 */
|
||||
|
||||
/* LB sdram refresh timer, about 6us */
|
||||
#define CONFIG_SYS_LBC_LSRT 0x32000000
|
||||
|
@ -303,22 +320,54 @@
|
|||
#endif
|
||||
|
||||
/*
|
||||
* Windows to access PIB via local bus
|
||||
* Windows to access Platform I/O Boards (PIB) via local bus
|
||||
*/
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */
|
||||
#define CONFIG_SYS_PIB_BASE 0xF8008000
|
||||
#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
|
||||
|
||||
/* [RFC] This LBLAW only covers the 2nd window (CS5) */
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM \
|
||||
CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
|
||||
/*
|
||||
* CS4 on Local Bus, to PIB
|
||||
*/
|
||||
#define CONFIG_SYS_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
|
||||
#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
|
||||
/* CS4 base address at 0xf8008000 */
|
||||
#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_PIB_BASE \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
/* 0xF8008801 */
|
||||
#define CONFIG_SYS_OR4_PRELIM (OR_AM_32KB \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xffffe9f7 */
|
||||
|
||||
/*
|
||||
* CS5 on Local Bus, to PIB
|
||||
*/
|
||||
#define CONFIG_SYS_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
|
||||
#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
|
||||
/* CS5 base address at 0xf8010000 */
|
||||
#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_PIB_BASE + \
|
||||
CONFIG_SYS_PIB_WINDOW_SIZE) \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
/* 0xF8010801 */
|
||||
#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PIB_BASE \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xffffe9f7 */
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
|
|
|
@ -198,19 +198,20 @@
|
|||
|
||||
/* Window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit port */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
|
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
|
@ -228,11 +229,20 @@
|
|||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */
|
||||
/*
|
||||
* [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB
|
||||
* ... What's correct?
|
||||
*/
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
|
||||
|
||||
/* Port size 8 bit, UPMA */
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | 0x00000881)
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xfc000001
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_UPMA \
|
||||
| BR_V)
|
||||
/* 0x60000881 */
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD)
|
||||
/* 0xFC000001 */
|
||||
|
||||
/*
|
||||
* Fujitsu MB86277 (MINT) graphics controller
|
||||
|
@ -240,12 +250,16 @@
|
|||
#define CONFIG_SYS_VIDEO_BASE 0x70000000
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
|
||||
|
||||
/* Port size 32 bit, UPMB */
|
||||
/* PS=11, UPMB */
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE | 0x000018a1)
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \
|
||||
| BR_PS_32 \
|
||||
| BR_MS_UPMB \
|
||||
| BR_V)
|
||||
/* 0x000018a1 */
|
||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD)
|
||||
/* 0xFC000001 */
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
|
|
|
@ -243,19 +243,20 @@
|
|||
|
||||
/* Window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit port */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
|
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xFE000FF7 */
|
||||
|
||||
|
@ -272,11 +273,22 @@
|
|||
#define CONFIG_SYS_BCSR 0xF8000000
|
||||
/* Access window base at BCSR base */
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
|
||||
/* Port size=8bit, MSEL=GPCM */
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
/* 0xF8000801 */
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xFFFFE9F7 */
|
||||
|
||||
/*
|
||||
* NAND Flash on the Local Bus
|
||||
|
@ -286,13 +298,13 @@
|
|||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
|
||||
#define CONFIG_SYS_NAND_BASE 0xE0600000
|
||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_DECC_CHK_GEN /* Use HW ECC */ \
|
||||
| BR_PS_8 /* 8 bit port */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR3_PRELIM (0xFFFF8000 /* length 32K */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
|
||||
| OR_FCM_BCTLD \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
|
@ -303,7 +315,7 @@
|
|||
/* 0xFFFF919E */
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
|
|
|
@ -275,14 +275,15 @@
|
|||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit port */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \
|
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_9 \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xFF806FF7 TODO SLOW 8 MB flash size */
|
||||
/* 0xFF800191 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
|
||||
|
@ -294,13 +295,13 @@
|
|||
/*
|
||||
* NAND Flash on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
|
||||
#define CONFIG_SYS_NAND_BASE 0xE0600000
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
|
||||
| (2 << BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 | /* 8 bit Port */ \
|
||||
| BR_MS_FCM | /* MSEL = FCM */ \
|
||||
| BR_DECC_CHK_GEN /* Use HW ECC */ \
|
||||
| BR_PS_8 /* 8 bit port */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* length 32K */ \
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
|
@ -308,7 +309,7 @@
|
|||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
|
||||
/* Vitesse 7385 */
|
||||
|
||||
|
@ -316,11 +317,24 @@
|
|||
|
||||
#ifdef CONFIG_VSC7385_ENET
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
/* 0xF0000801 */
|
||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_SETA \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xfffe09ff */
|
||||
|
||||
/* Access Base */
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
@ -103,26 +103,27 @@
|
|||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFF800000
|
||||
#define CONFIG_SYS_FLASH_SIZE 8
|
||||
#define CONFIG_SYS_FLASH_SIZE_SHIFT 3
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| BR_PS_16 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \
|
||||
| (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
|
||||
|
||||
/*
|
||||
* U-Boot memory configuration
|
||||
|
|
|
@ -151,26 +151,26 @@
|
|||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_DECC_CHK_GEN /* Use HW ECC */ \
|
||||
| BR_PS_8 /* 8 bit Port */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
|
||||
#ifdef CONFIG_NAND_SP
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
|
||||
/* NAND chip block size */
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10)
|
||||
#define NAND_CACHE_PAGES 32
|
||||
#elif defined(CONFIG_NAND_LP)
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
|
||||
| OR_FCM_PGS \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
|
@ -178,8 +178,8 @@
|
|||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 2048 /* NAND chip page size */
|
||||
/* NAND chip block size */
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
|
||||
#define NAND_CACHE_PAGES 64
|
||||
|
|
|
@ -119,13 +119,12 @@
|
|||
| OR_GPCM_SCY_5 \
|
||||
| OR_GPCM_TRLX)
|
||||
|
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
|
||||
#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
|
||||
| CONFIG_SYS_OR_TIMING_FLASH)
|
||||
|
||||
/* 1 GiB window size (2^(size + 1)) */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB)
|
||||
|
||||
/* Window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
|
|
|
@ -103,16 +103,17 @@
|
|||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
||||
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
|
||||
BR_PS_16 | /* 16 bit port size */ \
|
||||
BR_MS_GPCM | /* MSEL = GPCM */ \
|
||||
BR_V)
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
|
||||
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
||||
OR_GPCM_SCY_5 | \
|
||||
OR_GPCM_TRLX | OR_GPCM_EAD)
|
||||
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
|
||||
|
@ -123,15 +124,16 @@
|
|||
*/
|
||||
/* Window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
|
||||
(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
|
||||
BR_PS_8 | /* 8 bit port size */ \
|
||||
BR_MS_GPCM | /* MSEL = GPCM */ \
|
||||
BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
|
||||
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
||||
OR_GPCM_SCY_2 | \
|
||||
OR_GPCM_TRLX | OR_GPCM_EAD)
|
||||
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
|
|
|
@ -137,15 +137,16 @@
|
|||
* PAXE on the local bus CS3
|
||||
*/
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_512MB)
|
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
|
||||
(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
|
||||
BR_PS_8 | /* 8 bit port size */ \
|
||||
BR_MS_GPCM | /* MSEL = GPCM */ \
|
||||
BR_V)
|
||||
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
|
||||
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
||||
OR_GPCM_SCY_2 | \
|
||||
OR_GPCM_TRLX | OR_GPCM_EAD)
|
||||
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
|
||||
|
||||
/*
|
||||
* MMU Setup
|
||||
|
|
|
@ -69,8 +69,8 @@
|
|||
OR_GPCM_CSNT | \
|
||||
OR_GPCM_ACS_DIV4 | \
|
||||
OR_GPCM_SCY_2 | \
|
||||
(OR_GPCM_TRLX & \
|
||||
(~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
|
||||
OR_GPCM_TRLX_SET | \
|
||||
OR_GPCM_EHTR_CLEAR | \
|
||||
OR_GPCM_EAD)
|
||||
|
||||
/* LPXF: icache cacheable, but dcache-inhibit and guarded */
|
||||
|
|
|
@ -248,18 +248,18 @@
|
|||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE /* Flash Base addr */ \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit port */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_4 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD)
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512
|
||||
|
@ -274,11 +274,12 @@
|
|||
*/
|
||||
#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \
|
||||
| (1 << BR_PS_SHIFT) /* 8 bit port */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* length 32K */ \
|
||||
| BR_PS_8 /* 8 bit port size */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
|
||||
| OR_GPCM_SCY_5 \
|
||||
| OR_GPCM_EHTR)
|
||||
| OR_GPCM_EHTR_SET)
|
||||
/* 0xFFFF8052 */
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE
|
||||
|
@ -289,11 +290,12 @@
|
|||
*/
|
||||
#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \
|
||||
| (1 << BR_PS_SHIFT) /* 8 bit port */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR2_PRELIM (0xFFFF8000 /* length 32K */ \
|
||||
| BR_PS_8 /* 8 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \
|
||||
| OR_GPCM_SCY_4 \
|
||||
| OR_GPCM_EHTR)
|
||||
| OR_GPCM_EHTR_SET)
|
||||
/* 0xFFFF8042 */
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE
|
||||
|
|
|
@ -136,8 +136,8 @@
|
|||
/*
|
||||
* SDRAM on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */
|
||||
#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
|
||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
|
||||
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
|
@ -148,14 +148,25 @@
|
|||
#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
|
||||
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit port */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xFF806FF7 */
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
|
||||
/* window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
|
||||
|
@ -212,15 +223,15 @@
|
|||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
|
||||
*
|
||||
* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
|
||||
* FIXME: the top 17 bits of BR2.
|
||||
*/
|
||||
|
||||
/* Port-size=32bit, MSEL=SDRAM */
|
||||
#define CONFIG_SYS_BR2_PRELIM 0xF0001861
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
|
||||
| BR_PS_32 \
|
||||
| BR_MS_SDRAM \
|
||||
| BR_V)
|
||||
/* 0xF0001861 */
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
|
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
|
||||
|
@ -236,7 +247,12 @@
|
|||
* 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xFC006901
|
||||
#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
|
||||
| OR_SDRAM_XAM \
|
||||
| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
|
||||
| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
|
||||
| OR_SDRAM_EAD)
|
||||
/* 0xFC006901 */
|
||||
|
||||
/* LB sdram refresh timer, about 6us */
|
||||
#define CONFIG_SYS_LBC_LSRT 0x32000000
|
||||
|
@ -615,12 +631,15 @@
|
|||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
|
||||
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
|
||||
#define CONFIG_SYS_IBAT6L (0xF0000000 \
|
||||
/* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
|
||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
|
||||
| BATL_PP_RW \
|
||||
| BATL_MEMCOHERENCE \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
|
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_IBAT7L (0)
|
||||
#define CONFIG_SYS_IBAT7U (0)
|
||||
|
|
|
@ -70,7 +70,7 @@
|
|||
OR_GPCM_CSNT | \
|
||||
OR_GPCM_ACS_DIV4 | \
|
||||
OR_GPCM_SCY_3 | \
|
||||
OR_GPCM_TRLX)
|
||||
OR_GPCM_TRLX_SET)
|
||||
|
||||
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
|
||||
0x0000c000 | \
|
||||
|
|
|
@ -73,8 +73,8 @@
|
|||
OR_GPCM_CSNT | \
|
||||
OR_GPCM_ACS_DIV4 | \
|
||||
OR_GPCM_SCY_2 | \
|
||||
(OR_GPCM_TRLX & \
|
||||
(~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
|
||||
OR_GPCM_TRLX_SET | \
|
||||
OR_GPCM_EHTR_CLEAR | \
|
||||
OR_GPCM_EAD)
|
||||
/*
|
||||
* PINC3 on the local bus CS3
|
||||
|
@ -91,11 +91,10 @@
|
|||
|
||||
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
|
||||
OR_GPCM_CSNT | \
|
||||
(OR_GPCM_ACS_DIV2 & /* ACS = 11 */\
|
||||
(~OR_GPCM_XACS)) | /* XACS = 0 */\
|
||||
(OR_GPCM_SCY_2 & \
|
||||
(~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
|
||||
OR_GPCM_TRLX)
|
||||
OR_GPCM_ACS_DIV2 | \
|
||||
OR_GPCM_SCY_2 | \
|
||||
OR_GPCM_TRLX_SET | \
|
||||
OR_GPCM_EHTR_CLEAR)
|
||||
|
||||
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
|
||||
0x0000c000 | \
|
||||
|
|
|
@ -67,8 +67,8 @@
|
|||
OR_GPCM_CSNT | \
|
||||
OR_GPCM_ACS_DIV4 | \
|
||||
OR_GPCM_SCY_2 | \
|
||||
(OR_GPCM_TRLX & \
|
||||
(~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
|
||||
OR_GPCM_TRLX_SET | \
|
||||
OR_GPCM_EHTR_CLEAR | \
|
||||
OR_GPCM_EAD)
|
||||
/*
|
||||
* PINC2 on the local bus CS3
|
||||
|
@ -85,11 +85,10 @@
|
|||
|
||||
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \
|
||||
OR_GPCM_CSNT | \
|
||||
(OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \
|
||||
(~OR_GPCM_XACS)) | /* XACS = 0 */ \
|
||||
(OR_GPCM_SCY_2 & \
|
||||
(~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
|
||||
OR_GPCM_TRLX)
|
||||
OR_GPCM_ACS_DIV2 | \
|
||||
OR_GPCM_SCY_2 | \
|
||||
OR_GPCM_TRLX_SET | \
|
||||
OR_GPCM_EHTR_CLEAR)
|
||||
|
||||
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
|
||||
0x0000c000 | \
|
||||
|
|
|
@ -146,18 +146,19 @@
|
|||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
|
||||
|
||||
#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit */ \
|
||||
| BR_V) /* valid */
|
||||
| BR_PS_16 /* 16 bit */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV4 \
|
||||
| OR_GPCM_SCY_5 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xfe000c55 */
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
|
||||
|
@ -209,7 +210,7 @@
|
|||
| BR_MS_FCM \
|
||||
| BR_V) /* valid */
|
||||
/* 0x61000c21 */
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (0xffff8000 \
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
|
||||
| OR_FCM_BCTLD \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_2 \
|
||||
|
@ -223,7 +224,7 @@
|
|||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
|
||||
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
|
||||
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
|
||||
|
@ -233,12 +234,12 @@
|
|||
| BR_PS_8 \
|
||||
| BR_V)
|
||||
/* 0x60000801 */
|
||||
#define CONFIG_SYS_OR2_PRELIM (0xfffe0000 \
|
||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_3 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xfffe0937 */
|
||||
/* local bus read write buffer mapping SRAM@0x64000000 */
|
||||
|
@ -247,12 +248,12 @@
|
|||
| BR_V)
|
||||
/* 0x62001001 */
|
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM (0xfe000000 \
|
||||
#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xfe0009f7 */
|
||||
|
||||
|
|
|
@ -123,29 +123,56 @@
|
|||
#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
|
||||
#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
||||
(2 << BR_PS_SHIFT) | /* 16bit */ \
|
||||
BR_V) /* valid */
|
||||
BR_PS_16 | /* 16bit */ \
|
||||
BR_MS_GPCM | /* MSEL = GPCM */ \
|
||||
BR_V) /* valid */
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xffc06ff7 */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
|
||||
#else
|
||||
#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
|
||||
#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
||||
(2 << BR_PS_SHIFT) | /* 16bit */ \
|
||||
BR_V) /* valid */
|
||||
BR_PS_16 | /* 16bit */ \
|
||||
BR_MS_GPCM | /* MSEL = GPCM */ \
|
||||
BR_V) /* valid */
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xf8006ff7 */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
|
||||
#endif
|
||||
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801)
|
||||
#define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200)
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011)
|
||||
#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
|
||||
| BR_PS_32 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V)
|
||||
/* 0xF0001801 */
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
|
||||
| OR_GPCM_SETA)
|
||||
/* 0xfffc0208 */
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
|
||||
|
|
Loading…
Add table
Reference in a new issue