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[MIPS] Update <asm/addrspace.h> header
- Fix traditional KSEG names - Replace PHYSADDR with CPHYSADDR Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This commit is contained in:
Shinya Kuribayashi
Shinya Kuribayashi
parent
f0d5a6f060
commit
7daf2ebe91
8 changed files with 182 additions and 99 deletions
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@ -36,7 +36,7 @@ static int wdi_status = 0;
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#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
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#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096))
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#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096))
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void inline log_serial_char(char c){
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char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
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@ -63,7 +63,7 @@ long int initdram(int board_type)
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/* Can't probe for RAM size unless we are running from Flash.
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*/
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if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1))
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if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
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{
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return max_sdram_size();
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}
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@ -85,16 +85,16 @@ static void sdram_timing_init (ulong size)
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while (p4 < 32 && done == 0) {
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WRITE_MC_IOGP_1;
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for (addr = KSEG1 + 0x4000;
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addr < KSEG1ADDR (size);
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for (addr = CKSEG1 + 0x4000;
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addr < CKSEG1ADDR (size);
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addr = addr + 4) {
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*(uint *) addr = 0xaa55aa55;
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}
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pass = 1;
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for (addr = KSEG1 + 0x4000;
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addr < KSEG1ADDR (size) && pass == 1;
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for (addr = CKSEG1 + 0x4000;
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addr < CKSEG1ADDR (size) && pass == 1;
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addr = addr + 4) {
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if (*(uint *) addr != 0xaa55aa55)
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pass = 0;
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@ -138,7 +138,7 @@ long int initdram(int board_type)
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ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
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void (* sdram_init) (ulong);
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sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init);
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sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
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sdram_init(0x10000);
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@ -260,14 +260,14 @@ void copy_code (ulong dest_addr)
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/* flush caches
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*/
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start = KSEG0;
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start = CKSEG0;
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end = start + CFG_DCACHE_SIZE;
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while(start < end) {
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cache_unroll(start,Index_Writeback_Inv_D);
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start += CFG_CACHELINE_SIZE;
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}
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start = KSEG0;
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start = CKSEG0;
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end = start + CFG_ICACHE_SIZE;
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while(start < end) {
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cache_unroll(start,Index_Invalidate_I);
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@ -13,34 +13,34 @@
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#include <pci.h>
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#include <asm/addrspace.h>
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#define VR4131_PCIMMAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c00)
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#define VR4131_PCIMMAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c04)
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#define VR4131_PCITAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c08)
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#define VR4131_PCITAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c0c)
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#define VR4131_PCIMIOAWREG (volatile unsigned int*)(KSEG1 + 0x0f000c10)
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#define VR4131_PCICONFDREG (volatile unsigned int*)(KSEG1 + 0x0f000c14)
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#define VR4131_PCICONFAREG (volatile unsigned int*)(KSEG1 + 0x0f000c18)
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#define VR4131_PCIMAILREG (volatile unsigned int*)(KSEG1 + 0x0f000c1c)
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#define VR4131_BUSERRADREG (volatile unsigned int*)(KSEG1 + 0x0f000c24)
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#define VR4131_INTCNTSTAREG (volatile unsigned int*)(KSEG1 + 0x0f000c28)
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#define VR4131_PCIEXACCREG (volatile unsigned int*)(KSEG1 + 0x0f000c2c)
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#define VR4131_PCIRECONTREG (volatile unsigned int*)(KSEG1 + 0x0f000c30)
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#define VR4131_PCIENREG (volatile unsigned int*)(KSEG1 + 0x0f000c34)
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#define VR4131_PCICLKSELREG (volatile unsigned int*)(KSEG1 + 0x0f000c38)
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#define VR4131_PCITRDYREG (volatile unsigned int*)(KSEG1 + 0x0f000c3c)
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#define VR4131_PCICLKRUNREG (volatile unsigned int*)(KSEG1 + 0x0f000c60)
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#define VR4131_PCIHOSTCONFIG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
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#define VR4131_VENDORIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
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#define VR4131_DEVICEIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
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#define VR4131_COMMANDREG (volatile unsigned int*)(KSEG1 + 0x0f000d04)
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#define VR4131_STATUSREG (volatile unsigned int*)(KSEG1 + 0x0f000d04)
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#define VR4131_REVREG (volatile unsigned int*)(KSEG1 + 0x0f000d08)
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#define VR4131_CLASSREG (volatile unsigned int*)(KSEG1 + 0x0f000d08)
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#define VR4131_CACHELSREG (volatile unsigned int*)(KSEG1 + 0x0f000d0c)
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#define VR4131_LATTIMERRG (volatile unsigned int*)(KSEG1 + 0x0f000d0c)
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#define VR4131_MAILBAREG (volatile unsigned int*)(KSEG1 + 0x0f000d10)
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#define VR4131_PCIMBA1REG (volatile unsigned int*)(KSEG1 + 0x0f000d14)
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#define VR4131_PCIMBA2REG (volatile unsigned int*)(KSEG1 + 0x0f000d18)
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#define VR4131_PCIMMAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c00)
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#define VR4131_PCIMMAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c04)
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#define VR4131_PCITAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c08)
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#define VR4131_PCITAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c0c)
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#define VR4131_PCIMIOAWREG (volatile unsigned int *)(CKSEG1 + 0x0f000c10)
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#define VR4131_PCICONFDREG (volatile unsigned int *)(CKSEG1 + 0x0f000c14)
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#define VR4131_PCICONFAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c18)
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#define VR4131_PCIMAILREG (volatile unsigned int *)(CKSEG1 + 0x0f000c1c)
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#define VR4131_BUSERRADREG (volatile unsigned int *)(CKSEG1 + 0x0f000c24)
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#define VR4131_INTCNTSTAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c28)
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#define VR4131_PCIEXACCREG (volatile unsigned int *)(CKSEG1 + 0x0f000c2c)
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#define VR4131_PCIRECONTREG (volatile unsigned int *)(CKSEG1 + 0x0f000c30)
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#define VR4131_PCIENREG (volatile unsigned int *)(CKSEG1 + 0x0f000c34)
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#define VR4131_PCICLKSELREG (volatile unsigned int *)(CKSEG1 + 0x0f000c38)
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#define VR4131_PCITRDYREG (volatile unsigned int *)(CKSEG1 + 0x0f000c3c)
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#define VR4131_PCICLKRUNREG (volatile unsigned int *)(CKSEG1 + 0x0f000c60)
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#define VR4131_PCIHOSTCONFIG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
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#define VR4131_VENDORIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
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#define VR4131_DEVICEIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
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#define VR4131_COMMANDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04)
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#define VR4131_STATUSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04)
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#define VR4131_REVREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08)
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#define VR4131_CLASSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08)
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#define VR4131_CACHELSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
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#define VR4131_LATTIMERRG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
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#define VR4131_MAILBAREG (volatile unsigned int *)(CKSEG1 + 0x0f000d10)
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#define VR4131_PCIMBA1REG (volatile unsigned int *)(CKSEG1 + 0x0f000d14)
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#define VR4131_PCIMBA2REG (volatile unsigned int *)(CKSEG1 + 0x0f000d18)
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/*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */
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/*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */
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@ -40,7 +40,7 @@
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*/
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#define MIPS_MAX_CACHE_SIZE 0x10000
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#define INDEX_BASE KSEG0
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#define INDEX_BASE CKSEG0
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.macro cache_op op addr
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.set push
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@ -218,7 +218,7 @@ NESTED(mips_cache_reset, 0, ra)
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/*
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* Now clear that much memory starting from zero.
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*/
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PTR_LI a0, KSEG1
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PTR_LI a0, CKSEG1
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PTR_ADDU a1, a0, v0
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2: PTR_ADDIU a0, 64
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f_fill64 a0, -64, zero
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@ -318,7 +318,7 @@ LEAF(dcache_enable)
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.globl mips_cache_lock
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.ent mips_cache_lock
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mips_cache_lock:
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li a1, K0BASE - CACHE_LOCK_SIZE
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li a1, CKSEG0 - CACHE_LOCK_SIZE
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addu a0, a1
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li a2, CACHE_LOCK_SIZE
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li a3, CFG_CACHELINE_SIZE
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@ -234,7 +234,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
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/* Initialize the descriptor rings.
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*/
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for (i = 0; i < NUM_RX_DESC; i++) {
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inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]);
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inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
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memset(rx_desc, 0, sizeof(rx_ring[i]));
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/* Set maximum size of receive buffer.
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@ -252,14 +252,14 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
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/* Let the last descriptor point to the first
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* one.
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*/
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rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring);
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rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
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} else {
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/* Set the address of the next descriptor.
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*/
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rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]);
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rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
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}
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rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]);
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rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
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}
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#if 0
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@ -268,7 +268,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
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#endif
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for (i = 0; i < NUM_TX_DESC; i++) {
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inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]);
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inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
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memset(tx_desc, 0, sizeof(tx_ring[i]));
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@ -282,11 +282,11 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
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/* Let the last descriptor point to the
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* first one.
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*/
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tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring);
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tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
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} else {
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/* Set the address of the next descriptor.
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*/
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tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]);
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tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
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}
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}
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@ -346,7 +346,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
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int res = -1;
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u32 command;
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u32 regValue;
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inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]);
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inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
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#if 0
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printf("Entered inca_switch_send()\n");
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@ -365,7 +365,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
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}
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if (tx_old_hold >= 0) {
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KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1;
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((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
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}
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tx_old_hold = tx_hold;
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@ -376,7 +376,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
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tx_desc->TxDataPtr = (u32)packet;
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tx_desc->params.field.NBA = length;
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KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0;
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((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
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tx_hold = tx_new;
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tx_new = (tx_new + 1) % NUM_TX_DESC;
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@ -397,7 +397,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
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DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
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#if 1
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for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) {
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for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
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if (i >= TOUT_LOOP) {
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printf("%s: tx buffer not ready\n", dev->name);
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goto Done;
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@ -423,7 +423,7 @@ static int inca_switch_recv(struct eth_device *dev)
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#endif
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for (;;) {
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rx_desc = KSEG1ADDR(&rx_ring[rx_new]);
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rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
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if (rx_desc->status.field.C == 0) {
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break;
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@ -456,7 +456,7 @@ static int inca_switch_recv(struct eth_device *dev)
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#if 0
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printf("Received %d bytes\n", length);
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#endif
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NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), length - 4);
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NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
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} else {
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#if 1
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printf("Zero length!!!\n");
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@ -464,7 +464,7 @@ static int inca_switch_recv(struct eth_device *dev)
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}
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KSEG1ADDR(&rx_ring[rx_hold])->params.field.HOLD = 0;
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((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
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rx_hold = rx_new;
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@ -3,16 +3,94 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996 by Ralf Baechle
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* Copyright (C) 2000 by Maciej W. Rozycki
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*
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* Defitions for the address spaces of the MIPS CPUs.
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* Copyright (C) 1996, 99 Ralf Baechle
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* Copyright (C) 2000, 2002 Maciej W. Rozycki
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* Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
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*/
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#ifndef __ASM_MIPS_ADDRSPACE_H
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#define __ASM_MIPS_ADDRSPACE_H
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#ifndef _ASM_ADDRSPACE_H
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#define _ASM_ADDRSPACE_H
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/*
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* Configure language
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*/
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#ifdef __ASSEMBLY__
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#define _ATYPE_
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#define _ATYPE32_
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#define _ATYPE64_
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#define _CONST64_(x) x
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#else
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#define _ATYPE_ __PTRDIFF_TYPE__
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#define _ATYPE32_ int
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#define _ATYPE64_ __s64
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#ifdef CONFIG_64BIT
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#define _CONST64_(x) x ## L
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#else
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#define _CONST64_(x) x ## LL
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#endif
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#endif
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/*
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* 32-bit MIPS address spaces
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*/
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#ifdef __ASSEMBLY__
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#define _ACAST32_
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#define _ACAST64_
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#else
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#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
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#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
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#endif
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/*
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* Returns the kernel segment base of a given address
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*/
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#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
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/*
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* Returns the physical address of a CKSEGx / XKPHYS address
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*/
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#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
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#define XPHYSADDR(a) ((_ACAST64_(a)) & \
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_CONST64_(0x000000ffffffffff))
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#ifdef CONFIG_64BIT
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/*
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* Memory segments (64bit kernel mode addresses)
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* The compatibility segments use the full 64-bit sign extended value. Note
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* the R8000 doesn't have them so don't reference these in generic MIPS code.
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*/
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#define XKUSEG _CONST64_(0x0000000000000000)
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#define XKSSEG _CONST64_(0x4000000000000000)
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#define XKPHYS _CONST64_(0x8000000000000000)
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#define XKSEG _CONST64_(0xc000000000000000)
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#define CKSEG0 _CONST64_(0xffffffff80000000)
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#define CKSEG1 _CONST64_(0xffffffffa0000000)
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#define CKSSEG _CONST64_(0xffffffffc0000000)
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#define CKSEG3 _CONST64_(0xffffffffe0000000)
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#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
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#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
|
||||
#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
|
||||
#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
|
||||
|
||||
#else
|
||||
|
||||
#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
|
||||
#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
|
||||
#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
|
||||
#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
|
||||
|
||||
/*
|
||||
* Map an address to a certain kernel segment
|
||||
*/
|
||||
#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
|
||||
#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
|
||||
#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
|
||||
#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
|
||||
|
||||
/*
|
||||
* Memory segments (32bit kernel mode addresses)
|
||||
* These are the traditional names used in the 32-bit universe.
|
||||
*/
|
||||
#define KUSEG 0x00000000
|
||||
#define KSEG0 0x80000000
|
||||
|
|
@ -20,25 +98,34 @@
|
|||
#define KSEG2 0xc0000000
|
||||
#define KSEG3 0xe0000000
|
||||
|
||||
#define K0BASE KSEG0
|
||||
#define CKUSEG 0x00000000
|
||||
#define CKSEG0 0x80000000
|
||||
#define CKSEG1 0xa0000000
|
||||
#define CKSEG2 0xc0000000
|
||||
#define CKSEG3 0xe0000000
|
||||
|
||||
/*
|
||||
* Returns the kernel segment base of a given address
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000)
|
||||
#else
|
||||
#define KSEGX(a) ((a) & 0xe0000000)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Returns the physical address of a KSEG0/KSEG1 address
|
||||
* Cache modes for XKPHYS address conversion macros
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
|
||||
#else
|
||||
#define PHYSADDR(a) ((a) & 0x1fffffff)
|
||||
#endif
|
||||
#define K_CALG_COH_EXCL1_NOL2 0
|
||||
#define K_CALG_COH_SHRL1_NOL2 1
|
||||
#define K_CALG_UNCACHED 2
|
||||
#define K_CALG_NONCOHERENT 3
|
||||
#define K_CALG_COH_EXCL 4
|
||||
#define K_CALG_COH_SHAREABLE 5
|
||||
#define K_CALG_NOTUSED 6
|
||||
#define K_CALG_UNCACHED_ACCEL 7
|
||||
|
||||
/*
|
||||
* 64-bit address conversions
|
||||
*/
|
||||
#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
|
||||
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
|
||||
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
|
||||
#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
|
||||
(_CONST64_(cm) << 59) | (a))
|
||||
|
||||
/*
|
||||
* Returns the uncached address of a sdram address
|
||||
|
|
@ -52,31 +139,27 @@
|
|||
#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
|
||||
#endif /* CONFIG_AU1X00 */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* Map an address to a certain kernel segment
|
||||
* The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
|
||||
* the region, 3 bits for the CCA mode. This leaves 59 bits of which the
|
||||
* R8000 implements most with its 48-bit physical address space.
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0))
|
||||
#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1))
|
||||
#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2))
|
||||
#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3))
|
||||
#else
|
||||
#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0)
|
||||
#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1)
|
||||
#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2)
|
||||
#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3)
|
||||
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
|
||||
|
||||
#ifndef CONFIG_CPU_R8000
|
||||
|
||||
/*
|
||||
* The R8000 doesn't have the 32-bit compat spaces so we don't define them
|
||||
* in order to catch bugs in the source code.
|
||||
*/
|
||||
|
||||
#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
|
||||
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Memory segments (64bit kernel mode addresses)
|
||||
*/
|
||||
#define XKUSEG 0x0000000000000000
|
||||
#define XKSSEG 0x4000000000000000
|
||||
#define XKPHYS 0x8000000000000000
|
||||
#define XKSEG 0xc000000000000000
|
||||
#define CKSEG0 0xffffffff80000000
|
||||
#define CKSEG1 0xffffffffa0000000
|
||||
#define CKSSEG 0xffffffffc0000000
|
||||
#define CKSEG3 0xffffffffe0000000
|
||||
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
|
||||
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
|
||||
|
||||
#endif /* __ASM_MIPS_ADDRSPACE_H */
|
||||
#endif /* _ASM_ADDRSPACE_H */
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@ static inline void set_io_port_base(unsigned long base)
|
|||
*/
|
||||
extern inline unsigned long virt_to_phys(volatile void * address)
|
||||
{
|
||||
return PHYSADDR(address);
|
||||
return CPHYSADDR(address);
|
||||
}
|
||||
|
||||
extern inline void * phys_to_virt(unsigned long address)
|
||||
|
|
@ -133,7 +133,7 @@ extern inline void * phys_to_virt(unsigned long address)
|
|||
*/
|
||||
extern inline unsigned long virt_to_bus(volatile void * address)
|
||||
{
|
||||
return PHYSADDR(address);
|
||||
return CPHYSADDR(address);
|
||||
}
|
||||
|
||||
extern inline void * bus_to_virt(unsigned long address)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue