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[MIPS] Update <asm/addrspace.h> header

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- Fix traditional KSEG names
- Replace PHYSADDR with CPHYSADDR

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This commit is contained in:
Shinya Kuribayashi 2008-06-05 22:29:00 +09:00 • committed by Shinya Kuribayashi
parent f0d5a6f060
commit 7daf2ebe91
8 changed files with 182 additions and 99 deletions
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2
board/gth2/gth2.c
View file

@ -36,7 +36,7 @@ static int wdi_status = 0;
#define SDRAM_SIZE ((64*1024*1024)-(12*4096)) #define SDRAM_SIZE ((64*1024*1024)-(12*4096))
#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096)) #define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096))
void inline log_serial_char(char c){ void inline log_serial_char(char c){
char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER; char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;

2
board/incaip/incaip.c
View file

@ -63,7 +63,7 @@ long int initdram(int board_type)
/* Can't probe for RAM size unless we are running from Flash. /* Can't probe for RAM size unless we are running from Flash.
*/ */
if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1)) if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
{ {
return max_sdram_size(); return max_sdram_size();
} }

14
board/purple/purple.c
View file

@ -85,16 +85,16 @@ static void sdram_timing_init (ulong size)
while (p4 < 32 && done == 0) { while (p4 < 32 && done == 0) {
WRITE_MC_IOGP_1; WRITE_MC_IOGP_1;
for (addr = KSEG1 + 0x4000; for (addr = CKSEG1 + 0x4000;
addr < KSEG1ADDR (size); addr < CKSEG1ADDR (size);
addr = addr + 4) { addr = addr + 4) {
*(uint *) addr = 0xaa55aa55; *(uint *) addr = 0xaa55aa55;
} }
pass = 1; pass = 1;
for (addr = KSEG1 + 0x4000; for (addr = CKSEG1 + 0x4000;
addr < KSEG1ADDR (size) && pass == 1; addr < CKSEG1ADDR (size) && pass == 1;
addr = addr + 4) { addr = addr + 4) {
if (*(uint *) addr != 0xaa55aa55) if (*(uint *) addr != 0xaa55aa55)
pass = 0; pass = 0;
@ -138,7 +138,7 @@ long int initdram(int board_type)
ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB; ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
void (* sdram_init) (ulong); void (* sdram_init) (ulong);
sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init); sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
sdram_init(0x10000); sdram_init(0x10000);
@ -260,14 +260,14 @@ void copy_code (ulong dest_addr)
/* flush caches /* flush caches
*/ */
start = KSEG0; start = CKSEG0;
end = start + CFG_DCACHE_SIZE; end = start + CFG_DCACHE_SIZE;
while(start < end) { while(start < end) {
cache_unroll(start,Index_Writeback_Inv_D); cache_unroll(start,Index_Writeback_Inv_D);
start += CFG_CACHELINE_SIZE; start += CFG_CACHELINE_SIZE;
} }
start = KSEG0; start = CKSEG0;
end = start + CFG_ICACHE_SIZE; end = start + CFG_ICACHE_SIZE;
while(start < end) { while(start < end) {
cache_unroll(start,Index_Invalidate_I); cache_unroll(start,Index_Invalidate_I);

56
board/tb0229/vr4131-pci.c
View file

@ -13,34 +13,34 @@
#include <pci.h> #include <pci.h>
#include <asm/addrspace.h> #include <asm/addrspace.h>
#define VR4131_PCIMMAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c00) #define VR4131_PCIMMAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c00)
#define VR4131_PCIMMAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c04) #define VR4131_PCIMMAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c04)
#define VR4131_PCITAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c08) #define VR4131_PCITAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c08)
#define VR4131_PCITAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c0c) #define VR4131_PCITAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c0c)
#define VR4131_PCIMIOAWREG (volatile unsigned int*)(KSEG1 + 0x0f000c10) #define VR4131_PCIMIOAWREG (volatile unsigned int *)(CKSEG1 + 0x0f000c10)
#define VR4131_PCICONFDREG (volatile unsigned int*)(KSEG1 + 0x0f000c14) #define VR4131_PCICONFDREG (volatile unsigned int *)(CKSEG1 + 0x0f000c14)
#define VR4131_PCICONFAREG (volatile unsigned int*)(KSEG1 + 0x0f000c18) #define VR4131_PCICONFAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c18)
#define VR4131_PCIMAILREG (volatile unsigned int*)(KSEG1 + 0x0f000c1c) #define VR4131_PCIMAILREG (volatile unsigned int *)(CKSEG1 + 0x0f000c1c)
#define VR4131_BUSERRADREG (volatile unsigned int*)(KSEG1 + 0x0f000c24) #define VR4131_BUSERRADREG (volatile unsigned int *)(CKSEG1 + 0x0f000c24)
#define VR4131_INTCNTSTAREG (volatile unsigned int*)(KSEG1 + 0x0f000c28) #define VR4131_INTCNTSTAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c28)
#define VR4131_PCIEXACCREG (volatile unsigned int*)(KSEG1 + 0x0f000c2c) #define VR4131_PCIEXACCREG (volatile unsigned int *)(CKSEG1 + 0x0f000c2c)
#define VR4131_PCIRECONTREG (volatile unsigned int*)(KSEG1 + 0x0f000c30) #define VR4131_PCIRECONTREG (volatile unsigned int *)(CKSEG1 + 0x0f000c30)
#define VR4131_PCIENREG (volatile unsigned int*)(KSEG1 + 0x0f000c34) #define VR4131_PCIENREG (volatile unsigned int *)(CKSEG1 + 0x0f000c34)
#define VR4131_PCICLKSELREG (volatile unsigned int*)(KSEG1 + 0x0f000c38) #define VR4131_PCICLKSELREG (volatile unsigned int *)(CKSEG1 + 0x0f000c38)
#define VR4131_PCITRDYREG (volatile unsigned int*)(KSEG1 + 0x0f000c3c) #define VR4131_PCITRDYREG (volatile unsigned int *)(CKSEG1 + 0x0f000c3c)
#define VR4131_PCICLKRUNREG (volatile unsigned int*)(KSEG1 + 0x0f000c60) #define VR4131_PCICLKRUNREG (volatile unsigned int *)(CKSEG1 + 0x0f000c60)
#define VR4131_PCIHOSTCONFIG (volatile unsigned int*)(KSEG1 + 0x0f000d00) #define VR4131_PCIHOSTCONFIG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
#define VR4131_VENDORIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00) #define VR4131_VENDORIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
#define VR4131_DEVICEIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00) #define VR4131_DEVICEIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
#define VR4131_COMMANDREG (volatile unsigned int*)(KSEG1 + 0x0f000d04) #define VR4131_COMMANDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04)
#define VR4131_STATUSREG (volatile unsigned int*)(KSEG1 + 0x0f000d04) #define VR4131_STATUSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04)
#define VR4131_REVREG (volatile unsigned int*)(KSEG1 + 0x0f000d08) #define VR4131_REVREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08)
#define VR4131_CLASSREG (volatile unsigned int*)(KSEG1 + 0x0f000d08) #define VR4131_CLASSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08)
#define VR4131_CACHELSREG (volatile unsigned int*)(KSEG1 + 0x0f000d0c) #define VR4131_CACHELSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
#define VR4131_LATTIMERRG (volatile unsigned int*)(KSEG1 + 0x0f000d0c) #define VR4131_LATTIMERRG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
#define VR4131_MAILBAREG (volatile unsigned int*)(KSEG1 + 0x0f000d10) #define VR4131_MAILBAREG (volatile unsigned int *)(CKSEG1 + 0x0f000d10)
#define VR4131_PCIMBA1REG (volatile unsigned int*)(KSEG1 + 0x0f000d14) #define VR4131_PCIMBA1REG (volatile unsigned int *)(CKSEG1 + 0x0f000d14)
#define VR4131_PCIMBA2REG (volatile unsigned int*)(KSEG1 + 0x0f000d18) #define VR4131_PCIMBA2REG (volatile unsigned int *)(CKSEG1 + 0x0f000d18)
/*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */ /*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */
/*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */ /*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */

6
cpu/mips/cache.S
View file

@ -40,7 +40,7 @@
*/ */
#define MIPS_MAX_CACHE_SIZE 0x10000 #define MIPS_MAX_CACHE_SIZE 0x10000
#define INDEX_BASE KSEG0 #define INDEX_BASE CKSEG0
.macro cache_op op addr .macro cache_op op addr
.set push .set push
@ -218,7 +218,7 @@ NESTED(mips_cache_reset, 0, ra)
/* /*
* Now clear that much memory starting from zero. * Now clear that much memory starting from zero.
*/ */
PTR_LI a0, KSEG1 PTR_LI a0, CKSEG1
PTR_ADDU a1, a0, v0 PTR_ADDU a1, a0, v0
2: PTR_ADDIU a0, 64 2: PTR_ADDIU a0, 64
f_fill64 a0, -64, zero f_fill64 a0, -64, zero
@ -318,7 +318,7 @@ LEAF(dcache_enable)
.globl mips_cache_lock .globl mips_cache_lock
.ent mips_cache_lock .ent mips_cache_lock
mips_cache_lock: mips_cache_lock:
li a1, K0BASE - CACHE_LOCK_SIZE li a1, CKSEG0 - CACHE_LOCK_SIZE
addu a0, a1 addu a0, a1
li a2, CACHE_LOCK_SIZE li a2, CACHE_LOCK_SIZE
li a3, CFG_CACHELINE_SIZE li a3, CFG_CACHELINE_SIZE

28
drivers/net/inca-ip_sw.c
View file

@ -234,7 +234,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
/* Initialize the descriptor rings. /* Initialize the descriptor rings.
*/ */
for (i = 0; i < NUM_RX_DESC; i++) { for (i = 0; i < NUM_RX_DESC; i++) {
inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]); inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
memset(rx_desc, 0, sizeof(rx_ring[i])); memset(rx_desc, 0, sizeof(rx_ring[i]));
/* Set maximum size of receive buffer. /* Set maximum size of receive buffer.
@ -252,14 +252,14 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
/* Let the last descriptor point to the first /* Let the last descriptor point to the first
* one. * one.
*/ */
rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring); rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
} else { } else {
/* Set the address of the next descriptor. /* Set the address of the next descriptor.
*/ */
rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]); rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
} }
rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]); rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
} }
#if 0 #if 0
@ -268,7 +268,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
#endif #endif
for (i = 0; i < NUM_TX_DESC; i++) { for (i = 0; i < NUM_TX_DESC; i++) {
inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]); inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
memset(tx_desc, 0, sizeof(tx_ring[i])); memset(tx_desc, 0, sizeof(tx_ring[i]));
@ -282,11 +282,11 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
/* Let the last descriptor point to the /* Let the last descriptor point to the
* first one. * first one.
*/ */
tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring); tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
} else { } else {
/* Set the address of the next descriptor. /* Set the address of the next descriptor.
*/ */
tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]); tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
} }
} }
@ -346,7 +346,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
int res = -1; int res = -1;
u32 command; u32 command;
u32 regValue; u32 regValue;
inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]); inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
#if 0 #if 0
printf("Entered inca_switch_send()\n"); printf("Entered inca_switch_send()\n");
@ -365,7 +365,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
} }
if (tx_old_hold >= 0) { if (tx_old_hold >= 0) {
KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
} }
tx_old_hold = tx_hold; tx_old_hold = tx_hold;
@ -376,7 +376,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
tx_desc->TxDataPtr = (u32)packet; tx_desc->TxDataPtr = (u32)packet;
tx_desc->params.field.NBA = length; tx_desc->params.field.NBA = length;
KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
tx_hold = tx_new; tx_hold = tx_new;
tx_new = (tx_new + 1) % NUM_TX_DESC; tx_new = (tx_new + 1) % NUM_TX_DESC;
@ -397,7 +397,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
#if 1 #if 1
for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) { for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
if (i >= TOUT_LOOP) { if (i >= TOUT_LOOP) {
printf("%s: tx buffer not ready\n", dev->name); printf("%s: tx buffer not ready\n", dev->name);
goto Done; goto Done;
@ -423,7 +423,7 @@ static int inca_switch_recv(struct eth_device *dev)
#endif #endif
for (;;) { for (;;) {
rx_desc = KSEG1ADDR(&rx_ring[rx_new]); rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
if (rx_desc->status.field.C == 0) { if (rx_desc->status.field.C == 0) {
break; break;
@ -456,7 +456,7 @@ static int inca_switch_recv(struct eth_device *dev)
#if 0 #if 0
printf("Received %d bytes\n", length); printf("Received %d bytes\n", length);
#endif #endif
NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), length - 4); NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
} else { } else {
#if 1 #if 1
printf("Zero length!!!\n"); printf("Zero length!!!\n");
@ -464,7 +464,7 @@ static int inca_switch_recv(struct eth_device *dev)
} }
KSEG1ADDR(&rx_ring[rx_hold])->params.field.HOLD = 0; ((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
rx_hold = rx_new; rx_hold = rx_new;

169
include/asm-mips/addrspace.h
View file

@ -3,16 +3,94 @@
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
* for more details. * for more details.
* *
* Copyright (C) 1996 by Ralf Baechle * Copyright (C) 1996, 99 Ralf Baechle
* Copyright (C) 2000 by Maciej W. Rozycki * Copyright (C) 2000, 2002 Maciej W. Rozycki
* * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
* Defitions for the address spaces of the MIPS CPUs.
*/ */
#ifndef __ASM_MIPS_ADDRSPACE_H #ifndef _ASM_ADDRSPACE_H
#define __ASM_MIPS_ADDRSPACE_H #define _ASM_ADDRSPACE_H
/*
* Configure language
*/
#ifdef __ASSEMBLY__
#define _ATYPE_
#define _ATYPE32_
#define _ATYPE64_
#define _CONST64_(x) x
#else
#define _ATYPE_ __PTRDIFF_TYPE__
#define _ATYPE32_ int
#define _ATYPE64_ __s64
#ifdef CONFIG_64BIT
#define _CONST64_(x) x ## L
#else
#define _CONST64_(x) x ## LL
#endif
#endif
/*
* 32-bit MIPS address spaces
*/
#ifdef __ASSEMBLY__
#define _ACAST32_
#define _ACAST64_
#else
#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
#endif
/*
* Returns the kernel segment base of a given address
*/
#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
/*
* Returns the physical address of a CKSEGx / XKPHYS address
*/
#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
#define XPHYSADDR(a) ((_ACAST64_(a)) & \
_CONST64_(0x000000ffffffffff))
#ifdef CONFIG_64BIT
/*
* Memory segments (64bit kernel mode addresses)
* The compatibility segments use the full 64-bit sign extended value. Note
* the R8000 doesn't have them so don't reference these in generic MIPS code.
*/
#define XKUSEG _CONST64_(0x0000000000000000)
#define XKSSEG _CONST64_(0x4000000000000000)
#define XKPHYS _CONST64_(0x8000000000000000)
#define XKSEG _CONST64_(0xc000000000000000)
#define CKSEG0 _CONST64_(0xffffffff80000000)
#define CKSEG1 _CONST64_(0xffffffffa0000000)
#define CKSSEG _CONST64_(0xffffffffc0000000)
#define CKSEG3 _CONST64_(0xffffffffe0000000)
#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
#else
#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
/*
* Map an address to a certain kernel segment
*/
#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
/* /*
* Memory segments (32bit kernel mode addresses) * Memory segments (32bit kernel mode addresses)
* These are the traditional names used in the 32-bit universe.
*/ */
#define KUSEG 0x00000000 #define KUSEG 0x00000000
#define KSEG0 0x80000000 #define KSEG0 0x80000000
@ -20,25 +98,34 @@
#define KSEG2 0xc0000000 #define KSEG2 0xc0000000
#define KSEG3 0xe0000000 #define KSEG3 0xe0000000
#define K0BASE KSEG0 #define CKUSEG 0x00000000
#define CKSEG0 0x80000000
#define CKSEG1 0xa0000000
#define CKSEG2 0xc0000000
#define CKSEG3 0xe0000000
/*
* Returns the kernel segment base of a given address
*/
#ifndef __ASSEMBLY__
#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000)
#else
#define KSEGX(a) ((a) & 0xe0000000)
#endif #endif
/* /*
* Returns the physical address of a KSEG0/KSEG1 address * Cache modes for XKPHYS address conversion macros
*/ */
#ifndef __ASSEMBLY__ #define K_CALG_COH_EXCL1_NOL2 0
#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) #define K_CALG_COH_SHRL1_NOL2 1
#else #define K_CALG_UNCACHED 2
#define PHYSADDR(a) ((a) & 0x1fffffff) #define K_CALG_NONCOHERENT 3
#endif #define K_CALG_COH_EXCL 4
#define K_CALG_COH_SHAREABLE 5
#define K_CALG_NOTUSED 6
#define K_CALG_UNCACHED_ACCEL 7
/*
* 64-bit address conversions
*/
#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
(_CONST64_(cm) << 59) | (a))
/* /*
* Returns the uncached address of a sdram address * Returns the uncached address of a sdram address
@ -52,31 +139,27 @@
#define UNCACHED_SDRAM(a) KSEG1ADDR(a) #define UNCACHED_SDRAM(a) KSEG1ADDR(a)
#endif /* CONFIG_AU1X00 */ #endif /* CONFIG_AU1X00 */
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
/* /*
* Map an address to a certain kernel segment * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
* the region, 3 bits for the CCA mode. This leaves 59 bits of which the
* R8000 implements most with its 48-bit physical address space.
*/ */
#ifndef __ASSEMBLY__ #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0))
#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1)) #ifndef CONFIG_CPU_R8000
#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2))
#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3)) /*
#else * The R8000 doesn't have the 32-bit compat spaces so we don't define them
#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0) * in order to catch bugs in the source code.
#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1) */
#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2)
#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3) #define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
#endif #endif
/* #define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
* Memory segments (64bit kernel mode addresses) #define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
*/
#define XKUSEG 0x0000000000000000
#define XKSSEG 0x4000000000000000
#define XKPHYS 0x8000000000000000
#define XKSEG 0xc000000000000000
#define CKSEG0 0xffffffff80000000
#define CKSEG1 0xffffffffa0000000
#define CKSSEG 0xffffffffc0000000
#define CKSEG3 0xffffffffe0000000
#endif /* __ASM_MIPS_ADDRSPACE_H */ #endif /* _ASM_ADDRSPACE_H */

4
include/asm-mips/io.h
View file

@ -120,7 +120,7 @@ static inline void set_io_port_base(unsigned long base)
*/ */
extern inline unsigned long virt_to_phys(volatile void * address) extern inline unsigned long virt_to_phys(volatile void * address)
{ {
return PHYSADDR(address); return CPHYSADDR(address);
} }
extern inline void * phys_to_virt(unsigned long address) extern inline void * phys_to_virt(unsigned long address)
@ -133,7 +133,7 @@ extern inline void * phys_to_virt(unsigned long address)
*/ */
extern inline unsigned long virt_to_bus(volatile void * address) extern inline unsigned long virt_to_bus(volatile void * address)
{ {
return PHYSADDR(address); return CPHYSADDR(address);
} }
extern inline void * bus_to_virt(unsigned long address) extern inline void * bus_to_virt(unsigned long address)