GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-21 14:41:31 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

sh: sh2: Remove CPU support

Browse source 
This CPU core is old, no boards using the CPU are left in mainline,
it has no prospects of ever being converted to DM, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
This commit is contained in:
Marek Vasut 2019-05-07 21:52:47 +02:00 • committed by Marek Vasut
parent 54eac8b3a3
commit 7de3ea8b98
16 changed files with 2 additions and 325 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
arch/sh/Kconfig
View file

@ -1,13 +1,6 @@
menu "SuperH architecture"
depends on SH
config CPU_SH2
bool
config CPU_SH2A
bool
select CPU_SH2
config CPU_SH3
bool
@ -101,7 +94,6 @@ config SYS_ARCH
default "sh"
config SYS_CPU
default "sh2" if CPU_SH2
default "sh3" if CPU_SH3
default "sh4" if CPU_SH4

9
arch/sh/cpu/sh2/Makefile
View file

@ -1,9 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
# Copyright (C) 2008 Renesas Solutions Corp.
obj-y = cpu.o interrupts.o watchdog.o

15
arch/sh/cpu/sh2/config.mk
View file

@ -1,15 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2007-2008
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
ENDIANNESS += -EB
ifdef CONFIG_CPU_SH2A
PLATFORM_CPPFLAGS += -m2a-nofpu -mb
else # SH2
PLATFORM_CPPFLAGS += -m3e -mb
endif
PLATFORM_CPPFLAGS += $(call cc-option,-mno-fdpic)
PLATFORM_LDFLAGS += $(ENDIANNESS)

84
arch/sh/cpu/sh2/cpu.c
View file

@ -1,84 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#define STBCR4 0xFFFE040C
#define cmt_clock_enable() do {\
writeb(readb(STBCR4) & ~0x04, STBCR4);\
} while (0)
#define scif0_enable() do {\
writeb(readb(STBCR4) & ~0x80, STBCR4);\
} while (0)
#define scif3_enable() do {\
writeb(readb(STBCR4) & ~0x10, STBCR4);\
} while (0)
int checkcpu(void)
{
puts("CPU: SH2\n");
return 0;
}
int cpu_init(void)
{
/* SCIF enable */
#if defined(CONFIG_CONS_SCIF3)
scif3_enable();
#else
scif0_enable();
#endif
/* CMT clock enable */
cmt_clock_enable() ;
return 0;
}
int cleanup_before_linux(void)
{
disable_interrupts();
return 0;
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
reset_cpu(0);
return 0;
}
void flush_cache(unsigned long addr, unsigned long size)
{
}
void icache_enable(void)
{
}
void icache_disable(void)
{
}
int icache_status(void)
{
return 0;
}
void dcache_enable(void)
{
}
void dcache_disable(void)
{
}
int dcache_status(void)
{
return 0;
}

22
arch/sh/cpu/sh2/interrupts.c
View file

@ -1,22 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
*/
#include <common.h>
int interrupt_init(void)
{
return 0;
}
void enable_interrupts(void)
{
}
int disable_interrupts(void)
{
return 0;
}

23
arch/sh/cpu/sh2/watchdog.c
View file

@ -1,23 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2008,2010 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2008,2010 Renesas Solutions Corp.
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/system.h>
int watchdog_init(void)
{
return 0;
}
void reset_cpu(unsigned long ignored)
{
/* Address error with SR.BL=1 first. */
trigger_address_error();
while (1)
;
}

2
arch/sh/include/asm/config.h
View file

@ -6,13 +6,11 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#if !defined(CONFIG_CPU_SH2)
#include <asm/processor.h>
/* Timer */
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0x8) /* TCNT0 */
#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
#endif
#endif

30
arch/sh/include/asm/cpu_sh2.h
View file

@ -1,30 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
*/
#ifndef _ASM_CPU_SH2_H_
#define _ASM_CPU_SH2_H_
/* cache control */
#define CCR_CACHE_STOP 0x00000008
#define CCR_CACHE_ENABLE 0x00000005
#define CCR_CACHE_ICI 0x00000008
#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
#define CACHE_OC_WAY_SHIFT 13
#define CACHE_OC_NUM_ENTRIES 256
#define CACHE_OC_ENTRY_SHIFT 4
#if defined(CONFIG_CPU_SH7203)
# include <asm/cpu_sh7203.h>
#elif defined(CONFIG_CPU_SH7264)
# include <asm/cpu_sh7264.h>
#elif defined(CONFIG_CPU_SH7269)
# include <asm/cpu_sh7269.h>
#else
# error "Unknown SH2 variant"
#endif
#endif /* _ASM_CPU_SH2_H_ */

41
arch/sh/include/asm/cpu_sh7203.h
View file

@ -1,41 +0,0 @@
#ifndef _ASM_CPU_SH7203_H_
#define _ASM_CPU_SH7203_H_
/* Cache */
#define CCR1 0xFFFC1000
#define CCR CCR1
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PETCR 0xA4050106
/* Port Data Registers */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
/* BSC */
/* SDRAM controller */
/* SCIF */
#define SCSMR_0 0xFFFE8000
#define SCIF0_BASE SCSMR_0
/* Timer(CMT) */
#define CMSTR 0xFFFEC000
#define CMCSR_0 0xFFFEC002
#define CMCNT_0 0xFFFEC004
#define CMCOR_0 0xFFFEC006
#define CMCSR_1 0xFFFEC008
#define CMCNT_1 0xFFFEC00A
#define CMCOR_1 0xFFFEC00C
/* On chip oscillator circuits */
#define FRQCR 0xA415FF80
#define WTCNT 0xA415FF84
#define WTCSR 0xA415FF86
#endif /* _ASM_CPU_SH7203_H_ */

41
arch/sh/include/asm/cpu_sh7264.h
View file

@ -1,41 +0,0 @@
#ifndef _ASM_CPU_SH7264_H_
#define _ASM_CPU_SH7264_H_
/* Cache */
#define CCR1 0xFFFC1000
#define CCR CCR1
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PETCR 0xA4050106
/* Port Data Registers */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
/* BSC */
/* SDRAM controller */
/* SCIF */
#define SCSMR_3 0xFFFE9800
#define SCIF3_BASE SCSMR_3
/* Timer(CMT) */
#define CMSTR 0xFFFEC000
#define CMCSR_0 0xFFFEC002
#define CMCNT_0 0xFFFEC004
#define CMCOR_0 0xFFFEC006
#define CMCSR_1 0xFFFEC008
#define CMCNT_1 0xFFFEC00A
#define CMCOR_1 0xFFFEC00C
/* On chip oscillator circuits */
#define FRQCR 0xA415FF80
#define WTCNT 0xA415FF84
#define WTCSR 0xA415FF86
#endif /* _ASM_CPU_SH7264_H_ */

26
arch/sh/include/asm/cpu_sh7269.h
View file

@ -1,26 +0,0 @@
#ifndef _ASM_CPU_SH7269_H_
#define _ASM_CPU_SH7269_H_
/* Cache */
#define CCR1 0xFFFC1000
#define CCR CCR1
/* SCIF */
#define SCSMR_0 0xE8007000
#define SCIF0_BASE SCSMR_0
#define SCSMR_1 0xE8007800
#define SCIF1_BASE SCSMR_1
#define SCSMR_2 0xE8008000
#define SCIF2_BASE SCSMR_2
#define SCSMR_3 0xE8008800
#define SCIF3_BASE SCSMR_3
#define SCSMR_7 0xE800A800
#define SCIF7_BASE SCSMR_7
/* Timer(CMT) */
#define CMSTR 0xFFFEC000
#define CMCSR_0 0xFFFEC002
#define CMCNT_0 0xFFFEC004
#define CMCOR_0 0xFFFEC006
#endif /* _ASM_CPU_SH7269_H_ */

4
arch/sh/include/asm/processor.h
View file

@ -1,8 +1,6 @@
#ifndef _ASM_SH_PROCESSOR_H_
#define _ASM_SH_PROCESSOR_H_
#if defined(CONFIG_CPU_SH2)
# include <asm/cpu_sh2.h>
#elif defined(CONFIG_CPU_SH3)
#if defined(CONFIG_CPU_SH3)
# include <asm/cpu_sh3.h>
#elif defined(CONFIG_CPU_SH4)
# include <asm/cpu_sh4.h>

4
arch/sh/lib/Makefile
View file

@ -7,11 +7,7 @@ extra-y += start.o
obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
ifeq ($(CONFIG_CPU_SH2),y)
obj-y += time_sh2.o
else
obj-y += time.o
endif
obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
udivsi3-y := udivsi3_i4i-Os.o

6
arch/sh/lib/start.S
View file

@ -12,12 +12,6 @@
.global _start
_start:
#ifdef CONFIG_CPU_SH2
.long 0x00000010 /* Ppower ON reset PC*/
.long 0x00000000
.long 0x00000010 /* Manual reset PC */
.long 0x00000000
#endif
mov.l ._lowlevel_init, r0
100: bsrf r0
nop

9
drivers/serial/serial_sh.h
View file

@ -106,14 +106,7 @@ struct uart_port {
/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
# define SCSCR_INIT(port) 0x3a
#elif defined(CONFIG_CPU_SH7203) || \
defined(CONFIG_CPU_SH7264)
# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1)
#elif defined(CONFIG_RZA1)
# define SCSPTR0 0xe8007020 /* 16 bit SCIF */
# define SCSPTR1 0xe8007820 /* 16 bit SCIF */
# define SCSPTR2 0xe8008020 /* 16 bit SCIF */

3
scripts/config_whitelist.txt
View file

@ -270,9 +270,6 @@ CONFIG_CPU_PXA26X
CONFIG_CPU_PXA27X
CONFIG_CPU_PXA300
CONFIG_CPU_R8000
CONFIG_CPU_SH7203
CONFIG_CPU_SH7264
CONFIG_CPU_SH7269
CONFIG_CPU_SH7706
CONFIG_CPU_SH7720
CONFIG_CPU_SH7722