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https://github.com/Fishwaldo/u-boot.git
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x86: Move common PCH code into a common place
The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
f215287bd5
commit
7e4a6ae62c
6 changed files with 99 additions and 84 deletions
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@ -11,4 +11,5 @@ obj-$(CONFIG_HAVE_MRC) += me_status.o
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ifndef CONFIG_TARGET_EFI
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obj-y += microcode.o
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endif
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obj-y += pch.o
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obj-$(CONFIG_HAVE_MRC) += report_platform.o
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25
arch/x86/cpu/intel_common/pch.c
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25
arch/x86/cpu/intel_common/pch.c
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@ -0,0 +1,25 @@
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/pch_common.h>
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u32 pch_common_sir_read(struct udevice *dev, int idx)
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{
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u32 data;
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dm_pci_write_config32(dev, SATA_SIRI, idx);
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dm_pci_read_config32(dev, SATA_SIRD, &data);
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return data;
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}
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void pch_common_sir_write(struct udevice *dev, int idx, u32 value)
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{
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dm_pci_write_config32(dev, SATA_SIRI, idx);
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dm_pci_write_config32(dev, SATA_SIRD, value);
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}
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@ -21,6 +21,7 @@
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#include <asm/intel_regs.h>
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#include <asm/io.h>
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#include <asm/lapic.h>
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#include <asm/lpc_common.h>
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#include <asm/microcode.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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@ -9,28 +9,13 @@
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#include <dm.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <asm/pch_common.h>
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#include <asm/pci.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/bd82x6x.h>
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DECLARE_GLOBAL_DATA_PTR;
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static inline u32 sir_read(struct udevice *dev, int idx)
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{
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u32 data;
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dm_pci_write_config32(dev, SATA_SIRI, idx);
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dm_pci_read_config32(dev, SATA_SIRD, &data);
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return data;
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}
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static inline void sir_write(struct udevice *dev, int idx, u32 value)
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{
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dm_pci_write_config32(dev, SATA_SIRI, idx);
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dm_pci_write_config32(dev, SATA_SIRD, value);
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}
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static void common_sata_init(struct udevice *dev, unsigned int port_map)
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{
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u32 reg32;
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@ -177,27 +162,27 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
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pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
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/* Additional Programming Requirements */
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sir_write(dev, 0x04, 0x00001600);
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sir_write(dev, 0x28, 0xa0000033);
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reg32 = sir_read(dev, 0x54);
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pch_common_sir_write(dev, 0x04, 0x00001600);
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pch_common_sir_write(dev, 0x28, 0xa0000033);
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reg32 = pch_common_sir_read(dev, 0x54);
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reg32 &= 0xff000000;
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reg32 |= 0x5555aa;
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sir_write(dev, 0x54, reg32);
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sir_write(dev, 0x64, 0xcccc8484);
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reg32 = sir_read(dev, 0x68);
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pch_common_sir_write(dev, 0x54, reg32);
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pch_common_sir_write(dev, 0x64, 0xcccc8484);
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reg32 = pch_common_sir_read(dev, 0x68);
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reg32 &= 0xffff0000;
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reg32 |= 0xcccc;
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sir_write(dev, 0x68, reg32);
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reg32 = sir_read(dev, 0x78);
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pch_common_sir_write(dev, 0x68, reg32);
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reg32 = pch_common_sir_read(dev, 0x78);
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reg32 &= 0x0000ffff;
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reg32 |= 0x88880000;
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sir_write(dev, 0x78, reg32);
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sir_write(dev, 0x84, 0x001c7000);
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sir_write(dev, 0x88, 0x88338822);
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sir_write(dev, 0xa0, 0x001c7000);
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sir_write(dev, 0xc4, 0x0c0c0c0c);
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sir_write(dev, 0xc8, 0x0c0c0c0c);
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sir_write(dev, 0xd4, 0x10000000);
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pch_common_sir_write(dev, 0x78, reg32);
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pch_common_sir_write(dev, 0x84, 0x001c7000);
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pch_common_sir_write(dev, 0x88, 0x88338822);
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pch_common_sir_write(dev, 0xa0, 0x001c7000);
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pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
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pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
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pch_common_sir_write(dev, 0xd4, 0x10000000);
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pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
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pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
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@ -69,8 +69,6 @@
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#define RTC_POWER_FAILED (1 << 1)
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#define SLEEP_AFTER_POWER_FAIL (1 << 0)
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#define PMBASE 0x40
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#define ACPI_CNTL 0x44
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#define BIOS_CNTL 0xDC
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#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
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#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
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@ -99,60 +97,11 @@
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#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
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#define GPIO_ROUT 0xb8
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#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
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#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */
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#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */
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#define LPC_EN 0x82 /* LPC IF Enables Register */
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#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
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#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
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#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
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#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
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#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
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#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
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#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
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#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
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#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
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#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */
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#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
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#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
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#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
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#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
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#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
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#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */
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#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */
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#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */
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#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */
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#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */
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#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */
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#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */
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#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */
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/* PCI Configuration Space (D31:F1): IDE */
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#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
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#define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2)
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#define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5)
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#define INTR_LN 0x3c
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#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
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#define IDE_DECODE_ENABLE (1 << 15)
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#define IDE_SITRE (1 << 14)
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#define IDE_ISP_5_CLOCKS (0 << 12)
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#define IDE_ISP_4_CLOCKS (1 << 12)
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#define IDE_ISP_3_CLOCKS (2 << 12)
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#define IDE_RCT_4_CLOCKS (0 << 8)
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#define IDE_RCT_3_CLOCKS (1 << 8)
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#define IDE_RCT_2_CLOCKS (2 << 8)
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#define IDE_RCT_1_CLOCKS (3 << 8)
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#define IDE_DTE1 (1 << 7)
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#define IDE_PPE1 (1 << 6)
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#define IDE_IE1 (1 << 5)
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#define IDE_TIME1 (1 << 4)
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#define IDE_DTE0 (1 << 3)
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#define IDE_PPE0 (1 << 2)
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#define IDE_IE0 (1 << 1)
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#define IDE_TIME0 (1 << 0)
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#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
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#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
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#define IDE_SSDE1 (1 << 3)
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#define IDE_SSDE0 (1 << 2)
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@ -337,9 +286,7 @@
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(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
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((b) << DIR_IBR) | ((a) << DIR_IAR))
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#define RC 0x3400 /* 32bit */
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#define HPTC 0x3404 /* 32bit */
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#define GCS 0x3410 /* 32bit */
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#define BUC 0x3414 /* 32bit */
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#define PCH_DISABLE_GBE (1 << 5)
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#define FD 0x3418 /* 32bit */
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56
arch/x86/include/asm/pch_common.h
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56
arch/x86/include/asm/pch_common.h
Normal file
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@ -0,0 +1,56 @@
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __asm_pch_common_h
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#define __asm_pch_common_h
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/* Common Intel SATA registers */
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#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
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#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
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#define SATA_SP 0xd0 /* Scratchpad */
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#define INTR_LN 0x3c
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#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
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#define IDE_DECODE_ENABLE (1 << 15)
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#define IDE_SITRE (1 << 14)
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#define IDE_ISP_5_CLOCKS (0 << 12)
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#define IDE_ISP_4_CLOCKS (1 << 12)
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#define IDE_ISP_3_CLOCKS (2 << 12)
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#define IDE_RCT_4_CLOCKS (0 << 8)
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#define IDE_RCT_3_CLOCKS (1 << 8)
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#define IDE_RCT_2_CLOCKS (2 << 8)
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#define IDE_RCT_1_CLOCKS (3 << 8)
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#define IDE_DTE1 (1 << 7)
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#define IDE_PPE1 (1 << 6)
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#define IDE_IE1 (1 << 5)
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#define IDE_TIME1 (1 << 4)
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#define IDE_DTE0 (1 << 3)
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#define IDE_PPE0 (1 << 2)
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#define IDE_IE0 (1 << 1)
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#define IDE_TIME0 (1 << 0)
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#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
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#define SERIRQ_CNTL 0x64
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/**
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* pch_common_sir_read() - Read from a SATA indexed register
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*
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* @dev: SATA device
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* @idx: Register index to read
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* @return value read from register
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*/
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u32 pch_common_sir_read(struct udevice *dev, int idx);
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/**
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* pch_common_sir_write() - Write to a SATA indexed register
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*
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* @dev: SATA device
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* @idx: Register index to write
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* @value: Value to write
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*/
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void pch_common_sir_write(struct udevice *dev, int idx, u32 value);
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#endif
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