mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
omap5: uevm: convert to device model
Convert omap5 uevm board to device model. Signed-off-by: Tero Kristo <t-kristo@ti.com>
This commit is contained in:
Tero Kristo
Lokesh Vutla
parent
8f1ed2e4ed
commit
803e9a1f28
3 changed files with 64 additions and 73 deletions
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@ -7,6 +7,7 @@
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* Based on "dra7.dtsi"
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*/
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#ifdef CONFIG_DRA7XX
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/{
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chosen {
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tick-timer = &timer2;
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@ -105,3 +106,44 @@
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&i2c1 {
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u-boot,dm-spl;
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};
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#else /* OMAP54XX */
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&l4_cfg {
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segment@0 {
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/* SCM Core */
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target-module@2000 {
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compatible = "simple-bus";
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};
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/* USB HS */
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target-module@64000 {
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compatible = "simple-bus";
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};
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};
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};
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&l4_per {
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segment@0 {
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/* UART3 */
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target-module@20000 {
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compatible = "simple-bus";
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};
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/* I2C1 */
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target-module@70000 {
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compatible = "simple-bus";
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};
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/* MMC1 */
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target-module@9c000 {
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compatible = "simple-bus";
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};
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/* MMC2 */
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target-module@b4000 {
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compatible = "simple-bus";
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};
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};
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};
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#endif
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@ -12,6 +12,7 @@
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#include <asm/arch/omap.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mmc_host_def.h>
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#include <serial.h>
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#include <tca642x.h>
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#include <usb.h>
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#include <linux/delay.h>
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@ -149,40 +150,22 @@ int board_init(void)
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return 0;
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}
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#if defined(CONFIG_SPL_OS_BOOT)
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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return 0;
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}
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#endif /* CONFIG_SPL_OS_BOOT */
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int board_eth_init(bd_t *bis)
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{
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return 0;
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}
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#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
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static void enable_host_clocks(void)
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{
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int auxclk;
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int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
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OPTFCLKEN_HSIC480M_P3_CLK |
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OPTFCLKEN_HSIC60M_P2_CLK |
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OPTFCLKEN_HSIC480M_P2_CLK |
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OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
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/* Enable port 2 and 3 clocks*/
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setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
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/* Enable port 2 and 3 usb host ports tll clocks*/
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setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
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(OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
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#ifdef CONFIG_USB_XHCI_OMAP
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/* Enable the USB OTG Super speed clocks */
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setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
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(OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
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#endif
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auxclk = readl((*prcm)->scrm_auxclk1);
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/* Request auxilary clock */
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auxclk |= AUXCLK_ENABLE_MASK;
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writel(auxclk, (*prcm)->scrm_auxclk1);
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}
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#endif
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/**
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* @brief misc_init_r - Configure EVM board specific configurations
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* such as power configurations, ethernet initialization as phase2 of
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@ -223,45 +206,6 @@ int board_mmc_init(bd_t *bis)
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}
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#endif
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#ifdef CONFIG_USB_EHCI_HCD
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
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.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
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.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
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};
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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int ret;
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enable_host_clocks();
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ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
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if (ret < 0) {
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puts("Failed to initialize ehci\n");
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return ret;
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}
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return 0;
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}
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int ehci_hcd_stop(void)
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{
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return omap_ehci_hcd_stop();
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}
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void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
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{
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/* The LAN9730 needs to be reset after the port power has been set. */
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if (port == 3) {
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gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
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udelay(10);
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gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
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}
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}
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#endif
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#ifdef CONFIG_USB_XHCI_OMAP
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/**
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* @brief board_usb_init - Configure EVM board specific configurations
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@ -276,8 +220,6 @@ int board_usb_init(int index, enum usb_init_type init)
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ret = palmas_enable_ss_ldo();
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#endif
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enable_host_clocks();
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return 0;
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}
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#endif
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@ -2,6 +2,7 @@ CONFIG_ARM=y
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CONFIG_ARCH_OMAP2PLUS=y
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CONFIG_OMAP54XX=y
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CONFIG_TARGET_OMAP5_UEVM=y
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CONFIG_DEFAULT_DEVICE_TREE="omap5-uevm"
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CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
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CONFIG_SPL=y
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CONFIG_ENV_OFFSET_REDUND=0x280000
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@ -10,6 +11,7 @@ CONFIG_SPL_TEXT_BASE=0x40300000
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CONFIG_DISTRO_DEFAULTS=y
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# CONFIG_USE_BOOTCOMMAND is not set
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CONFIG_SYS_CONSOLE_INFO_QUIET=y
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CONFIG_DEFAULT_FDT_FILE="omap5-uevm.dtb"
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CONFIG_VERSION_VARIABLE=y
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# CONFIG_SPL_NAND_SUPPORT is not set
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CONFIG_SPL_OS_BOOT=y
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@ -20,14 +22,17 @@ CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
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CONFIG_DM=y
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CONFIG_DM_MMC=y
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CONFIG_AHCI=y
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CONFIG_SCSI_AHCI=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_RAM=y
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@ -37,9 +42,9 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_SCSI=y
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CONFIG_CONS_INDEX=3
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_OMAP3_SPI=y
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# CONFIG_SPI is not set
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_OMAP=y
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@ -53,3 +58,5 @@ CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_SMSC95XX=y
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CONFIG_FAT_WRITE=y
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CONFIG_OF_LIBFDT=y
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CONFIG_SYS_MALLOC_F_LEN=0x4000
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CONFIG_DM_ETH=y
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