mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 05:01:30 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-uniphier
This commit is contained in:
Tom Rini
commit
823ecd72bb
46 changed files with 1033 additions and 227 deletions
|
|
@ -689,6 +689,7 @@ config TARGET_COLIBRI_PXA270
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|||
|
||||
config ARCH_UNIPHIER
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bool "Socionext UniPhier SoCs"
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||||
select CLK_UNIPHIER
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select CPU_V7
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||||
select SUPPORT_SPL
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select SPL
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||||
|
|
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|||
|
|
@ -59,7 +59,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
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dtb-$(CONFIG_ARCH_UNIPHIER) += \
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uniphier-ph1-ld4-ref.dtb \
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uniphier-ph1-ld6b-ref.dtb \
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uniphier-ph1-pro4-ace.dtb \
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uniphier-ph1-pro4-ref.dtb \
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||||
uniphier-ph1-pro4-sanji.dtb \
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||||
uniphier-ph1-pro5-4kbox.dtb \
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||||
uniphier-ph1-sld3-ref.dtb \
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||||
uniphier-ph1-sld8-ref.dtb \
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||||
|
|
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|||
|
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@ -9,6 +9,13 @@
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|||
/include/ "skeleton.dtsi"
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||||
/ {
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clocks {
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refclk: ref {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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@ -67,6 +74,18 @@
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reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
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};
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mio: mioctrl@59810000 {
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/* specify compatible in each SoC DTSI */
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reg = <0x59810000 0x800>;
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#clock-cells = <1>;
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};
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peri: perictrl@59820000 {
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/* specify compatible in each SoC DTSI */
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reg = <0x59820000 0x200>;
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#clock-cells = <1>;
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};
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timer@60000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x60000200 0x20>;
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@ -94,6 +113,14 @@
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reg = <0x5f801000 0xe00>;
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};
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sysctrl: sysctrl@61840000 {
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/* specify compatible in each SoC DTSI */
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reg = <0x61840000 0x4000>;
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#clock-cells = <1>;
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clock-names = "ref";
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clocks = <&refclk>;
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};
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nand: nand@68000000 {
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compatible = "denali,denali-nand-dt";
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reg = <0x68000000 0x20>, <0x68100000 0x1000>;
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|
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@ -115,6 +115,7 @@
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interrupts = <0 80 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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clocks = <&mio 3>, <&mio 6>;
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};
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usb1: usb@5a810100 {
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@ -124,6 +125,7 @@
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interrupts = <0 81 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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clocks = <&mio 4>, <&mio 6>;
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};
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usb2: usb@5a820100 {
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@ -133,9 +135,14 @@
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interrupts = <0 82 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb2>;
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clocks = <&mio 5>, <&mio 6>;
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};
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};
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&refclk {
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clock-frequency = <24576000>;
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};
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&serial0 {
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clock-frequency = <36864000>;
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};
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@ -153,6 +160,22 @@
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clock-frequency = <36864000>;
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};
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||||
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&mio {
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compatible = "socionext,ph1-ld4-mioctrl";
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clock-names = "stdmac", "ehci";
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clocks = <&sysctrl 10>, <&sysctrl 18>;
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};
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|
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&peri {
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compatible = "socionext,ph1-ld4-perictrl";
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||||
clock-names = "uart", "i2c";
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clocks = <&sysctrl 3>, <&sysctrl 4>;
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||||
};
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|
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&pinctrl {
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compatible = "socionext,ph1-ld4-pinctrl", "syscon";
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||||
};
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|
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&sysctrl {
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compatible = "socionext,ph1-ld4-sysctrl";
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};
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|
|
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105
arch/arm/dts/uniphier-ph1-pro4-ace.dts
Normal file
105
arch/arm/dts/uniphier-ph1-pro4-ace.dts
Normal file
|
|
@ -0,0 +1,105 @@
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|||
/*
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||||
* Device Tree Source for UniPhier PH1-Pro4 Ace Board
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*
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
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||||
*
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||||
* SPDX-License-Identifier: GPL-2.0+ X11
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||||
*/
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||||
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/dts-v1/;
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/include/ "uniphier-ph1-pro4.dtsi"
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||||
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||||
/ {
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||||
model = "UniPhier PH1-Pro4 Ace Board";
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compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4";
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||||
|
||||
memory {
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device_type = "memory";
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||||
reg = <0x80000000 0x40000000>;
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||||
};
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chosen {
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stdout-path = "serial0:115200n8";
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||||
};
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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||||
i2c5 = &i2c5;
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||||
i2c6 = &i2c6;
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||||
};
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||||
};
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||||
&serial0 {
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||||
status = "okay";
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};
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||||
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||||
&serial1 {
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status = "okay";
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};
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||||
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||||
&serial2 {
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status = "okay";
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||||
};
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&i2c0 {
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status = "okay";
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||||
eeprom {
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compatible = "24c64", "i2c-eeprom";
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reg = <0x54>;
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||||
u-boot,i2c-offset-len = <2>;
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};
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};
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&i2c1 {
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status = "okay";
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};
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||||
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&i2c2 {
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status = "okay";
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};
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||||
&i2c3 {
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status = "okay";
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||||
};
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|
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&usb0 {
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status = "okay";
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};
|
||||
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||||
&usb1 {
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status = "okay";
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||||
};
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||||
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||||
&usb2 {
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status = "okay";
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||||
};
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||||
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&usb3 {
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status = "okay";
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};
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/* for U-Boot only */
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/ {
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soc {
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u-boot,dm-pre-reloc;
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};
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};
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||||
&serial0 {
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u-boot,dm-pre-reloc;
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||||
};
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||||
&pinctrl {
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||||
u-boot,dm-pre-reloc;
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||||
};
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||||
&pinctrl_uart0 {
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||||
u-boot,dm-pre-reloc;
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||||
};
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||||
100
arch/arm/dts/uniphier-ph1-pro4-sanji.dts
Normal file
100
arch/arm/dts/uniphier-ph1-pro4-sanji.dts
Normal file
|
|
@ -0,0 +1,100 @@
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|||
/*
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||||
* Device Tree Source for UniPhier PH1-Pro4 Sanji Board
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*
|
||||
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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||||
* SPDX-License-Identifier: GPL-2.0+ X11
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*/
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/dts-v1/;
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/include/ "uniphier-ph1-pro4.dtsi"
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/ {
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model = "UniPhier PH1-Pro4 Sanji Board";
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compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4";
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memory {
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device_type = "memory";
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reg = <0x80000000 0x80000000>;
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||||
};
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||||
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||||
chosen {
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||||
stdout-path = "serial0:115200n8";
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||||
};
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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};
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};
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&serial0 {
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status = "okay";
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};
|
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|
||||
&serial1 {
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status = "okay";
|
||||
};
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|
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&i2c0 {
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status = "okay";
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eeprom {
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compatible = "24c64", "i2c-eeprom";
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reg = <0x54>;
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u-boot,i2c-offset-len = <2>;
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};
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};
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|
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&i2c1 {
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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||||
};
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|
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&i2c3 {
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status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
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status = "okay";
|
||||
};
|
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|
||||
&usb1 {
|
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status = "okay";
|
||||
};
|
||||
|
||||
&usb2 {
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status = "okay";
|
||||
};
|
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|
||||
&usb3 {
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status = "okay";
|
||||
};
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||||
|
||||
/* for U-Boot only */
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/ {
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soc {
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u-boot,dm-pre-reloc;
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};
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};
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||||
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&serial0 {
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u-boot,dm-pre-reloc;
|
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};
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||||
|
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&pinctrl {
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u-boot,dm-pre-reloc;
|
||||
};
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||||
|
||||
&pinctrl_uart0 {
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u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
@ -147,6 +147,7 @@
|
|||
interrupts = <0 80 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
clocks = <&mio 3>, <&mio 6>;
|
||||
};
|
||||
|
||||
usb3: usb@5a810100 {
|
||||
|
|
@ -156,6 +157,7 @@
|
|||
interrupts = <0 81 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb3>;
|
||||
clocks = <&mio 4>, <&mio 6>;
|
||||
};
|
||||
|
||||
usb0: usb@65a00000 {
|
||||
|
|
@ -177,6 +179,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&refclk {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
clock-frequency = <73728000>;
|
||||
};
|
||||
|
|
@ -193,6 +199,22 @@
|
|||
clock-frequency = <73728000>;
|
||||
};
|
||||
|
||||
&mio {
|
||||
compatible = "socionext,ph1-pro4-mioctrl";
|
||||
clock-names = "stdmac", "ehci";
|
||||
clocks = <&sysctrl 10>, <&sysctrl 18>;
|
||||
};
|
||||
|
||||
&peri {
|
||||
compatible = "socionext,ph1-pro4-perictrl";
|
||||
clock-names = "uart", "fi2c";
|
||||
clocks = <&sysctrl 3>, <&sysctrl 4>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "socionext,ph1-pro4-pinctrl", "syscon";
|
||||
};
|
||||
|
||||
&sysctrl {
|
||||
compatible = "socionext,ph1-pro4-sysctrl";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -171,6 +171,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&refclk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
clock-frequency = <73728000>;
|
||||
};
|
||||
|
|
@ -187,6 +191,22 @@
|
|||
clock-frequency = <73728000>;
|
||||
};
|
||||
|
||||
&mio {
|
||||
compatible = "socionext,ph1-pro5-mioctrl";
|
||||
clock-names = "stdmac";
|
||||
clocks = <&sysctrl 10>;
|
||||
};
|
||||
|
||||
&peri {
|
||||
compatible = "socionext,ph1-pro5-perictrl";
|
||||
clock-names = "uart", "fi2c";
|
||||
clocks = <&sysctrl 3>, <&sysctrl 4>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "socionext,ph1-pro5-pinctrl", "syscon";
|
||||
};
|
||||
|
||||
&sysctrl {
|
||||
compatible = "socionext,ph1-pro5-sysctrl";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -30,6 +30,12 @@
|
|||
};
|
||||
|
||||
clocks {
|
||||
refclk: ref {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
arm_timer_clk: arm_timer_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
|
|
@ -172,11 +178,20 @@
|
|||
reg = <0x59800000 0x2000>;
|
||||
};
|
||||
|
||||
mio: mioctrl@59810000 {
|
||||
compatible = "socionext,ph1-sld3-mioctrl";
|
||||
reg = <0x59810000 0x800>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "stdmac", "ehci";
|
||||
clocks = <&sysctrl 10>, <&sysctrl 18>;
|
||||
};
|
||||
|
||||
usb0: usb@5a800100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a800100 0x100>;
|
||||
interrupts = <0 80 4>;
|
||||
clocks = <&mio 3>, <&mio 6>;
|
||||
};
|
||||
|
||||
usb1: usb@5a810100 {
|
||||
|
|
@ -184,6 +199,7 @@
|
|||
status = "disabled";
|
||||
reg = <0x5a810100 0x100>;
|
||||
interrupts = <0 81 4>;
|
||||
clocks = <&mio 4>, <&mio 6>;
|
||||
};
|
||||
|
||||
usb2: usb@5a820100 {
|
||||
|
|
@ -191,6 +207,7 @@
|
|||
status = "disabled";
|
||||
reg = <0x5a820100 0x100>;
|
||||
interrupts = <0 82 4>;
|
||||
clocks = <&mio 5>, <&mio 6>;
|
||||
};
|
||||
|
||||
usb3: usb@5a830100 {
|
||||
|
|
@ -198,6 +215,15 @@
|
|||
status = "disabled";
|
||||
reg = <0x5a830100 0x100>;
|
||||
interrupts = <0 83 4>;
|
||||
clocks = <&mio 7>, <&mio 6>;
|
||||
};
|
||||
|
||||
sysctrl: sysctrl@f1840000 {
|
||||
compatible = "socionext,ph1-sld3-sysctrl";
|
||||
reg = <0xf1840000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "ref";
|
||||
clocks = <&refclk>;
|
||||
};
|
||||
|
||||
nand: nand@f8000000 {
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@
|
|||
interrupts = <0 80 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
clocks = <&mio 3>, <&mio 6>;
|
||||
};
|
||||
|
||||
usb1: usb@5a810100 {
|
||||
|
|
@ -124,6 +125,7 @@
|
|||
interrupts = <0 81 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
clocks = <&mio 4>, <&mio 6>;
|
||||
};
|
||||
|
||||
usb2: usb@5a820100 {
|
||||
|
|
@ -133,9 +135,14 @@
|
|||
interrupts = <0 82 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
clocks = <&mio 5>, <&mio 6>;
|
||||
};
|
||||
};
|
||||
|
||||
&refclk {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
clock-frequency = <80000000>;
|
||||
};
|
||||
|
|
@ -153,6 +160,22 @@
|
|||
clock-frequency = <80000000>;
|
||||
};
|
||||
|
||||
&mio {
|
||||
compatible = "socionext,ph1-sld8-mioctrl";
|
||||
clock-names = "stdmac", "ehci";
|
||||
clocks = <&sysctrl 10>, <&sysctrl 18>;
|
||||
};
|
||||
|
||||
&peri {
|
||||
compatible = "socionext,ph1-sld8-perictrl";
|
||||
clock-names = "uart", "i2c";
|
||||
clocks = <&sysctrl 3>, <&sysctrl 4>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "socionext,ph1-sld8-pinctrl", "syscon";
|
||||
};
|
||||
|
||||
&sysctrl {
|
||||
compatible = "socionext,ph1-sld8-sysctrl";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
i2c0 = &i2c0;
|
||||
i2c2 = &i2c2;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
|
|
@ -39,6 +40,16 @@
|
|||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
eeprom {
|
||||
compatible = "24c64", "i2c-eeprom";
|
||||
reg = <0x54>;
|
||||
u-boot,i2c-offset-len = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
|
|
|
|||
|
|
@ -182,6 +182,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&refclk {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
clock-frequency = <88900000>;
|
||||
};
|
||||
|
|
@ -198,6 +202,22 @@
|
|||
clock-frequency = <88900000>;
|
||||
};
|
||||
|
||||
&mio {
|
||||
compatible = "socionext,proxstream2-mioctrl";
|
||||
clock-names = "stdmac";
|
||||
clocks = <&sysctrl 10>;
|
||||
};
|
||||
|
||||
&peri {
|
||||
compatible = "socionext,proxstream2-perictrl";
|
||||
clock-names = "uart", "fi2c";
|
||||
clocks = <&sysctrl 3>, <&sysctrl 4>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "socionext,proxstream2-pinctrl", "syscon";
|
||||
};
|
||||
|
||||
&sysctrl {
|
||||
compatible = "socionext,proxstream2-sysctrl";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ enum {
|
|||
BOOT_DEVICE_NOR,
|
||||
BOOT_DEVICE_UART,
|
||||
BOOT_DEVICE_SPI,
|
||||
BOOT_DEVICE_USB,
|
||||
BOOT_DEVICE_SATA,
|
||||
BOOT_DEVICE_I2C,
|
||||
BOOT_DEVICE_BOARD,
|
||||
|
|
|
|||
|
|
@ -5,9 +5,8 @@
|
|||
ifdef CONFIG_SPL_BUILD
|
||||
|
||||
obj-y += lowlevel_init.o
|
||||
obj-y += init_page_table.o
|
||||
|
||||
obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ dram/
|
||||
obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/
|
||||
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
|
||||
|
||||
obj-$(CONFIG_DEBUG_LL) += debug_ll.o
|
||||
|
|
@ -33,5 +32,6 @@ obj-y += timer.o
|
|||
obj-y += boards.o
|
||||
obj-y += soc_info.o
|
||||
obj-y += boot-mode/
|
||||
obj-y += dram/
|
||||
|
||||
obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
|
||||
|
|
|
|||
|
|
@ -11,6 +11,8 @@
|
|||
#include <linux/io.h>
|
||||
#include <../drivers/mtd/nand/denali.h>
|
||||
|
||||
#include "boot-mode/boot-device.h"
|
||||
|
||||
static void nand_denali_wp_disable(void)
|
||||
{
|
||||
#ifdef CONFIG_NAND_DENALI
|
||||
|
|
@ -35,7 +37,9 @@ static const struct uniphier_fdt_file uniphier_fdt_files[] = {
|
|||
{ "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", },
|
||||
{ "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", },
|
||||
{ "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", },
|
||||
{ "socionext,ph1-pro4-ace", "uniphier-ph1-pro4-ace.dtb", },
|
||||
{ "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", },
|
||||
{ "socionext,ph1-pro4-sanji", "uniphier-ph1-pro4-sanji.dtb", },
|
||||
{ "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", },
|
||||
{ "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", },
|
||||
{ "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", },
|
||||
|
|
@ -62,7 +66,7 @@ int board_late_init(void)
|
|||
{
|
||||
puts("MODE: ");
|
||||
|
||||
switch (spl_boot_device()) {
|
||||
switch (spl_boot_device_raw()) {
|
||||
case BOOT_DEVICE_MMC1:
|
||||
printf("eMMC Boot\n");
|
||||
setenv("bootmode", "emmcboot");
|
||||
|
|
@ -76,6 +80,10 @@ int board_late_init(void)
|
|||
printf("NOR Boot\n");
|
||||
setenv("bootmode", "norboot");
|
||||
break;
|
||||
case BOOT_DEVICE_USB:
|
||||
printf("USB Boot\n");
|
||||
setenv("bootmode", "usbboot");
|
||||
break;
|
||||
default:
|
||||
printf("Unsupported Boot Mode\n");
|
||||
return -1;
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ static const struct uniphier_board_data ph1_ld4_data = {
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
|
||||
/* 1GB RAM board */
|
||||
static const struct uniphier_board_data ph1_pro4_data = {
|
||||
.dram_ch0_base = 0x80000000,
|
||||
.dram_ch0_size = 0x20000000,
|
||||
|
|
@ -49,6 +50,17 @@ static const struct uniphier_board_data ph1_pro4_data = {
|
|||
.dram_ch1_width = 32,
|
||||
.dram_freq = 1600,
|
||||
};
|
||||
|
||||
/* 2GB RAM board */
|
||||
static const struct uniphier_board_data ph1_pro4_2g_data = {
|
||||
.dram_ch0_base = 0x80000000,
|
||||
.dram_ch0_size = 0x40000000,
|
||||
.dram_ch0_width = 32,
|
||||
.dram_ch1_base = 0xc0000000,
|
||||
.dram_ch1_size = 0x40000000,
|
||||
.dram_ch1_width = 32,
|
||||
.dram_freq = 1600,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
|
||||
|
|
@ -118,6 +130,8 @@ static const struct uniphier_board_id uniphier_boards[] = {
|
|||
{ "socionext,ph1-ld4", &ph1_ld4_data, },
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
|
||||
{ "socionext,ph1-pro4-ace", &ph1_pro4_2g_data, },
|
||||
{ "socionext,ph1-pro4-sanji", &ph1_pro4_2g_data, },
|
||||
{ "socionext,ph1-pro4", &ph1_pro4_data, },
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
|
||||
|
|
|
|||
|
|
@ -22,4 +22,6 @@ void ph1_ld4_boot_mode_show(void);
|
|||
void ph1_pro5_boot_mode_show(void);
|
||||
void proxstream2_boot_mode_show(void);
|
||||
|
||||
u32 spl_boot_device_raw(void);
|
||||
|
||||
#endif /* _ASM_BOOT_DEVICE_H_ */
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ static struct boot_device_info boot_device_table[] = {
|
|||
{BOOT_DEVICE_NONE, "Reserved"},
|
||||
};
|
||||
|
||||
int get_boot_mode_sel(void)
|
||||
static int get_boot_mode_sel(void)
|
||||
{
|
||||
return (readl(SG_PINMON0) >> 1) & 0x1f;
|
||||
}
|
||||
|
|
@ -55,6 +55,9 @@ u32 proxstream2_boot_device(void)
|
|||
{
|
||||
int boot_mode;
|
||||
|
||||
if (readl(SG_PINMON0) & BIT(6))
|
||||
return BOOT_DEVICE_USB;
|
||||
|
||||
boot_mode = get_boot_mode_sel();
|
||||
|
||||
return boot_device_table[boot_mode].type;
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
#include "../soc-info.h"
|
||||
#include "boot-device.h"
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
u32 spl_boot_device_raw(void)
|
||||
{
|
||||
if (boot_is_swapped())
|
||||
return BOOT_DEVICE_NOR;
|
||||
|
|
@ -43,3 +43,12 @@ u32 spl_boot_device(void)
|
|||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
u32 ret;
|
||||
|
||||
ret = spl_boot_device_raw();
|
||||
|
||||
return ret == BOOT_DEVICE_USB ? BOOT_DEVICE_NOR : ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ void ph1_ld4_clk_init(void)
|
|||
#ifdef CONFIG_UNIPHIER_ETH
|
||||
tmp |= SC_RSTCTRL_NRST_ETHER;
|
||||
#endif
|
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
tmp |= SC_RSTCTRL_NRST_STDMAC;
|
||||
#endif
|
||||
#ifdef CONFIG_NAND_DENALI
|
||||
|
|
@ -32,7 +32,7 @@ void ph1_ld4_clk_init(void)
|
|||
#ifdef CONFIG_UNIPHIER_ETH
|
||||
tmp |= SC_CLKCTRL_CEN_ETHER;
|
||||
#endif
|
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
|
||||
#endif
|
||||
#ifdef CONFIG_NAND_DENALI
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ void ph1_pro4_clk_init(void)
|
|||
#ifdef CONFIG_UNIPHIER_ETH
|
||||
tmp |= SC_RSTCTRL_NRST_ETHER;
|
||||
#endif
|
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
tmp |= SC_RSTCTRL_NRST_STDMAC;
|
||||
#endif
|
||||
#ifdef CONFIG_NAND_DENALI
|
||||
|
|
@ -47,7 +47,7 @@ void ph1_pro4_clk_init(void)
|
|||
#ifdef CONFIG_UNIPHIER_ETH
|
||||
tmp |= SC_CLKCTRL_CEN_ETHER;
|
||||
#endif
|
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
|
||||
#endif
|
||||
#ifdef CONFIG_NAND_DENALI
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o \
|
||||
ddrphy-training.o ddrphy-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o \
|
||||
|
|
@ -11,5 +13,9 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \
|
|||
obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += umc-proxstream2.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += umc-proxstream2.o
|
||||
|
||||
else
|
||||
|
||||
obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
|
||||
obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -13,6 +13,16 @@
|
|||
#include "ddrphy-regs.h"
|
||||
#include "umc-regs.h"
|
||||
|
||||
enum dram_size {
|
||||
DRAM_SZ_128M,
|
||||
DRAM_SZ_256M,
|
||||
DRAM_SZ_512M,
|
||||
DRAM_SZ_NR,
|
||||
};
|
||||
|
||||
static u32 umc_initctlb[DRAM_SZ_NR] = {0x43030d3f, 0x43030d3f, 0x7b030d3f};
|
||||
static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
|
||||
|
||||
static void umc_start_ssif(void __iomem *ssif_base)
|
||||
{
|
||||
writel(0x00000001, ssif_base + 0x0000b004);
|
||||
|
|
@ -56,19 +66,36 @@ static void umc_start_ssif(void __iomem *ssif_base)
|
|||
writel(0x00000001, ssif_base + UMC_DMDRST);
|
||||
}
|
||||
|
||||
static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
|
||||
int size, int freq)
|
||||
static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
|
||||
int size, int width)
|
||||
{
|
||||
enum dram_size dram_size;
|
||||
|
||||
switch (size / (width / 16)) {
|
||||
case SZ_128M:
|
||||
dram_size = DRAM_SZ_128M;
|
||||
break;
|
||||
case SZ_256M:
|
||||
dram_size = DRAM_SZ_256M;
|
||||
break;
|
||||
case SZ_512M:
|
||||
dram_size = DRAM_SZ_512M;
|
||||
break;
|
||||
default:
|
||||
printf("unsupported DRAM size\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
|
||||
writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
|
||||
writel(0x5101387f, dramcont + UMC_INITCTLA);
|
||||
writel(0x43030d3f, dramcont + UMC_INITCTLB);
|
||||
writel(umc_initctlb[dram_size], dramcont + UMC_INITCTLB);
|
||||
writel(0x00ff00ff, dramcont + UMC_INITCTLC);
|
||||
writel(0x00000d71, dramcont + UMC_DRMMR0);
|
||||
writel(0x00000006, dramcont + UMC_DRMMR1);
|
||||
writel(0x00000298, dramcont + UMC_DRMMR2);
|
||||
writel(0x00000000, dramcont + UMC_DRMMR3);
|
||||
writel(0x003f0617, dramcont + UMC_SPCCTLA);
|
||||
writel(umc_spcctla[dram_size], dramcont + UMC_SPCCTLA);
|
||||
writel(0x00ff0008, dramcont + UMC_SPCCTLB);
|
||||
writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
|
||||
writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
|
||||
|
|
@ -90,9 +117,11 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
|
|||
writel(0x200a0a00, dramcont + UMC_SPCSETB);
|
||||
writel(0x00010000, dramcont + UMC_SPCSETD);
|
||||
writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int umc_init_sub(int freq, int size_ch0, int size_ch1)
|
||||
int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
|
||||
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
|
||||
|
|
@ -103,6 +132,12 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
|
|||
void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
|
||||
void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
|
||||
void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
|
||||
int ret;
|
||||
|
||||
if (bd->dram_freq != 1600) {
|
||||
pr_err("Unsupported DDR configuration\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
umc_dram_init_start(dramcont0);
|
||||
umc_dram_init_start(dramcont1);
|
||||
|
|
@ -111,52 +146,43 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
|
|||
|
||||
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
|
||||
|
||||
ph1_pro4_ddrphy_init(phy0_0, freq, size_ch0);
|
||||
ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch0_size);
|
||||
|
||||
ddrphy_prepare_training(phy0_0, 0);
|
||||
ddrphy_training(phy0_0);
|
||||
|
||||
writel(0x00000103, dramcont0 + UMC_DIOCTLA);
|
||||
|
||||
ph1_pro4_ddrphy_init(phy0_1, freq, size_ch0);
|
||||
ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch0_size);
|
||||
|
||||
ddrphy_prepare_training(phy0_1, 1);
|
||||
ddrphy_training(phy0_1);
|
||||
|
||||
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
|
||||
|
||||
ph1_pro4_ddrphy_init(phy1_0, freq, size_ch1);
|
||||
ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch1_size);
|
||||
|
||||
ddrphy_prepare_training(phy1_0, 0);
|
||||
ddrphy_training(phy1_0);
|
||||
|
||||
writel(0x00000103, dramcont1 + UMC_DIOCTLA);
|
||||
|
||||
ph1_pro4_ddrphy_init(phy1_1, freq, size_ch1);
|
||||
ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch1_size);
|
||||
|
||||
ddrphy_prepare_training(phy1_1, 1);
|
||||
ddrphy_training(phy1_1);
|
||||
|
||||
umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
|
||||
umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
|
||||
ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch0_size,
|
||||
bd->dram_ch0_width);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch1_size,
|
||||
bd->dram_ch1_width);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
umc_start_ssif(ssif_base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
if (((bd->dram_ch0_size == SZ_512M && bd->dram_ch0_width == 32) ||
|
||||
(bd->dram_ch0_size == SZ_256M && bd->dram_ch0_width == 16)) &&
|
||||
((bd->dram_ch1_size == SZ_512M && bd->dram_ch1_width == 32) ||
|
||||
(bd->dram_ch1_size == SZ_256M && bd->dram_ch1_width == 16)) &&
|
||||
bd->dram_freq == 1600) {
|
||||
return umc_init_sub(bd->dram_freq,
|
||||
bd->dram_ch0_size / SZ_128M,
|
||||
bd->dram_ch1_size / SZ_128M);
|
||||
} else {
|
||||
pr_err("Unsupported DDR configuration\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@
|
|||
#include "ddrmphy-regs.h"
|
||||
#include "umc-regs.h"
|
||||
|
||||
#define CH_NR 3
|
||||
|
||||
enum dram_freq {
|
||||
FREQ_1866M,
|
||||
FREQ_2133M,
|
||||
|
|
@ -43,6 +45,9 @@ static u32 ddrphy_dtpr3[FREQ_NR] = {0x0010cb49, 0x0010ec89};
|
|||
static u32 ddrphy_mr0[FREQ_NR] = {0x00000115, 0x00000125};
|
||||
static u32 ddrphy_mr2[FREQ_NR] = {0x000002a0, 0x000002a8};
|
||||
|
||||
/* dependent on package and board design */
|
||||
static u32 ddrphy_acbdlr0[CH_NR] = {0x0000000c, 0x0000000c, 0x00000009};
|
||||
|
||||
static u32 umc_cmdctla[FREQ_NR] = {0x66DD131D, 0x77EE1722};
|
||||
/*
|
||||
* The ch2 is a different generation UMC core.
|
||||
|
|
@ -150,7 +155,8 @@ static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
|
|||
return dgsl_max;
|
||||
}
|
||||
|
||||
static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width)
|
||||
static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width,
|
||||
int ch)
|
||||
{
|
||||
u32 tmp;
|
||||
void __iomem *zq_base, *dx_base;
|
||||
|
|
@ -178,6 +184,8 @@ static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width)
|
|||
writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3);
|
||||
writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4);
|
||||
|
||||
writel(ddrphy_acbdlr0[ch], phy_base + DMPHY_ACBDLR0);
|
||||
|
||||
writel(0x55555555, phy_base + DMPHY_ACIOCR1);
|
||||
writel(0x00000000, phy_base + DMPHY_ACIOCR2);
|
||||
writel(0x55555555, phy_base + DMPHY_ACIOCR3);
|
||||
|
|
@ -528,7 +536,7 @@ static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch,
|
|||
writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
|
||||
umc_dc_base + UMC_DIOCTLA);
|
||||
|
||||
ddrphy_init(phy_base, freq, width);
|
||||
ddrphy_init(phy_base, freq, width, ch);
|
||||
|
||||
ret = ddrphy_impedance_calibration(phy_base);
|
||||
if (ret)
|
||||
|
|
|
|||
|
|
@ -1,20 +0,0 @@
|
|||
/*
|
||||
* UniPhier MIO (Media I/O) registers
|
||||
*
|
||||
* Copyright (C) 2014 Panasonic Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef ARCH_MIO_REGS_H
|
||||
#define ARCH_MIO_REGS_H
|
||||
|
||||
#define MIO_BASE 0x59810000
|
||||
|
||||
#define MIO_CLKCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0020)
|
||||
#define MIO_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0110)
|
||||
#define MIO_USB_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0114)
|
||||
|
||||
#define MIO_USB_RSTCTRL_XRST (0x1 << 0)
|
||||
|
||||
#endif /* ARCH_MIO_REGS_H */
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
/* page table */
|
||||
#define NR_SECTIONS 4096
|
||||
#define SECTION_SHIFT 20
|
||||
#define DEVICE 0x00002002 /* Non-shareable Device */
|
||||
#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
|
||||
|
||||
#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT))
|
||||
#define STACK_SECTION ((CONFIG_SPL_STACK) >> (SECTION_SHIFT))
|
||||
|
||||
.section ".rodata"
|
||||
.align 14
|
||||
ENTRY(init_page_table)
|
||||
section = 0
|
||||
.rept NR_SECTIONS
|
||||
.if section == 0 || section == 1 || section == STACK_SECTION
|
||||
attr = NORMAL
|
||||
.else
|
||||
attr = DEVICE
|
||||
.endif
|
||||
.word (section << SECTION_SHIFT) | attr
|
||||
section = section + 1
|
||||
.endr
|
||||
END(init_page_table)
|
||||
|
|
@ -29,12 +29,16 @@ ENTRY(lowlevel_init)
|
|||
bl debug_ll_init
|
||||
#endif
|
||||
|
||||
bl setup_init_ram @ RAM area for stack and page talbe
|
||||
|
||||
/*
|
||||
* Now we are using the page table embedded in the Boot ROM.
|
||||
* It is not handy since it is not a straight mapped table for sLD3.
|
||||
* What we need to do next is to switch over to the page table in SPL.
|
||||
* Also, the access to the external bus is prohibited. What we need
|
||||
* to do next is to create a page table and switch over to it.
|
||||
*/
|
||||
ldr r3, =init_page_table @ page table must be 16KB aligned
|
||||
bl create_page_table
|
||||
bl v7_flush_dcache_all
|
||||
|
||||
/* Disable MMU and Dcache before switching Page Table */
|
||||
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
|
||||
|
|
@ -43,8 +47,6 @@ ENTRY(lowlevel_init)
|
|||
|
||||
bl enable_mmu
|
||||
|
||||
bl setup_init_ram @ RAM area for temporary stack pointer
|
||||
|
||||
mov lr, r8 @ restore link
|
||||
mov pc, lr @ back to my caller
|
||||
ENDPROC(lowlevel_init)
|
||||
|
|
@ -55,7 +57,7 @@ ENTRY(enable_mmu)
|
|||
orr r0, r0, #0x20 @ disable TTBR1
|
||||
mcr p15, 0, r0, c2, c0, 2
|
||||
|
||||
orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
|
||||
orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA
|
||||
mcr p15, 0, r0, c2, c0, 0 @ TTBR0
|
||||
|
||||
mov r0, #0
|
||||
|
|
@ -82,8 +84,9 @@ ENDPROC(enable_mmu)
|
|||
* For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
|
||||
* It is large enough for tmp RAM.
|
||||
*/
|
||||
#define BOOT_RAM_SIZE (SZ_32K)
|
||||
#define BOOT_WAY_BITS (0x00000100) /* way 8 */
|
||||
#define BOOT_RAM_SIZE (SZ_32K)
|
||||
#define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
|
||||
#define BOOT_WAY_BITS (0x00000100) /* way 8 */
|
||||
|
||||
ENTRY(setup_init_ram)
|
||||
/*
|
||||
|
|
@ -96,7 +99,7 @@ ENTRY(setup_init_ram)
|
|||
ldr r0, = 0x00408006 @ touch to zero with address range
|
||||
ldr r1, = SSCOQM
|
||||
str r0, [r1]
|
||||
ldr r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE) @ base address
|
||||
ldr r0, = BOOT_RAM_BASE
|
||||
ldr r1, = SSCOQAD
|
||||
str r0, [r1]
|
||||
ldr r0, = BOOT_RAM_SIZE
|
||||
|
|
@ -119,3 +122,86 @@ ENTRY(setup_init_ram)
|
|||
|
||||
mov pc, lr
|
||||
ENDPROC(setup_init_ram)
|
||||
|
||||
#define DEVICE 0x00002002 /* Non-shareable Device */
|
||||
#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
|
||||
|
||||
ENTRY(create_page_table)
|
||||
ldr r0, = DEVICE
|
||||
ldr r1, = BOOT_RAM_BASE
|
||||
mov r12, r1 @ r12 is preserved during D-cache flush
|
||||
0: str r0, [r1], #4 @ specify all the sections as Device
|
||||
adds r0, r0, #0x00100000
|
||||
bcc 0b
|
||||
|
||||
ldr r0, = NORMAL
|
||||
str r0, [r12] @ mark the first section as Normal
|
||||
add r0, r0, #0x00100000
|
||||
str r0, [r12, #4] @ mark the second section as Normal
|
||||
mov pc, lr
|
||||
ENDPROC(create_page_table)
|
||||
|
||||
/* We don't use Thumb instructions for now */
|
||||
#define ARM(x...) x
|
||||
#define THUMB(x...)
|
||||
|
||||
/*
|
||||
* v7_flush_dcache_all()
|
||||
*
|
||||
* Flush the whole D-cache.
|
||||
*
|
||||
* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
|
||||
*
|
||||
* - mm - mm_struct describing address space
|
||||
*
|
||||
* Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
|
||||
*/
|
||||
ENTRY(v7_flush_dcache_all)
|
||||
dmb @ ensure ordering with previous memory accesses
|
||||
mrc p15, 1, r0, c0, c0, 1 @ read clidr
|
||||
mov r3, r0, lsr #23 @ move LoC into position
|
||||
ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
|
||||
beq finished @ if loc is 0, then no need to clean
|
||||
start_flush_levels:
|
||||
mov r10, #0 @ start clean at cache level 0
|
||||
flush_levels:
|
||||
add r2, r10, r10, lsr #1 @ work out 3x current cache level
|
||||
mov r1, r0, lsr r2 @ extract cache type bits from clidr
|
||||
and r1, r1, #7 @ mask of the bits for current cache only
|
||||
cmp r1, #2 @ see what cache we have at this level
|
||||
blt skip @ skip if no cache, or just i-cache
|
||||
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
|
||||
isb @ isb to sych the new cssr&csidr
|
||||
mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
|
||||
and r2, r1, #7 @ extract the length of the cache lines
|
||||
add r2, r2, #4 @ add 4 (line length offset)
|
||||
movw r4, #0x3ff
|
||||
ands r4, r4, r1, lsr #3 @ find maximum number on the way size
|
||||
clz r5, r4 @ find bit position of way size increment
|
||||
movw r7, #0x7fff
|
||||
ands r7, r7, r1, lsr #13 @ extract max number of the index size
|
||||
loop1:
|
||||
mov r9, r7 @ create working copy of max index
|
||||
loop2:
|
||||
ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
|
||||
THUMB( lsl r6, r4, r5 )
|
||||
THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
|
||||
ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
|
||||
THUMB( lsl r6, r9, r2 )
|
||||
THUMB( orr r11, r11, r6 ) @ factor index number into r11
|
||||
mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
|
||||
subs r9, r9, #1 @ decrement the index
|
||||
bge loop2
|
||||
subs r4, r4, #1 @ decrement the way
|
||||
bge loop1
|
||||
skip:
|
||||
add r10, r10, #2 @ increment cache number
|
||||
cmp r3, r10
|
||||
bgt flush_levels
|
||||
finished:
|
||||
mov r10, #0 @ swith back to cache level 0
|
||||
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
|
||||
dsb st
|
||||
isb
|
||||
mov pc, lr
|
||||
ENDPROC(v7_flush_dcache_all)
|
||||
|
|
|
|||
|
|
@ -35,15 +35,6 @@ void ph1_ld4_pin_init(void)
|
|||
sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER
|
||||
sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
|
||||
sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */
|
||||
sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
|
||||
sg_set_pinsel(56, 0, 8, 4); /* USB1OD -> USB1OD */
|
||||
/* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */
|
||||
/* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */
|
||||
#endif
|
||||
|
||||
tmp = readl(SG_IECTRL);
|
||||
tmp |= 0x41;
|
||||
writel(tmp, SG_IECTRL);
|
||||
|
|
|
|||
|
|
@ -40,12 +40,5 @@ void ph1_pro4_pin_init(void)
|
|||
sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER
|
||||
sg_set_pinsel(184, 0, 4, 8); /* USB2VBUS -> USB2VBUS */
|
||||
sg_set_pinsel(185, 0, 4, 8); /* USB2OD -> USB2OD */
|
||||
sg_set_pinsel(187, 0, 4, 8); /* USB3VBUS -> USB3VBUS */
|
||||
sg_set_pinsel(188, 0, 4, 8); /* USB3OD -> USB3OD */
|
||||
#endif
|
||||
|
||||
writel(1, SG_LOADPINCTRL);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
void ph1_sld3_pin_init(void)
|
||||
{
|
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
sg_set_pinsel(13, 0, 4, 4); /* USB0OC */
|
||||
sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */
|
||||
|
||||
|
|
|
|||
|
|
@ -32,13 +32,4 @@ void ph1_sld8_pin_init(void)
|
|||
sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */
|
||||
sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER
|
||||
sg_set_pinsel(41, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
|
||||
sg_set_pinsel(42, 0, 8, 4); /* USB0OD -> USB0OD */
|
||||
sg_set_pinsel(43, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
|
||||
sg_set_pinsel(44, 0, 8, 4); /* USB1OD -> USB1OD */
|
||||
/* sg_set_pinsel(114, 1, 8, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
|
||||
/* sg_set_pinsel(115, 1, 8, 4); */ /* RXD1 -> USB2OD */
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,5 +27,7 @@ CONFIG_PINCTRL=y
|
|||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_UNIPHIER_SERIAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
|
|
|
|||
|
|
@ -22,5 +22,7 @@ CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
|
|||
CONFIG_SPL_NAND_DENALI=y
|
||||
CONFIG_UNIPHIER_SERIAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
|
|
|
|||
|
|
@ -68,8 +68,8 @@ Burn U-Boot images to NAND
|
|||
--------------------------
|
||||
|
||||
Write two files to the NAND device as follows:
|
||||
- spl/u-boot-spl-dtb.bin at the offset address 0x00000000
|
||||
- u-boot-dtb.img at the offset address 0x00010000
|
||||
- spl/u-boot-spl.bin at the offset address 0x00000000
|
||||
- u-boot.img at the offset address 0x00010000
|
||||
|
||||
If a TFTP server is available, the images can be easily updated.
|
||||
Just copy the u-boot-spl-dtb.bin and u-boot-dtb.img to the TFTP public
|
||||
|
|
@ -145,4 +145,4 @@ newer SoCs. Even if it is, EA[25] is not connected on most of the boards.
|
|||
|
||||
--
|
||||
Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
Aug. 2015
|
||||
Feb. 2016
|
||||
|
|
|
|||
|
|
@ -20,4 +20,6 @@ config SPL_CLK
|
|||
setting up clocks within SPL, and allows the same drivers to be
|
||||
used as U-Boot proper.
|
||||
|
||||
source "drivers/clk/uniphier/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -10,3 +10,4 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
|
|||
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
|
||||
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
|
||||
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
|
||||
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
|
||||
|
|
|
|||
13
drivers/clk/uniphier/Kconfig
Normal file
13
drivers/clk/uniphier/Kconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
config CLK_UNIPHIER
|
||||
bool
|
||||
select CLK
|
||||
select SPL_CLK
|
||||
|
||||
menu "Clock drivers for UniPhier SoCs"
|
||||
depends on CLK_UNIPHIER
|
||||
|
||||
config CLK_UNIPHIER_MIO
|
||||
bool "Clock driver for UniPhier Media I/O block"
|
||||
default y
|
||||
|
||||
endmenu
|
||||
3
drivers/clk/uniphier/Makefile
Normal file
3
drivers/clk/uniphier/Makefile
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
obj-y += clk-uniphier-core.o
|
||||
|
||||
obj-$(CONFIG_CLK_UNIPHIER_MIO) += clk-uniphier-mio.o
|
||||
159
drivers/clk/uniphier/clk-uniphier-core.c
Normal file
159
drivers/clk/uniphier/clk-uniphier-core.c
Normal file
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mapmem.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/io.h>
|
||||
#include <clk.h>
|
||||
#include <dm/device.h>
|
||||
|
||||
#include "clk-uniphier.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static int uniphier_clk_enable(struct udevice *dev, int index)
|
||||
{
|
||||
struct uniphier_clk_priv *priv = dev_get_priv(dev);
|
||||
struct uniphier_clk_gate_data *gate = priv->socdata->gate;
|
||||
unsigned int nr_gate = priv->socdata->nr_gate;
|
||||
void __iomem *reg;
|
||||
u32 mask, data, tmp;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nr_gate; i++) {
|
||||
if (gate[i].index != index)
|
||||
continue;
|
||||
|
||||
reg = priv->base + gate[i].reg;
|
||||
mask = gate[i].mask;
|
||||
data = gate[i].data & mask;
|
||||
|
||||
tmp = readl(reg);
|
||||
tmp &= ~mask;
|
||||
tmp |= data & mask;
|
||||
debug("%s: %p: %08x\n", __func__, reg, tmp);
|
||||
writel(tmp, reg);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ulong uniphier_clk_get_rate(struct udevice *dev, int index)
|
||||
{
|
||||
struct uniphier_clk_priv *priv = dev_get_priv(dev);
|
||||
struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
|
||||
unsigned int nr_rdata = priv->socdata->nr_rate;
|
||||
void __iomem *reg;
|
||||
u32 mask, data;
|
||||
ulong matched_rate = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nr_rdata; i++) {
|
||||
if (rdata[i].index != index)
|
||||
continue;
|
||||
|
||||
if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
|
||||
return rdata[i].rate;
|
||||
|
||||
reg = priv->base + rdata[i].reg;
|
||||
mask = rdata[i].mask;
|
||||
data = rdata[i].data & mask;
|
||||
if ((readl(reg) & mask) == data) {
|
||||
if (matched_rate && rdata[i].rate != matched_rate) {
|
||||
printf("failed to get clk rate for insane register values\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
matched_rate = rdata[i].rate;
|
||||
}
|
||||
}
|
||||
|
||||
debug("%s: rate = %lu\n", __func__, matched_rate);
|
||||
|
||||
return matched_rate;
|
||||
}
|
||||
|
||||
static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate)
|
||||
{
|
||||
struct uniphier_clk_priv *priv = dev_get_priv(dev);
|
||||
struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
|
||||
unsigned int nr_rdata = priv->socdata->nr_rate;
|
||||
void __iomem *reg;
|
||||
u32 mask, data, tmp;
|
||||
ulong best_rate = 0;
|
||||
int i;
|
||||
|
||||
/* first, decide the best match rate */
|
||||
for (i = 0; i < nr_rdata; i++) {
|
||||
if (rdata[i].index != index)
|
||||
continue;
|
||||
|
||||
if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
|
||||
return 0;
|
||||
|
||||
if (rdata[i].rate > best_rate && rdata[i].rate <= rate)
|
||||
best_rate = rdata[i].rate;
|
||||
}
|
||||
|
||||
if (!best_rate)
|
||||
return -ENODEV;
|
||||
|
||||
debug("%s: requested rate = %lu, set rate = %lu\n", __func__,
|
||||
rate, best_rate);
|
||||
|
||||
/* second, really set registers */
|
||||
for (i = 0; i < nr_rdata; i++) {
|
||||
if (rdata[i].index != index || rdata[i].rate != best_rate)
|
||||
continue;
|
||||
|
||||
reg = priv->base + rdata[i].reg;
|
||||
mask = rdata[i].mask;
|
||||
data = rdata[i].data & mask;
|
||||
|
||||
tmp = readl(reg);
|
||||
tmp &= ~mask;
|
||||
tmp |= data;
|
||||
debug("%s: %p: %08x\n", __func__, reg, tmp);
|
||||
writel(tmp, reg);
|
||||
}
|
||||
|
||||
return best_rate;
|
||||
}
|
||||
|
||||
const struct clk_ops uniphier_clk_ops = {
|
||||
.enable = uniphier_clk_enable,
|
||||
.get_periph_rate = uniphier_clk_get_rate,
|
||||
.set_periph_rate = uniphier_clk_set_rate,
|
||||
};
|
||||
|
||||
int uniphier_clk_probe(struct udevice *dev)
|
||||
{
|
||||
struct uniphier_clk_priv *priv = dev_get_priv(dev);
|
||||
fdt_addr_t addr;
|
||||
fdt_size_t size;
|
||||
|
||||
addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
|
||||
&size);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
priv->base = map_sysmem(addr, size);
|
||||
if (!priv->base)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->socdata = (void *)dev_get_driver_data(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int uniphier_clk_remove(struct udevice *dev)
|
||||
{
|
||||
struct uniphier_clk_priv *priv = dev_get_priv(dev);
|
||||
|
||||
unmap_sysmem(priv->base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
178
drivers/clk/uniphier/clk-uniphier-mio.c
Normal file
178
drivers/clk/uniphier/clk-uniphier-mio.c
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <clk.h>
|
||||
#include <dm/device.h>
|
||||
|
||||
#include "clk-uniphier.h"
|
||||
|
||||
#define UNIPHIER_MIO_CLK_GATE_SD(ch, idx) \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x20 + 0x200 * (ch), \
|
||||
.mask = 0x00000100, \
|
||||
.data = 0x00000100, \
|
||||
}, \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x110 + 0x200 * (ch), \
|
||||
.mask = 0x00000001, \
|
||||
.data = 0x00000001, \
|
||||
}
|
||||
|
||||
#define UNIPHIER_MIO_CLK_RATE_SD(ch, idx) \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x30 + 0x200 * (ch), \
|
||||
.mask = 0x00031300, \
|
||||
.data = 0x00000000, \
|
||||
.rate = 44444444, \
|
||||
}, \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x30 + 0x200 * (ch), \
|
||||
.mask = 0x00031300, \
|
||||
.data = 0x00010000, \
|
||||
.rate = 33333333, \
|
||||
}, \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x30 + 0x200 * (ch), \
|
||||
.mask = 0x00031300, \
|
||||
.data = 0x00020000, \
|
||||
.rate = 50000000, \
|
||||
}, \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x30 + 0x200 * (ch), \
|
||||
.mask = 0x00031300, \
|
||||
.data = 0x00020000, \
|
||||
.rate = 66666666, \
|
||||
}, \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x30 + 0x200 * (ch), \
|
||||
.mask = 0x00031300, \
|
||||
.data = 0x00001000, \
|
||||
.rate = 100000000, \
|
||||
}, \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x30 + 0x200 * (ch), \
|
||||
.mask = 0x00031300, \
|
||||
.data = 0x00001100, \
|
||||
.rate = 40000000, \
|
||||
}, \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x30 + 0x200 * (ch), \
|
||||
.mask = 0x00031300, \
|
||||
.data = 0x00001200, \
|
||||
.rate = 25000000, \
|
||||
}, \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x30 + 0x200 * (ch), \
|
||||
.mask = 0x00031300, \
|
||||
.data = 0x00001300, \
|
||||
.rate = 22222222, \
|
||||
}
|
||||
|
||||
#define UNIPHIER_MIO_CLK_GATE_USB(ch, idx) \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x20 + 0x200 * (ch), \
|
||||
.mask = 0x30000000, \
|
||||
.data = 0x30000000, \
|
||||
}, \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x110 + 0x200 * (ch), \
|
||||
.mask = 0x01000000, \
|
||||
.data = 0x01000000, \
|
||||
}, \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x114 + 0x200 * (ch), \
|
||||
.mask = 0x00000001, \
|
||||
.data = 0x00000001, \
|
||||
}
|
||||
|
||||
#define UNIPHIER_MIO_CLK_GATE_DMAC(idx) \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x20, \
|
||||
.mask = 0x02000000, \
|
||||
.data = 0x02000000, \
|
||||
}, \
|
||||
{ \
|
||||
.index = (idx), \
|
||||
.reg = 0x110, \
|
||||
.mask = 0x00020000, \
|
||||
.data = 0x00020000, \
|
||||
}
|
||||
|
||||
static struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
|
||||
UNIPHIER_MIO_CLK_GATE_SD(0, 0),
|
||||
UNIPHIER_MIO_CLK_GATE_SD(1, 1),
|
||||
UNIPHIER_MIO_CLK_GATE_SD(2, 2), /* for PH1-Pro4 only */
|
||||
UNIPHIER_MIO_CLK_GATE_USB(0, 3),
|
||||
UNIPHIER_MIO_CLK_GATE_USB(1, 4),
|
||||
UNIPHIER_MIO_CLK_GATE_USB(2, 5),
|
||||
UNIPHIER_MIO_CLK_GATE_DMAC(6),
|
||||
UNIPHIER_MIO_CLK_GATE_USB(3, 7), /* for PH1-sLD3 only */
|
||||
};
|
||||
|
||||
static struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = {
|
||||
UNIPHIER_MIO_CLK_RATE_SD(0, 0),
|
||||
UNIPHIER_MIO_CLK_RATE_SD(1, 1),
|
||||
UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */
|
||||
};
|
||||
|
||||
static struct uniphier_clk_soc_data uniphier_mio_clk_data = {
|
||||
.gate = uniphier_mio_clk_gate,
|
||||
.nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate),
|
||||
.rate = uniphier_mio_clk_rate,
|
||||
.nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate),
|
||||
};
|
||||
|
||||
static const struct udevice_id uniphier_mio_clk_match[] = {
|
||||
{
|
||||
.compatible = "socionext,ph1-sld3-mioctrl",
|
||||
.data = (ulong)&uniphier_mio_clk_data,
|
||||
},
|
||||
{
|
||||
.compatible = "socionext,ph1-ld4-mioctrl",
|
||||
.data = (ulong)&uniphier_mio_clk_data,
|
||||
},
|
||||
{
|
||||
.compatible = "socionext,ph1-pro4-mioctrl",
|
||||
.data = (ulong)&uniphier_mio_clk_data,
|
||||
},
|
||||
{
|
||||
.compatible = "socionext,ph1-sld8-mioctrl",
|
||||
.data = (ulong)&uniphier_mio_clk_data,
|
||||
},
|
||||
{
|
||||
.compatible = "socionext,ph1-pro5-mioctrl",
|
||||
.data = (ulong)&uniphier_mio_clk_data,
|
||||
},
|
||||
{
|
||||
.compatible = "socionext,proxstream2-mioctrl",
|
||||
.data = (ulong)&uniphier_mio_clk_data,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(uniphier_mio_clk) = {
|
||||
.name = "uniphier-mio-clk",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = uniphier_mio_clk_match,
|
||||
.probe = uniphier_clk_probe,
|
||||
.remove = uniphier_clk_remove,
|
||||
.priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
|
||||
.ops = &uniphier_clk_ops,
|
||||
};
|
||||
57
drivers/clk/uniphier/clk-uniphier.h
Normal file
57
drivers/clk/uniphier/clk-uniphier.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CLK_UNIPHIER_H__
|
||||
#define __CLK_UNIPHIER_H__
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
||||
struct uniphier_clk_gate_data {
|
||||
int index;
|
||||
unsigned int reg;
|
||||
u32 mask;
|
||||
u32 data;
|
||||
};
|
||||
|
||||
struct uniphier_clk_rate_data {
|
||||
int index;
|
||||
unsigned int reg;
|
||||
#define UNIPHIER_CLK_RATE_IS_FIXED UINT_MAX
|
||||
u32 mask;
|
||||
u32 data;
|
||||
unsigned long rate;
|
||||
};
|
||||
|
||||
struct uniphier_clk_soc_data {
|
||||
struct uniphier_clk_gate_data *gate;
|
||||
unsigned int nr_gate;
|
||||
struct uniphier_clk_rate_data *rate;
|
||||
unsigned int nr_rate;
|
||||
};
|
||||
|
||||
#define UNIPHIER_CLK_FIXED_RATE(i, f) \
|
||||
{ \
|
||||
.index = i, \
|
||||
.reg = UNIPHIER_CLK_RATE_IS_FIXED, \
|
||||
.rate = f, \
|
||||
}
|
||||
|
||||
/**
|
||||
* struct uniphier_clk_priv - private data for UniPhier clock driver
|
||||
*
|
||||
* @base: base address of the clock provider
|
||||
* @socdata: SoC specific data
|
||||
*/
|
||||
struct uniphier_clk_priv {
|
||||
void __iomem *base;
|
||||
struct uniphier_clk_soc_data *socdata;
|
||||
};
|
||||
|
||||
extern const struct clk_ops uniphier_clk_ops;
|
||||
int uniphier_clk_probe(struct udevice *dev);
|
||||
int uniphier_clk_remove(struct udevice *dev);
|
||||
|
||||
#endif /* __CLK_UNIPHIER_H__ */
|
||||
|
|
@ -74,13 +74,6 @@ config USB_EHCI_MX6
|
|||
---help---
|
||||
Enables support for the on-chip EHCI controller on i.MX6 SoCs.
|
||||
|
||||
config USB_EHCI_UNIPHIER
|
||||
bool "Support for UniPhier on-chip EHCI USB controller"
|
||||
depends on ARCH_UNIPHIER && OF_CONTROL
|
||||
default y
|
||||
---help---
|
||||
Enables support for the on-chip EHCI controller on UniPhier SoCs.
|
||||
|
||||
config USB_EHCI_GENERIC
|
||||
bool "Support for generic EHCI USB controller"
|
||||
depends on OF_CONTROL
|
||||
|
|
|
|||
|
|
@ -47,7 +47,6 @@ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
|
|||
obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
|
||||
obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
|
||||
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
|
||||
obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o
|
||||
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
|
||||
obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
|
||||
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
|
||||
|
|
|
|||
|
|
@ -1,75 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <usb.h>
|
||||
#include <mach/mio-regs.h>
|
||||
#include <fdtdec.h>
|
||||
#include "ehci.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define FDT gd->fdt_blob
|
||||
#define COMPAT "socionext,uniphier-ehci"
|
||||
|
||||
static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
|
||||
{
|
||||
int offset;
|
||||
|
||||
for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
|
||||
offset >= 0;
|
||||
offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
|
||||
if (index == 0) {
|
||||
*base = (struct ehci_hccr *)
|
||||
fdtdec_get_addr(FDT, offset, "reg");
|
||||
return 0;
|
||||
}
|
||||
index--;
|
||||
}
|
||||
|
||||
return -ENODEV; /* not found */
|
||||
}
|
||||
|
||||
static void uniphier_ehci_reset(int index, int on)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(MIO_USB_RSTCTRL(index));
|
||||
if (on)
|
||||
tmp &= ~MIO_USB_RSTCTRL_XRST;
|
||||
else
|
||||
tmp |= MIO_USB_RSTCTRL_XRST;
|
||||
writel(tmp, MIO_USB_RSTCTRL(index));
|
||||
}
|
||||
|
||||
int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
|
||||
struct ehci_hcor **hcor)
|
||||
{
|
||||
int ret;
|
||||
struct ehci_hccr *cr;
|
||||
struct ehci_hcor *or;
|
||||
|
||||
uniphier_ehci_reset(index, 0);
|
||||
|
||||
ret = get_uniphier_ehci_base(index, &cr);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase));
|
||||
|
||||
*hccr = cr;
|
||||
*hcor = or;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ehci_hcd_stop(int index)
|
||||
{
|
||||
uniphier_ehci_reset(index, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -173,7 +173,7 @@
|
|||
"setenv bootargs $bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
|
||||
"tftpboot; bootm;"
|
||||
"run __nfsboot"
|
||||
|
||||
#ifdef CONFIG_FIT
|
||||
#define CONFIG_BOOTFILE "fitImage"
|
||||
|
|
@ -186,7 +186,8 @@
|
|||
"nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
|
||||
"bootm $fit_addr_r\0" \
|
||||
"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
|
||||
"bootm $fit_addr_r\0"
|
||||
"bootm $fit_addr_r\0" \
|
||||
"__nfsboot=run tftpboot\0"
|
||||
#else
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_BOOTFILE "zImage"
|
||||
|
|
@ -201,31 +202,36 @@
|
|||
"ramdisk_addr_r=0x84a00000\0" \
|
||||
"ramdisk_size=0x00600000\0" \
|
||||
"ramdisk_file=rootfs.cpio.uboot\0" \
|
||||
"norboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
|
||||
"setexpr kernel_addr $nor_base + $kernel_addr &&" \
|
||||
"setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
|
||||
"setexpr fdt_addr $nor_base + $fdt_addr &&" \
|
||||
"bootz $kernel_addr $ramdisk_addr $fdt_addr\0" \
|
||||
"nandboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
|
||||
"nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
|
||||
"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
|
||||
"bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
|
||||
"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
|
||||
"cp.b $kernel_addr $kernel_addr_r $kernel_size &&" \
|
||||
"setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
|
||||
"setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
|
||||
"run boot_common\0" \
|
||||
"nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
|
||||
"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
|
||||
"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
|
||||
"bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
|
||||
"tftpboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
|
||||
"tftpboot $kernel_addr_r $bootfile &&" \
|
||||
"run boot_common\0" \
|
||||
"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
|
||||
"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
|
||||
"tftpboot $fdt_addr_r $fdt_file &&" \
|
||||
"bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
|
||||
"run boot_common\0" \
|
||||
"__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
|
||||
"tftpboot $fdt_addr_r $fdt_file &&" \
|
||||
"tftpboot $fdt_addr_r $fdt_file &&" \
|
||||
"setenv ramdisk_addr_r - &&" \
|
||||
"run boot_common\0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"verify=n\0" \
|
||||
"norbase=0x42000000\0" \
|
||||
"nor_base=0x42000000\0" \
|
||||
"nandupdate=nand erase 0 0x00100000 &&" \
|
||||
"tftpboot u-boot-spl-dtb.bin &&" \
|
||||
"tftpboot u-boot-spl.bin &&" \
|
||||
"nand write $loadaddr 0 0x00010000 &&" \
|
||||
"tftpboot u-boot-dtb.img &&" \
|
||||
"tftpboot u-boot.img &&" \
|
||||
"nand write $loadaddr 0x00010000 0x000f0000\0" \
|
||||
LINUXBOOT_ENV_SETTINGS
|
||||
|
||||
|
|
@ -245,7 +251,7 @@
|
|||
#define CONFIG_SPL_TEXT_BASE 0x00100000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SPL_STACK (0x0ff08000)
|
||||
#define CONFIG_SPL_STACK (0x00100000)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
|
||||
|
||||
#define CONFIG_PANIC_HANG
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue