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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Browse source 
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
  powerpc/mpc85xx: Workaround for erratum CPU_A011
  powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
  powerpc/P4080: Check SVR for CPU22 workaround
  lib/powerpc: addrmap_phys_to_virt() should return a pointer
  powerpc/85xx: clean up P1022DS board configuration header file
  powerpc/85xx: fdt_set_phy_handle() should return an error code
  powerpc/85xx: minor clean-ups to the P2020DS board header file
  powerpc/p1010rdb: add readme document for p1010rdb
  powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
  powerpc/mpc85xx:Add debugger support for e500v2 SoC
  powerpc/85xx:Fix NAND code base to support debugger
  powerpc/85xx:Make debug exception vector accessible
  powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
  PATCH 1/4][v4] doc:Add documentation for e500 external debugger support
  powerpc/p1010rdb: update mux config of p1010rdb board
  powerpc/mpc85xx:Add BSC9131 RDB Support
  powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
  powerpc/85xx: Add USB device-tree fixup for various platforms

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2012-07-08 19:16:14 +02:00
commit 8246ff864d
47 changed files with 1881 additions and 261 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
MAINTAINERS
View file

@ -21,6 +21,8 @@ Poonam Aggrwal <poonam.aggrwal@freescale.com>
P2020RDB P2020
BSC9131RDB BSC9131
Greg Allen <gallen@arlut.utexas.edu>
UTX8245 MPC8245

9
README
View file

@ -374,6 +374,15 @@ The following options need to be configured:
Defines the string to utilize when trying to match PCIe device
tree nodes for the given platform.
CONFIG_SYS_PPC_E500_DEBUG_TLB
Enables a temporary TLB entry to be used during boot to work
around limitations in e500v1 and e500v2 external debugger
support. This reduces the portions of the boot code where
breakpoints and single stepping do not work. The value of this
symbol should be set to the TLB1 entry to be used for this
purpose.
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN

1
arch/powerpc/cpu/mpc85xx/Makefile
View file

@ -70,6 +70,7 @@ COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3060) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o

13
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View file

@ -33,9 +33,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (IS_SVR_REV(svr, 1, 0)) {
switch (SVR_SOC_VER(svr)) {
case SVR_P1013:
case SVR_P1013_E:
case SVR_P1022:
case SVR_P1022_E:
puts("Work-around for Erratum SATA A001 enabled\n");
}
}
@ -51,7 +49,16 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
puts("Work-around for Erratum SERDES-A005 enabled\n");
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
puts("Work-around for Erratum CPU22 enabled\n");
if (SVR_MAJ(svr) < 3)
puts("Work-around for Erratum CPU22 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
/*
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
*/
if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3)
puts("Work-around for Erratum CPU-A011 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
puts("Work-around for Erratum CPU-A003999 enabled\n");

31
arch/powerpc/cpu/mpc85xx/cpu_init.c
View file

@ -308,10 +308,18 @@ int cpu_init_r(void)
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
flush_dcache();
mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
sync();
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
*/
if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) {
flush_dcache();
mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
sync();
}
#endif
puts ("L2: ");
@ -354,8 +362,7 @@ int cpu_init_r(void)
break;
case 0x1:
if (ver == SVR_8540 || ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8541_E ||
ver == SVR_8555 || ver == SVR_8555_E) {
ver == SVR_8541 || ver == SVR_8555) {
puts("128 KB ");
/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
cache_ctl = 0xc4000000;
@ -366,8 +373,7 @@ int cpu_init_r(void)
break;
case 0x2:
if (ver == SVR_8540 || ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8541_E ||
ver == SVR_8555 || ver == SVR_8555_E) {
ver == SVR_8541 || ver == SVR_8555) {
puts("256 KB ");
/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
cache_ctl = 0xc8000000;
@ -403,8 +409,7 @@ int cpu_init_r(void)
puts("enabled\n");
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
if ((SVR_SOC_VER(svr) == SVR_P2040) ||
(SVR_SOC_VER(svr) == SVR_P2040_E)) {
if (SVR_SOC_VER(svr) == SVR_P2040) {
puts("N/A\n");
goto skip_l2;
}
@ -506,9 +511,7 @@ skip_l2:
*/
if (IS_SVR_REV(svr, 1, 0) &&
((SVR_SOC_VER(svr) == SVR_P1022) ||
(SVR_SOC_VER(svr) == SVR_P1022_E) ||
(SVR_SOC_VER(svr) == SVR_P1013) ||
(SVR_SOC_VER(svr) == SVR_P1013_E))) {
(SVR_SOC_VER(svr) == SVR_P1013))) {
fsl_sata_reg_t *reg;
/* first SATA controller */
@ -537,7 +540,7 @@ void arch_preboot_os(void)
* disabled by the time we get called.
*/
msr = mfmsr();
msr &= ~(MSR_ME|MSR_CE|MSR_DE);
msr &= ~(MSR_ME|MSR_CE);
mtmsr(msr);
setup_ivors();

32
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc
* Copyright 2009-2012 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -53,6 +53,36 @@ void setup_ifc(void)
asm volatile("isync;msync;tlbwe;isync");
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
* As on debug exception MSR is cleared i.e. Address space is changed
* to 0. A TLB entry (in AS0) is required to handle debug exception generated
* in AS1.
*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* bacause flash's physical address is going to change as
* CONFIG_SYS_FLASH_BASE_PHYS.
*/
_mas0 = MAS0_TLBSEL(1) |
MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
MAS1_TSIZE(BOOKE_PAGESZ_4M);
_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
_mas7 = FSL_BOOKE_MAS7(flash_phys);
mtspr(MAS0, _mas0);
mtspr(MAS1, _mas1);
mtspr(MAS2, _mas2);
mtspr(MAS3, _mas3);
mtspr(MAS7, _mas7);
asm volatile("isync;msync;tlbwe;isync");
#endif
/* Change flash's physical address */
out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);

26
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
View file

@ -26,32 +26,6 @@
void cpu_init_f(void)
{
#ifdef CONFIG_FSL_LBC
fsl_lbc_t *lbc = LBC_BASE_ADDR;
/*
* LCRR - Clock Ratio Register - set up local bus timing
* when needed
*/
out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
#else
#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined
#endif
#endif
#ifdef CONFIG_FSL_IFC
#ifndef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
#endif
#endif
#endif
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;

11
arch/powerpc/cpu/mpc85xx/fdt.c
View file

@ -139,16 +139,14 @@ static inline u32 l2cache_size(void)
break;
case 0x1:
if (ver == SVR_8540 || ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8541_E ||
ver == SVR_8555 || ver == SVR_8555_E)
ver == SVR_8541 || ver == SVR_8555)
return 128;
else
return 256;
break;
case 0x2:
if (ver == SVR_8540 || ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8541_E ||
ver == SVR_8555 || ver == SVR_8555_E)
ver == SVR_8541 || ver == SVR_8555)
return 256;
else
return 512;
@ -231,8 +229,7 @@ static inline void ft_fixup_l2cache(void *blob)
int has_l2 = 1;
/* P2040/P2040E has no L2, so dont set any L2 props */
if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
(SVR_SOC_VER(get_svr()) == SVR_P2040_E))
if (SVR_SOC_VER(get_svr()) == SVR_P2040)
has_l2 = 0;
size = (l2cfg0 & 0x3fff) * 64 * 1024;
@ -407,7 +404,7 @@ static void ft_fixup_qe_snum(void *blob)
unsigned int svr;
svr = mfspr(SPRN_SVR);
if (SVR_SOC_VER(svr) == SVR_8569_E) {
if (SVR_SOC_VER(svr) == SVR_8569) {
if(IS_SVR_REV(svr, 1, 0))
do_fixup_by_compat_u32(blob, "fsl,qe",
"fsl,qe-num-snums", 46, 1);

4
arch/powerpc/cpu/mpc85xx/p2041_serdes.c
View file

@ -78,7 +78,7 @@ enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
prtcl = serdes_cfg_tbl[cfg][lane];
/* P2040[e] does not support XAUI */
if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1))
if (ver == SVR_P2040 && prtcl == XAUI_FM1)
prtcl = NONE;
return prtcl;
@ -94,7 +94,7 @@ int is_serdes_prtcl_valid(u32 prtcl)
return 0;
/* P2040[e] does not support XAUI */
if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1))
if (ver == SVR_P2040 && prtcl == XAUI_FM1)
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {

39
arch/powerpc/cpu/mpc85xx/release.S
View file

@ -143,23 +143,40 @@ __secondary_start_page:
mtspr L1CSR2,r8
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
mfspr r8,L1CSR2
oris r8,r8,(L1CSR2_DCWS)@h
mtspr L1CSR2,r8
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
*/
mfspr r3,SPRN_SVR
rlwinm r6,r3,24,~0x800 /* clear E bit */
lis r5,SVR_P4080@h
ori r5,r5,SVR_P4080@l
cmpw r6,r5
bne 1f
rlwinm r3,r3,0,0xf0
li r5,0x30
cmpw r3,r5
bge 2f
1:
mfspr r3,L1CSR2
oris r3,r3,(L1CSR2_DCWS)@h
mtspr L1CSR2,r3
2:
#endif
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* skip L2 setup on P2040/P2040E as they have no L2 */
mfspr r2,SPRN_SVR
mfspr r3,SPRN_SVR
rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
lis r3,SVR_P2040@h
ori r3,r3,SVR_P2040@l
cmpw r2,r3
beq 3f
lis r3,SVR_P2040_E@h
ori r3,r3,SVR_P2040_E@l
cmpw r2,r3
cmpw r6,r3
beq 3f
/* Enable/invalidate the L2 cache */

90
arch/powerpc/cpu/mpc85xx/start.S
View file

@ -82,6 +82,9 @@
.globl _start_e500
_start_e500:
/* Enable debug exception */
li r1,MSR_DE
mtmsr r1
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
/* ISBC uses L2 as stack.
@ -179,6 +182,72 @@ l2_disabled:
andi. r1,r3,L1CSR0_DCE@l
beq 2b
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
* As on debug exception MSR is cleared i.e. Address space is changed
* to 0. A TLB entry (in AS0) is required to handle debug exception generated
* in AS1.
*/
lis r6,FSL_BOOKE_MAS0(1,
CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1,
CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l
#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
* and this window is outside of 4K boot window.
*/
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l
lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
(MAS2_I|MAS2_G))@h
ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
(MAS2_I|MAS2_G))@l
/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h
ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l
lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
(MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
(MAS3_SX|MAS3_SW|MAS3_SR))@l
#else
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* because "nexti" will resize TLB to 4K
*/
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l
lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h
ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
(MAS2_I))@l
lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
(MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
(MAS3_SX|MAS3_SW|MAS3_SR))@l
#endif
mtspr MAS0,r6
mtspr MAS1,r7
mtspr MAS2,r8
mtspr MAS3,r9
tlbwe
isync
#endif
/*
* Ne need to setup interrupt vector for NAND SPL
* because NAND SPL never compiles it.
@ -733,8 +802,8 @@ create_init_ram_area:
msync
tlbwe
lis r6,MSR_IS|MSR_DS@h
ori r6,r6,MSR_IS|MSR_DS@l
lis r6,MSR_IS|MSR_DS|MSR_DE@h
ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
lis r7,switch_as@h
ori r7,r7,switch_as@l
@ -1372,17 +1441,24 @@ relocate_code:
7: sync /* Wait for all icbi to complete on bus */
isync
/*
* Re-point the IVPR at RAM
*/
mtspr IVPR,r10
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
addi r0,r10,in_ram - _start + _START_OFFSET
/*
* As IVPR is going to point RAM address,
* Make sure IVOR15 has valid opcode to support debugger
*/
mtspr IVOR15,r0
/*
* Re-point the IVPR at RAM
*/
mtspr IVPR,r10
mtlr r0
blr /* NEVER RETURNS! */
.globl in_ram

43
arch/powerpc/cpu/mpc8xxx/cpu.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Copyright 2009-2012 Freescale Semiconductor, Inc.
*
* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@ -37,82 +37,47 @@ DECLARE_GLOBAL_DATA_PTR;
struct cpu_type cpu_type_list [] = {
#if defined(CONFIG_MPC85xx)
CPU_TYPE_ENTRY(8533, 8533, 1),
CPU_TYPE_ENTRY(8533, 8533_E, 1),
CPU_TYPE_ENTRY(8535, 8535, 1),
CPU_TYPE_ENTRY(8535, 8535_E, 1),
CPU_TYPE_ENTRY(8536, 8536, 1),
CPU_TYPE_ENTRY(8536, 8536_E, 1),
CPU_TYPE_ENTRY(8540, 8540, 1),
CPU_TYPE_ENTRY(8541, 8541, 1),
CPU_TYPE_ENTRY(8541, 8541_E, 1),
CPU_TYPE_ENTRY(8543, 8543, 1),
CPU_TYPE_ENTRY(8543, 8543_E, 1),
CPU_TYPE_ENTRY(8544, 8544, 1),
CPU_TYPE_ENTRY(8544, 8544_E, 1),
CPU_TYPE_ENTRY(8545, 8545, 1),
CPU_TYPE_ENTRY(8545, 8545_E, 1),
CPU_TYPE_ENTRY(8547, 8547_E, 1),
CPU_TYPE_ENTRY(8547, 8547, 1),
CPU_TYPE_ENTRY(8548, 8548, 1),
CPU_TYPE_ENTRY(8548, 8548_E, 1),
CPU_TYPE_ENTRY(8555, 8555, 1),
CPU_TYPE_ENTRY(8555, 8555_E, 1),
CPU_TYPE_ENTRY(8560, 8560, 1),
CPU_TYPE_ENTRY(8567, 8567, 1),
CPU_TYPE_ENTRY(8567, 8567_E, 1),
CPU_TYPE_ENTRY(8568, 8568, 1),
CPU_TYPE_ENTRY(8568, 8568_E, 1),
CPU_TYPE_ENTRY(8569, 8569, 1),
CPU_TYPE_ENTRY(8569, 8569_E, 1),
CPU_TYPE_ENTRY(8572, 8572, 2),
CPU_TYPE_ENTRY(8572, 8572_E, 2),
CPU_TYPE_ENTRY(P1010, P1010, 1),
CPU_TYPE_ENTRY(P1010, P1010_E, 1),
CPU_TYPE_ENTRY(P1011, P1011, 1),
CPU_TYPE_ENTRY(P1011, P1011_E, 1),
CPU_TYPE_ENTRY(P1012, P1012, 1),
CPU_TYPE_ENTRY(P1012, P1012_E, 1),
CPU_TYPE_ENTRY(P1013, P1013, 1),
CPU_TYPE_ENTRY(P1013, P1013_E, 1),
CPU_TYPE_ENTRY(P1014, P1014_E, 1),
CPU_TYPE_ENTRY(P1014, P1014, 1),
CPU_TYPE_ENTRY(P1015, P1015_E, 1),
CPU_TYPE_ENTRY(P1015, P1015, 1),
CPU_TYPE_ENTRY(P1016, P1016_E, 1),
CPU_TYPE_ENTRY(P1016, P1016, 1),
CPU_TYPE_ENTRY(P1017, P1017, 1),
CPU_TYPE_ENTRY(P1017, P1017_E, 1),
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1020, P1020_E, 2),
CPU_TYPE_ENTRY(P1021, P1021, 2),
CPU_TYPE_ENTRY(P1021, P1021_E, 2),
CPU_TYPE_ENTRY(P1022, P1022, 2),
CPU_TYPE_ENTRY(P1022, P1022_E, 2),
CPU_TYPE_ENTRY(P1023, P1023, 2),
CPU_TYPE_ENTRY(P1023, P1023_E, 2),
CPU_TYPE_ENTRY(P1024, P1024, 2),
CPU_TYPE_ENTRY(P1024, P1024_E, 2),
CPU_TYPE_ENTRY(P1025, P1025, 2),
CPU_TYPE_ENTRY(P1025, P1025_E, 2),
CPU_TYPE_ENTRY(P2010, P2010, 1),
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2020, P2020_E, 2),
CPU_TYPE_ENTRY(P2040, P2040, 4),
CPU_TYPE_ENTRY(P2040, P2040_E, 4),
CPU_TYPE_ENTRY(P2041, P2041, 4),
CPU_TYPE_ENTRY(P2041, P2041_E, 4),
CPU_TYPE_ENTRY(P3041, P3041, 4),
CPU_TYPE_ENTRY(P3041, P3041_E, 4),
CPU_TYPE_ENTRY_MASK(P3060, P3060, 6, 0xf3),
CPU_TYPE_ENTRY_MASK(P3060, P3060_E, 6, 0xf3),
CPU_TYPE_ENTRY(P4040, P4040, 4),
CPU_TYPE_ENTRY(P4040, P4040_E, 4),
CPU_TYPE_ENTRY(P4080, P4080, 8),
CPU_TYPE_ENTRY(P4080, P4080_E, 8),
CPU_TYPE_ENTRY(P5010, P5010, 1),
CPU_TYPE_ENTRY(P5010, P5010_E, 1),
CPU_TYPE_ENTRY(P5020, P5020, 2),
CPU_TYPE_ENTRY(P5020, P5020_E, 2),
CPU_TYPE_ENTRY(BSC9130, 9130, 1),
CPU_TYPE_ENTRY(BSC9131, 9131, 1),
#elif defined(CONFIG_MPC86xx)
CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2),

31
arch/powerpc/include/asm/config_mpc85xx.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -122,6 +122,7 @@
#define CONFIG_MAX_CPUS 1
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2
@ -138,6 +139,7 @@
#elif defined(CONFIG_P1011)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@ -149,6 +151,7 @@
#elif defined(CONFIG_P1012)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@ -163,6 +166,7 @@
#elif defined(CONFIG_P1013)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_FSL_SATA_V2
@ -175,6 +179,7 @@
#define CONFIG_MAX_CPUS 1
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2
@ -190,6 +195,7 @@
#elif defined(CONFIG_P1015)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@ -201,6 +207,7 @@
#elif defined(CONFIG_P1016)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@ -228,6 +235,7 @@
#elif defined(CONFIG_P1020)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@ -238,6 +246,7 @@
#elif defined(CONFIG_P1021)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@ -251,6 +260,7 @@
#elif defined(CONFIG_P1022)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_FSL_SATA_V2
@ -276,6 +286,7 @@
#elif defined(CONFIG_P1024)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@ -287,6 +298,7 @@
#elif defined(CONFIG_P1025)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@ -301,6 +313,7 @@
#elif defined(CONFIG_P2010)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@ -309,6 +322,7 @@
#elif defined(CONFIG_P2020)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@ -335,6 +349,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@ -359,6 +374,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@ -446,6 +462,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
#define CONFIG_SYS_P4080_ERRATUM_CPU22
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
#define CONFIG_SYS_P4080_ERRATUM_SERDES9
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
@ -505,6 +522,18 @@
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_BSC9131)
#define CONFIG_MAX_CPUS 1
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#else
#error Processor type not defined for this platform
#endif

119
arch/powerpc/include/asm/immap_85xx.h
View file

@ -1,7 +1,7 @@
/*
* MPC85xx Internal Memory Map
*
* Copyright 2007-2011 Freescale Semiconductor, Inc.
* Copyright 2007-2012 Freescale Semiconductor, Inc.
*
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
@ -1934,7 +1934,11 @@ typedef struct ccsr_gur {
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
#else
#ifdef CONFIG_BSC9131
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
#else
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
#endif
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
#endif
#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
@ -2080,6 +2084,50 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_TDM 0x00014800
#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
#define MPC85xx_PMUXCR_SPI 0x00000000
#endif
#if defined(CONFIG_BSC9131)
#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
#endif
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
@ -2111,7 +2159,69 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
#define MPC85xx_PMUXCR2_USB 0x00150000
#endif
#if defined(CONFIG_BSC9131)
#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
u32 pmuxcr3;
#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
u32 pmuxcr4;
#else
u8 res6[8];
#endif
u32 devdisr; /* Device disable control */
#define MPC85xx_DEVDISR_PCI1 0x80000000
#define MPC85xx_DEVDISR_PCI2 0x40000000
@ -2166,7 +2276,14 @@ typedef struct ccsr_gur {
u32 ddrdllcr; /* DDR DLL control */
u8 res14[12];
u32 lbcdllcr; /* LBC DLL control */
#if defined(CONFIG_BSC9131)
u8 res15[12];
u32 halt_req_mask;
#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
u8 res18[232];
#else
u8 res15[248];
#endif
u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
u32 ddrioovcr; /* DDR IO Override Control */

2
arch/powerpc/include/asm/io.h
View file

@ -295,7 +295,7 @@ static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
#ifdef CONFIG_ADDR_MAP
return (void *)(addrmap_phys_to_virt(paddr));
return addrmap_phys_to_virt(paddr);
#else
return (void *)((unsigned long)paddr);
#endif

46
arch/powerpc/include/asm/processor.h
View file

@ -1036,7 +1036,7 @@
#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
/* Some parts define SVR[0:23] as the SOC version */
#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */
#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/
/* whether MPC8xxxE (i.e. has SEC) */
#if defined(CONFIG_MPC85xx)
@ -1055,87 +1055,55 @@
*/
#define SVR_8533 0x803400
#define SVR_8533_E 0x803C00
#define SVR_8535 0x803701
#define SVR_8535_E 0x803F01
#define SVR_8536 0x803700
#define SVR_8536_E 0x803F00
#define SVR_8540 0x803000
#define SVR_8541 0x807200
#define SVR_8541_E 0x807A00
#define SVR_8543 0x803200
#define SVR_8543_E 0x803A00
#define SVR_8544 0x803401
#define SVR_8544_E 0x803C01
#define SVR_8545 0x803102
#define SVR_8545_E 0x803902
#define SVR_8547_E 0x803901
#define SVR_8547 0x803101
#define SVR_8548 0x803100
#define SVR_8548_E 0x803900
#define SVR_8555 0x807100
#define SVR_8555_E 0x807900
#define SVR_8560 0x807000
#define SVR_8567 0x807501
#define SVR_8567_E 0x807D01
#define SVR_8568 0x807500
#define SVR_8568_E 0x807D00
#define SVR_8569 0x808000
#define SVR_8569_E 0x808800
#define SVR_8572 0x80E000
#define SVR_8572_E 0x80E800
#define SVR_P1010 0x80F100
#define SVR_P1010_E 0x80F900
#define SVR_P1011 0x80E500
#define SVR_P1011_E 0x80ED00
#define SVR_P1012 0x80E501
#define SVR_P1012_E 0x80ED01
#define SVR_P1013 0x80E700
#define SVR_P1013_E 0x80EF00
#define SVR_P1014 0x80F101
#define SVR_P1014_E 0x80F901
#define SVR_P1015 0x80E502
#define SVR_P1015_E 0x80ED02
#define SVR_P1016 0x80E503
#define SVR_P1016_E 0x80ED03
#define SVR_P1017 0x80F700
#define SVR_P1017_E 0x80FF00
#define SVR_P1020 0x80E400
#define SVR_P1020_E 0x80EC00
#define SVR_P1021 0x80E401
#define SVR_P1021_E 0x80EC01
#define SVR_P1022 0x80E600
#define SVR_P1022_E 0x80EE00
#define SVR_P1023 0x80F600
#define SVR_P1023_E 0x80FE00
#define SVR_P1024 0x80E402
#define SVR_P1024_E 0x80EC02
#define SVR_P1025 0x80E403
#define SVR_P1025_E 0x80EC03
#define SVR_P2010 0x80E300
#define SVR_P2010_E 0x80EB00
#define SVR_P2020 0x80E200
#define SVR_P2020_E 0x80EA00
#define SVR_P2040 0x821000
#define SVR_P2040_E 0x821800
#define SVR_P2041 0x821001
#define SVR_P2041_E 0x821801
#define SVR_P3041 0x821103
#define SVR_P3041_E 0x821903
#define SVR_P3060 0x820002
#define SVR_P3060_E 0x820802
#define SVR_P4040 0x820100
#define SVR_P4040_E 0x820900
#define SVR_P4080 0x820000
#define SVR_P4080_E 0x820800
#define SVR_P5010 0x822100
#define SVR_P5010_E 0x822900
#define SVR_P5020 0x822000
#define SVR_P5020_E 0x822800
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
#define SVR_8641D 0x809001
#define SVR_9130 0x860001
#define SVR_9130_E 0x860801
#define SVR_9131 0x860000
#define SVR_9131_E 0x860800
#define SVR_Unknown 0xFFFFFF
#define _GLOBAL(n)\

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#
# Copyright 2011-2012 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
#COBJS-y += bsc9131rdb_mux.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

137
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Overview
--------
- BSC9131 is integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
- It's MAPLE disabled personality is called 9231.
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port)
and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The e500 core subsystem within the Power Architecture consists of the following:
. 32-Kbyte L1 instruction cache
. 32-Kbyte L1 data cache
. 256-Kbyte L2 cache/L2 memory/L2 stash
. programmable interrupt controller (PIC)
. Debug support
. Timers
The SC3850 core subsystem consists of the following:
. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
. 32 Kbyte 8-way level 1 data cache (L1 DCache)
. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
. Memory management unit (MMU)
. Enhanced programmable interrupt controller (EPIC)
. Debug and profiling unit (DPU)
. Two 32-bit timers
BSC9131RDB board Overview
-------------------------
1Gbyte DDR3 (on board DDR)
128Mbyte 2K page size NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
USB-ULPI
eTSEC1: Connected to RGMII PHY
eTSEC2: Connected to RGMII PHY
DUART interface: supports one UARTs up to 115200 bps for console display
USIM connector
Frequency Combinations Supported
--------------------------------
Core MHz/CCB MHz/DDR(MT/s)
1. 1000/500/800
2. 800/400/667
Boot Methods Supported
-----------------------
1. NAND Flash
2. SPI Flash
Default Boot Method
--------------------
NAND boot
Building U-boot
--------------
To build the u-boot for BSC9131RDB:
1. NAND Flash
make BSC9131RDB_NAND
2. SPI Flash
make BSC9131RDB_SPIFLASH
Memory map
-----------
0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K
0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K
0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
Flashing Images
---------------
To place a new u-boot image in the NAND flash and then boot
with that new image temporarily, use this:
tftp 1000000 u-boot-nand.bin
nand erase 0 100000
nand write 1000000 0 100000
reset
Using the Device Tree Source File
---------------------------------
To create the DTB (Device Tree Binary) image file,
use a command similar to this:
dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
Likely, that .dts file will come from here;
linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
Booting Linux
-------------
Place a linux uImage in the TFTP disk area.
tftp 1000000 uImage
tftp 2000000 rootfs.ext2.gz.uboot
tftp c00000 bsc9131rdb.dtb
bootm 1000000 2000000 c00000

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board/freescale/bsc9131rdb/bsc9131rdb.c Normal file
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/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
MPC85xx_PMUXCR_IFC_AD_GPIO |
MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
return 0;
}
int checkboard(void)
{
struct cpu_type *cpu;
cpu = gd->cpu;
printf("Board: %sRDB\n", cpu->name);
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
fdt_fixup_dr_usb(blob, bd);
}
#endif

187
board/freescale/bsc9131rdb/ddr.c Normal file
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/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_DRAM_SIZE 1024
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{750, 850, &ddr_cfg_regs_800},
{0, 0, NULL}
};
unsigned long get_sdram_size(void)
{
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
}
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
phys_size_t fixed_sdram(void)
{
int i;
char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
phys_size_t ddr_size;
ulong ddr_freq, ddr_freq_mhz;
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, ddr_freq));
for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
sizeof(ddr_cfg_regs));
break;
}
}
if (fixed_ddr_parm_0[i].max_freq == 0) {
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, ddr_freq));
}
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
LAW_TRGT_IF_DDR_1) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
return ddr_size;
}
#else /* CONFIG_SYS_DDR_RAW_TIMING */
/* Micron MT41J256M8HX-15E */
dimm_params_t ddr_raw_timing = {
.n_ranks = 1,
.rank_density = 1073741824u,
.capacity = 1073741824u,
.primary_sdram_width = 32,
.ec_sdram_width = 0,
.registered_dimm = 0,
.mirrored_dimm = 0,
.n_row_addr = 15,
.n_col_addr = 10,
.n_banks_per_sdram_device = 8,
.edc_config = 0,
.burst_lengths_bitmask = 0x0c,
.tCKmin_X_ps = 1870,
.caslat_X = 0x1e << 4, /* 5,6,7,8 */
.tAA_ps = 13125,
.tWR_ps = 15000,
.tRCD_ps = 13125,
.tRRD_ps = 7500,
.tRP_ps = 13125,
.tRAS_ps = 37500,
.tRC_ps = 50625,
.tRFC_ps = 160000,
.tWTR_ps = 7500,
.tRTP_ps = 7500,
.refresh_rate_ps = 7800000,
.tFAW_ps = 37500,
};
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
unsigned int controller_number,
unsigned int dimm_number)
{
const char dimm_model[] = "Fixed DDR on board";
if ((controller_number == 0) && (dimm_number == 0)) {
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
}
return 0;
}
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
int i;
popts->clk_adjust = 6;
popts->cpo_override = 0x1f;
popts->write_data_delay = 2;
popts->half_strength_driver_enable = 1;
/* Write leveling override */
popts->wrlvl_en = 1;
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
popts->wrlvl_start = 0x8;
popts->trwt_override = 1;
popts->trwt = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
}
}
#endif /* CONFIG_SYS_DDR_RAW_TIMING */

31
board/freescale/bsc9131rdb/law.c Normal file
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@ -0,0 +1,31 @@
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
};
int num_law_entries = ARRAY_SIZE(law_table);

67
board/freescale/bsc9131rdb/tlb.c Normal file
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@ -0,0 +1,67 @@
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR (PA) */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
#if defined(CONFIG_SYS_RAMBOOT)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1M, 1)
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

36
board/freescale/common/fman.c
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@ -37,31 +37,33 @@
* ... update that Ethernet node's phy-handle property to point to the
* ethernet-phy node. This is how we link an Ethernet node to its PHY, so each
* PHY in a virtual MDIO node must have an alias.
*
* Returns 0 on success, or a negative FDT error code on error.
*/
void fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
const char *alias)
{
int offset, ph;
int offset;
unsigned int ph;
const char *path;
/* Get a path to the node that 'alias' points to */
path = fdt_get_alias(fdt, alias);
if (path) {
/* Get the offset of that node */
int off = fdt_path_offset(fdt, path);
if (off > 0)
ph = fdt_create_phandle(fdt, off);
else
return;
} else {
return ;
}
if (!path)
return -FDT_ERR_BADPATH;
/* failed to create a phandle */
if (ph <= 0)
return ;
/* Get the offset of that node */
offset = fdt_path_offset(fdt, path);
if (offset < 0)
return offset;
ph = fdt_create_phandle(fdt, offset);
if (!ph)
return -FDT_ERR_BADPHANDLE;
offset = fdt_node_offset_by_compat_reg(fdt, compat, addr);
if (offset > 0)
fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph));
if (offset < 0)
return offset;
return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph));
}

2
board/freescale/common/fman.h
View file

@ -20,7 +20,7 @@
#ifndef __FMAN_BOARD_HELPER__
#define __FMAN_BOARD_HELPER__
void fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
const char *alias);
#endif

7
board/freescale/mpc8536ds/mpc8536ds.c
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@ -1,5 +1,5 @@
/*
* Copyright 2008-2010, 2011 Freescale Semiconductor, Inc.
* Copyright 2008-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -290,5 +290,10 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
#ifdef CONFIG_HAS_FSL_MPH_USB
fdt_fixup_dr_usb(blob, bd);
#endif
}
#endif

212
board/freescale/p1010rdb/README Normal file
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@ -0,0 +1,212 @@
Overview
=========
The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
The P1010 is a cost-effective, low-power, highly integrated host processor
based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
that addresses the requirements of several routing, gateways, storage, consumer,
and industrial applications. Applications of interest include the main CPUs and
I/O processors in network attached storage (NAS), the voice over IP (VoIP)
router/gateway, and wireless LAN (WLAN) and industrial controllers.
The P1010RDB board features are as follows:
Memory subsystem:
- 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
- 32 Mbyte NOR flash single-chip memory
- 32 Mbyte NAND flash memory
- 256 Kbit M24256 I2C EEPROM
- 16 Mbyte SPI memory
- I2C Board EEPROM 128x8 bit memory
- SD/MMC connector to interface with the SD memory card
Interfaces:
- PCIe:
- Lane0: x1 mini-PCIe slot
- Lane1: x1 PCIe standard slot
- SATA:
- 1 internal SATA connector to 2.5” 160G SATA2 HDD
- 1 eSATA connector to rear panel
- 10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
- eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
- eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
- USB 2.0 port:
- x1 USB2.0 port via an external ULPI PHY to micro-AB connector
- x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
- FlexCAN ports:
- 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
interface;
- DUART interface:
- DUART interface: supports two UARTs up to 115200 bps for
console display
- RJ45 connectors are used for these 2 UART ports.
- TDM
- 2 FXS ports connected via an external SLIC to the TDM interface.
SLIC is controllled via SPI.
- 1 FXO port connected via a relay to FXS for switchover to POTS
Board connectors:
- Mini-ITX power supply connector
- JTAG/COP for debugging
IEEE Std. 1588 signals for test and measurement
Real-time clock on I2C bus
POR
- support critical POR setting changed via switch on board
PCB
- 6-layer routing (4-layer signals, 2-layer power and ground)
Physical Memory Map on P1010RDB
===============================
Address Start Address End Memory type Attributes
0x0000_0000 0x3fff_ffff DDR 1G Cacheable
0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
Serial Port Configuration on P1010RDB
=====================================
Configure the serial port of the attached computer with the following values:
-Data rate: 115200 bps
-Number of data bits: 8
-Parity: None
-Number of Stop bits: 1
-Flow Control: Hardware/None
Settings of DIP-switch
======================
SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
Note: 1 stands for 'on', 0 stands for 'off'
Setting of hwconfig
===================
If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
instead of to CAN/UART1.
Build and burn u-boot to NOR flash
==================================
1. Build u-boot.bin image
export ARCH=powerpc
export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
make P1010RDB_NOR
2. Burn u-boot.bin into NOR flash
=> tftp $loadaddr $uboot
=> protect off eff80000 +$filesize
=> erase eff80000 +$filesize
=> cp.b $loadaddr eff80000 $filesize
3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
Alternate NOR bank
==================
1. Burn u-boot.bin into alternate NOR bank
=> tftp $loadaddr $uboot
=> protect off eef80000 +$filesize
=> erase eef80000 +$filesize
=> cp.b $loadaddr eef80000 $filesize
2. Switch to alternate NOR bank
=> mw.b ffb00009 1
=> reset
or set SW1[8]= ON
SW1[8]= OFF: Upper bank used for booting start
SW1[8]= ON: Lower bank used for booting start
CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
0 - boot from upper 4 sectors
1 - boot from lower 4 sectors
Build and burn u-boot to NAND flash
===================================
1. Build u-boot.bin image
export ARCH=powerpc
export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
make P1010RDB_NAND
2. Burn u-boot-nand.bin into NAND flash
=> tftp $loadaddr $uboot-nand
=> nand erase 0 $filesize
=> nand write $loadaddr 0 $filesize
3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
Build and burn u-boot to SPI flash
==================================
1. Build u-boot-spi.bin image
make P1010RDB_SPIFLASH_config; make
Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
Download u-boot.bin to linux and you can find some config files
under /usr/share such as config_xx.dat. Do below command:
boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
u-boot-spi.bin
to generate u-boot-spi.bin.
2. Burn u-boot-spi.bin into SPI flash
=> tftp $loadaddr $uboot-spi
=> sf erase 0 100000
=> sf write $loadaddr 0 $filesize
3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
CPLD POR setting registers
==========================
1. Set POR switch selection register (addr 0xFFB00011) to 0.
2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
proper values.
If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
switch command by I2C.
3. Send reset command.
After reset, the new POR setting will be implemented.
Two examples are given in below:
Switch from NOR to NAND boot with default frequency:
=> i2c dev 0
=> i2c mw 18 1 f9
=> i2c mw 18 3 f0
=> mw.b ffb00011 0
=> mw.b ffb00017 1
=> reset
Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
=> i2c dev 0
=> i2c mw 18 1 f1
=> i2c mw 18 3 f0
=> mw.b ffb00011 0
=> mw.b ffb00014 2
=> mw.b ffb00015 5
=> mw.b ffb00016 3
=> mw.b ffb00017 f
=> reset
Boot Linux from network using TFTP on P1010RDB
==============================================
Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
=> tftp 1000000 uImage
=> tftp 2000000 p1010rdb.dtb
=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
=> bootm 1000000 3000000 2000000
Please contact your local field applications engineer or sales representative
to obtain related documents, such as P1010-RDB User Guide for details.

6
board/freescale/p1010rdb/ddr.c
View file

@ -101,7 +101,7 @@ unsigned long get_sdram_size(void)
cpu = gd->cpu;
/* P1014 and it's derivatives support max 16it DDR width */
if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E)
if (cpu->soc_ver == SVR_P1014)
ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
else
ddr_size = CONFIG_SYS_DRAM_SIZE;
@ -146,7 +146,7 @@ phys_size_t fixed_sdram(void)
cpu = gd->cpu;
/* P1014 and it's derivatives support max 16bit DDR width */
if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) {
if (cpu->soc_ver == SVR_P1014) {
ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1;
ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000;
@ -238,7 +238,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
cpu = gd->cpu;
/* P1014 and it's derivatives support max 16it DDR width */
if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E)
if (cpu->soc_ver == SVR_P1014)
popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {

60
board/freescale/p1010rdb/p1010rdb.c
View file

@ -190,7 +190,7 @@ int board_eth_init(bd_t *bis)
#endif
#ifdef CONFIG_TSEC3
/* P1014 and it's derivatives do not support eTSEC3 */
if (cpu->soc_ver != SVR_P1014 && cpu->soc_ver != SVR_P1014_E) {
if (cpu->soc_ver != SVR_P1014) {
SET_STD_TSEC_INFO(tsec_info[num], 3);
num++;
}
@ -252,6 +252,31 @@ void fdt_del_tdm(void *blob)
}
}
void fdt_del_sdhc(void *blob)
{
int nodeoff = 0;
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
"fsl,esdhc")) >= 0) {
fdt_del_node(blob, nodeoff);
}
}
void fdt_disable_uart1(void *blob)
{
int nodeoff;
nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
CONFIG_SYS_NS16550_COM2);
if (nodeoff > 0) {
fdt_status_disabled(blob, nodeoff);
} else {
printf("WARNING unable to set status for fsl,ns16550 "
"uart1: %s\n", fdt_strerror(nodeoff));
}
}
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
@ -276,24 +301,31 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
/* P1014 and it's derivatives don't support CAN and eTSEC3 */
if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) {
if (cpu->soc_ver == SVR_P1014) {
fdt_del_flexcan(blob);
fdt_del_node_and_alias(blob, "ethernet2");
}
#ifndef CONFIG_SDCARD
/* disable sdhc due to sdhc bug */
fdt_del_sdhc(blob);
if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
printf("fdt CAN");
fdt_del_tdm(blob);
fdt_del_spi_slic(blob);
}
#ifndef CONFIG_SPIFLASH
else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
printf("fdt TDM");
} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
fdt_del_flexcan(blob);
fdt_del_spi_flash(blob);
fdt_disable_uart1(blob);
} else {
/*
* If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
* explicitly, defaultly spi_cs_sel to spi-flash instead of
* to tdm/slic.
*/
fdt_del_tdm(blob);
fdt_del_flexcan(blob);
fdt_disable_uart1(blob);
}
#endif
#endif
}
#endif
@ -309,10 +341,7 @@ int misc_init_r(void)
MPC85xx_PMUXCR_CAN2_TDM |
MPC85xx_PMUXCR_CAN2_UART);
out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
}
#ifndef CONFIG_SPIFLASH
if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
printf("TDM");
} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
MPC85xx_PMUXCR_CAN1_UART);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
@ -321,8 +350,11 @@ int misc_init_r(void)
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
}
#endif
} else {
/* defaultly spi_cs_sel to flash */
out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
}
return 0;
}
#endif

6
board/freescale/p1022ds/p1022ds.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* Copyright 2010-2012 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
@ -337,6 +337,10 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_HAS_FSL_DR_USB
fdt_fixup_dr_usb(blob, bd);
#endif
FT_FSL_PCI_SETUP;
#ifdef CONFIG_FSL_SGMII_RISER

5
board/freescale/p1023rds/p1023rds.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* Copyright 2010-2012 Freescale Semiconductor, Inc.
*
* Authors: Roy Zang <tie-fei.zang@freescale.com>
* Chunhe Lan <b25806@freescale.com>
@ -202,6 +202,9 @@ void ft_board_setup(void *blob, bd_t *bd)
do_fixup_by_path_string(blob, "nor_flash", "status", "disabled");
do_fixup_by_path_string(blob, "nand_flash", "status", "okay");
#endif
#ifdef CONFIG_HAS_FSL_DR_USB
fdt_fixup_dr_usb(blob, bd);
#endif
fdt_fixup_fman_ethernet(blob);
}

6
board/freescale/p1_p2_rdb/ddr.c
View file

@ -204,8 +204,7 @@ phys_size_t fixed_sdram (void)
cpu = gd->cpu;
/* P1020 and it's derivatives support max 32bit DDR width */
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
} else {
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
@ -232,8 +231,7 @@ phys_size_t fixed_sdram (void)
strmhz(buf, ddr_freq));
/* P1020 and it's derivatives support max 32bit DDR width */
if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
ddr_cfg_regs.cs[0].bnds = 0x0000001F;
}

4
board/freescale/p2020come/p2020come.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
* Copyright 2009,2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -282,6 +282,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_HAS_FSL_DR_USB
fdt_fixup_dr_usb(blob, bd);
#endif
}
#endif

6
board/freescale/p2020ds/p2020ds.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2007-2011 Freescale Semiconductor, Inc.
* Copyright 2007-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -257,6 +257,10 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_HAS_FSL_DR_USB
fdt_fixup_dr_usb(blob, bd);
#endif
FT_FSL_PCI_SETUP;
#ifdef CONFIG_FSL_SGMII_RISER

6
board/freescale/p2041rdb/p2041rdb.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011,2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -211,6 +211,10 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_PCI
pci_of_setup(blob, bd);
#endif

6
board/freescale/p3060qds/p3060qds.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -323,6 +323,10 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_PCI
pci_of_setup(blob, bd);
#endif

1
boards.cfg
View file

@ -775,6 +775,7 @@ P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freesca
P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER
P5020DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH
stxgp3 powerpc mpc85xx stxgp3 stx
stxssa powerpc mpc85xx stxssa stx - stxssa
stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M

166
doc/README.mpc85xx Normal file
View file

@ -0,0 +1,166 @@
External Debug Support
----------------------
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG). In particular, for the debugger to
be able to receive control after a single step or breakpoint:
- MSR[DE] must be set
- A valid opcode must be fetchable, through the MMU, from the debug
exception vector (IVPR + IVOR15).
To maximize the time during which this requirement is met, U-Boot sets MSR[DE]
immediately on entry and keeps it set. It also uses a temporary TLB to keep a
mapping to a valid opcode at the debug exception vector, even if we normally
don't support exception vectors being used that early, and that's not the area
where U-Boot currently executes from.
Note that there may still be some small windows where debugging will not work,
such as in between updating IVPR and IVOR15.
Config Switches:
----------------
Please refer README section "MPC85xx External Debug Support"
Major Config Switches during various boot Modes
----------------------------------------------
NOR boot
!defined(CONFIG_SYS_RAMBOOT)
NOR boot Secure
!defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
RAMBOOT(SD, SPI & NAND boot)
defined(CONFIG_SYS_RAMBOOT)
RAMBOOT Secure (SD, SPI & NAND)
defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
NAND SPL BOOT
defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
TLB Entries during u-boot execution
-----------------------------------
Note: Sequence number is in order of execution
A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
1) TLB entry to overcome e500 v1/v2 debug restriction
Location : Label "_start_e500"
TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
Properties : 256K, AS0, I, IPROT
2) TLB entry for working in AS1
Location : Label "create_init_ram_area"
TLB Entry : 15
EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
Properties : 1M, AS1, I, G, IPROT
3) TLB entry for the stack during AS1
Location : Lable "create_init_ram_area"
TLB Entry : 14
EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
Properties : 16K, AS1, IPROT
4) TLB entry for CCSRBAR during AS1 execution
Location : cpu_init_early_f
TLB Entry : 13
EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
Properties : 1M, AS1, I, G
5) Invalidate unproctected TLB Entries
Location : cpu_init_early_f
Invalidated: 13
6) Create TLB entries as per boards/freescale/<board>/tlb.c
Location : cpu_init_early_f --> init_tlbs()
Properties : ..., AS0, ...
Please note It can overwrites previous TLB Entries.
7) Disable TLB Entries of AS1
Location : cpu_init_f --> disable_tlb()
Disable : 15, 14
8) Update Flash's TLB entry
Location : Board_init_r
TLB entry : Search from TLB entries
EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
Properties : Board specific size, AS0, I, G, IPROT
B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
1) TLB entry to overcome e500 v1/v2 debug restriction
Location : Label "_start_e500"
TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
#if defined(CONFIG_SECURE_BOOT)
EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
Properties : 1M, AS1, I, G, IPROT
#else
EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
Properties : 4M, AS0, I, G, IPROT
#endif
2) TLB entry for working in AS1
Location : Label "create_init_ram_area"
TLB Entry : 15
#if defined(CONFIG_SECURE_BOOT)
EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
Properties : 1M, AS1, I, G, IPROT
#else
EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
Properties : 4M, AS1, I, G, IPROT
#endif
3) TLB entry for the stack during AS1
Location : Lable "create_init_ram_area"
TLB Entry : 14
EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
Properties : 16K, AS1, IPROT
4) TLB entry for CCSRBAR during AS1 execution
Location : cpu_init_early_f
TLB Entry : 13
EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
Properties : 1M, AS1, I, G
5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Location : cpu_init_early_f
TLB Entry : 9
EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR
Properties : 1M, AS1, I
6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr
Location : cpu_init_early_f --> setup_ifc
TLB Entry : Get Flash TLB
EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
Properties : 4M, AS1, I, G, IPROT
7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction
Location : cpu_init_early_f --> setup_ifc
TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
Properties : 4M, AS0, I, G, IPROT
8) Invalidate unproctected TLB Entries
Location : cpu_init_early_f
Invalidated: 13, 9
9) Create TLB entries as per boards/freescale/<board>/tlb.c
Location : cpu_init_early_f --> init_tlbs()
Properties : ..., AS0, ...
Note: It can overwrites previous TLB Entries
10) Disable TLB Entries of AS1
Location : cpu_init_f --> disable_tlb()
Disable : 15, 14
11) Create DDR's TLB entriy
Location : Board_init_f -> init_func_ram -> initdram
TLB entry : Search free TLB entry
12) Update Flash's TLB entry
Location : Board_init_r
TLB entry : Search from TLB entries
EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
Properties : Board specific size, AS0, I, G, IPROT

2
include/addr_map.h
View file

@ -22,7 +22,7 @@
#include <asm/types.h>
extern phys_addr_t addrmap_virt_to_phys(void *vaddr);
extern unsigned long addrmap_phys_to_virt(phys_addr_t paddr);
extern void *addrmap_phys_to_virt(phys_addr_t paddr);
extern void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr,
phys_size_t size, int idx);

428
include/configs/BSC9131RDB.h Normal file
View file

@ -0,0 +1,428 @@
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* BSC9131 RDB board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#ifdef CONFIG_BSC9131RDB
#define CONFIG_BSC9131
#define CONFIG_NAND_FSL_IFC
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE 0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* enable branch predition */
#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x01ffffff
/* DDR Setup */
#define CONFIG_FSL_DDR3
#undef CONFIG_SYS_DDR_RAW_TIMING
#undef CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#ifndef __ASSEMBLY__
extern unsigned long get_sdram_size(void);
#endif
#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
#define CONFIG_SYS_DDR_RCW_1 0x00000000
#define CONFIG_SYS_DDR_RCW_2 0x00000000
#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
#define CONFIG_SYS_DDR_TIMING_4 0x00000001
#define CONFIG_SYS_DDR_TIMING_5 0x02401400
#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
/* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
/* CONFIG_SYS_IMMR */
/*
* Memory map
*
* 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
* 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
* 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
* 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
* 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
* 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
* 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
* 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
*
*/
/*
* IFC Definitions
*/
#define CONFIG_SYS_NO_FLASH
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* NAND Flash Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x08) \
| FTIM0_NAND_TWP(0x06) \
| FTIM0_NAND_TWCHT(0x03) \
| FTIM0_NAND_TWH(0x04))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x18) \
| FTIM1_NAND_TWBE(0x23) \
| FTIM1_NAND_TRR(0x08) \
| FTIM1_NAND_TRP(0x05))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
| FTIM2_NAND_TREH(0x04) \
| FTIM2_NAND_TWHRE(0x3f))
#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x22)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NAND */
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
/*
* Pass open firmware flat tree
*/
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
#define CONFIG_SYS_I2C_OFFSET 0x3000
/* I2C EEPROM */
#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_CMD_I2C
#define CONFIG_FSL_ESPI
/* eSPI - Enhanced SPI */
#ifdef CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 3
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
/*
* Environment
*/
#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x400
#endif
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SETEXPR
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_STORAGE
#define CONFIG_HAS_FSL_DR_USB
#endif
/*
* Environment Configuration
*/
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#endif
#define CONFIG_HOSTNAME BSC9131rdb
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"loadaddr=1000000\0" \
"bootfile=uImage\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=bsc9131rdb.dtb\0" \
"bdev=sda1\0" \
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
"othbootargs=ramdisk_size=600000 \0" \
"usbext2boot=setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs; " \
"usb start;" \
"ext2load usb 0:4 $loadaddr $bootfile;" \
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs; " \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
#endif /* __CONFIG_H */

5
include/configs/MPC8536DS.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2007-2009,2010-2011 Freescale Semiconductor, Inc.
* Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -711,6 +711,8 @@
/*
* USB
*/
#define CONFIG_HAS_FSL_MPH_USB
#ifdef CONFIG_HAS_FSL_MPH_USB
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
@ -719,6 +721,7 @@
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_STORAGE
#endif
#endif
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
#define CONFIG_CMD_EXT2

48
include/configs/P1022DS.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* Copyright 2010-2012 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
@ -433,6 +433,8 @@
/*
* USB
*/
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
@ -442,6 +444,7 @@
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_FAT
#endif
#endif
/*
* Miscellaneous configurable options
@ -487,35 +490,30 @@
#define CONFIG_LOADADDR 1000000
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#define CONFIG_BOOTARGS
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
"perf_mode=stable\0" \
"memctl_intlv_ctl=2\0" \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=uramdisk\0" \
"fdtaddr=c00000\0" \
"fdtfile=p1022ds.dtb\0" \
"bdev=sda3\0" \
"diuregs=md e002c000 1d\0" \
"dium=mw e002c01c\0" \
"diuerr=md e002c014 1\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \
"erase $ubootaddr +$filesize && " \
"cp.b $loadaddr $ubootaddr $filesize && " \
"protect on $ubootaddr +$filesize && " \
"cmp.b $loadaddr $ubootaddr $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=p1022ds.dtb\0" \
"bdev=sda3\0" \
"hwconfig=esdhc;audclk:12\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
@ -524,14 +522,14 @@
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \

5
include/configs/P1023RDS.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* Copyright 2010-2012 Freescale Semiconductor, Inc.
*
* Authors: Roy Zang <tie-fei.zang@freescale.com>
* Chunhe Lan <b25806@freescale.com>
@ -441,6 +441,8 @@ extern unsigned long get_clock_freq(void);
/*
* USB
*/
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
@ -453,6 +455,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
#endif
/*
* Miscellaneous configurable options

6
include/configs/P2020COME.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
* Copyright 2009-2010,2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -396,6 +396,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif /* CONFIG_MMC */
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
@ -403,7 +405,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_STORAGE
#define CONFIG_HAS_FSL_DR_USB
#endif
#endif
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)

27
include/configs/P2020DS.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2007-2011 Freescale Semiconductor, Inc.
* Copyright 2007-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -128,7 +128,6 @@
#else
#define CONFIG_FSL_DDR3 1
#endif
#undef CONFIG_FSL_DDR_INTERACTIVE
/* ECC will be enabled based on perf_mode environment variable */
/* #define CONFIG_DDR_ECC */
@ -207,8 +206,6 @@
*
*/
#undef CONFIG_CLOCKS_IN_MHZ
/*
* Memory map
*
@ -251,7 +248,6 @@
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
@ -373,7 +369,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
@ -391,7 +387,6 @@
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
@ -526,17 +521,6 @@
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_RTL8139
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#define CONFIG_SCSI_AHCI
@ -563,7 +547,6 @@
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define CONFIG_PIXIS_SGMII_CMD
#define CONFIG_FSL_SGMII_RISER 1
#define SGMII_RISER_PHY_OFFSET 0x1b
@ -643,6 +626,8 @@
/*
* USB
*/
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
@ -651,8 +636,7 @@
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
#endif
/*
* SDHC/MMC
@ -729,7 +713,6 @@
#define CONFIG_LOADADDR 1000000
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BAUDRATE 115200

8
include/configs/P2041RDB.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -570,11 +570,17 @@ unsigned long get_board_sys_clk(unsigned long dummy);
/*
* USB
*/
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_HAS_FSL_MPH_USB
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#define CONFIG_CMD_EXT2
#define CONFIG_MMC

8
include/configs/corenet_ds.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Copyright 2009-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -656,13 +656,17 @@
/*
* USB
*/
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_HAS_FSL_MPH_USB
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_CMD_EXT2
#define CONFIG_HAS_FSL_DR_USB
#endif
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC

19
lib/addr_map.c
View file

@ -47,26 +47,29 @@ phys_addr_t addrmap_virt_to_phys(void * vaddr)
return (phys_addr_t)(~0);
}
unsigned long addrmap_phys_to_virt(phys_addr_t paddr)
void *addrmap_phys_to_virt(phys_addr_t paddr)
{
int i;
for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++) {
u64 base, upper, addr;
phys_addr_t base, upper;
if (address_map[i].size == 0)
continue;
addr = (u64)paddr;
base = (u64)(address_map[i].paddr);
upper = (u64)(address_map[i].size) + base - 1;
base = address_map[i].paddr;
upper = address_map[i].size + base - 1;
if (addr >= base && addr <= upper) {
return paddr - address_map[i].paddr + address_map[i].vaddr;
if (paddr >= base && paddr <= upper) {
phys_addr_t offset;
offset = address_map[i].paddr - address_map[i].vaddr;
return (void *)(unsigned long)(paddr - offset);
}
}
return (unsigned long)(~0);
return (void *)(~0);
}
void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr,