From 1ac4f320bf0b593aa0a741f2d649a8ece8838672 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 2 Apr 2008 13:41:21 +0200 Subject: [PATCH 1/4] mpc837xerdb: Fix warning: implicit declaration of function 'fdt_fixup_dr_usb' Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Kim Phillips --- board/freescale/mpc837xerdb/mpc837xerdb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index e054f4e44d..f73fd5aa55 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -16,10 +16,10 @@ #include #include #include +#include #include #include - #if defined(CFG_DRAM_TEST) int testdram(void) From 2000784818f043db7ca60e2846a72d097766b894 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Thu, 3 Apr 2008 16:28:29 +0800 Subject: [PATCH 2/4] mpc83xx: Fix the SATA clock setting of 837x targets Currently the SATA controller clock is configured as CSB clock, usually the CSB clock is 400/333/266MHz. However, The SATA IP block is only guaranteed to operate up to 200 MHz as stated in the HW spec. The bug is reported by Joe D'Abbraccio This patch makes the SATA clock as half of CSB clock. Signed-off-by: Dave Liu Signed-off-by: Kim Phillips --- include/configs/MPC837XEMDS.h | 2 +- include/configs/MPC837XERDB.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 7c4e76e273..7fc0f7ef85 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -96,7 +96,7 @@ */ #define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ #define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ -#define CFG_SCCR_SATACM SCCR_SATACM_1 /* CSB:SATA[0:3] = 1:1 */ +#define CFG_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ /* * System IO Config diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index eaac525a35..c698ff84c6 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -108,7 +108,7 @@ /* System Clock Configuration Register */ #define CFG_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ #define CFG_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ -#define CFG_SCCR_SATACM SCCR_SATACM_1 /* SATA1-4 clock mode (0-3) */ +#define CFG_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ /* * System IO Config From 5fb5a689d822ca61e814bd523fc930af335242fa Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Mon, 31 Mar 2008 17:05:12 +0800 Subject: [PATCH 3/4] mpc83xx: Fix the bug of serdes initialization Currently the serdes will not be initializated due to the partid's error. Signed-off-by: Dave Liu Signed-off-by: Kim Phillips --- board/freescale/mpc837xemds/mpc837xemds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index f7cd5fe176..40a505b1d4 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -36,7 +36,7 @@ int board_early_init_f(void) u32 spridr = in_be32(&immr->sysconf.spridr); /* we check only part num, and don't look for CPU revisions */ - switch (spridr) { + switch (PARTID_NO_E(spridr)) { case SPR_8377: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); From 3f9c542d3d69b1a10a5e193e779133a0454d1f44 Mon Sep 17 00:00:00 2001 From: Lee Nipper Date: Thu, 10 Apr 2008 09:35:06 -0500 Subject: [PATCH 4/4] mpc83xx: Update DIMM data bus width test to support 40-bit width 32-bit wide ECC memory modules report 40-bit width. Changed the DIMM data bus width test to 'less than 64' instead of 'equal 32'. Signed-off-by: Lee Nipper Signed-off-by: Kim Phillips --- cpu/mpc83xx/spd_sdram.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 97ac7bb3d9..70cd410298 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -601,7 +601,7 @@ long int spd_sdram() debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); /* Check DIMM data bus width */ - if (spd.dataw_lsb == 0x20) { + if (spd.dataw_lsb < 64) { if (spd.mem_type == SPD_MEMTYPE_DDR) burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ else @@ -763,7 +763,7 @@ long int spd_sdram() sdram_cfg |= SDRAM_CFG_RD_EN; /* The DIMM is 32bit width */ - if (spd.dataw_lsb == 0x20) { + if (spd.dataw_lsb < 64) { if (spd.mem_type == SPD_MEMTYPE_DDR) sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE; if (spd.mem_type == SPD_MEMTYPE_DDR2)