GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-20 22:21:41 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

imx: mx7: implement functions to boot auxiliary core

Browse source 
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.

arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2016-01-28 16:55:07 +08:00 • committed by Stefano Babic
parent 3fe0b10460
commit 83703a1ccf
2 changed files with 41 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

36
arch/arm/cpu/armv7/mx7/soc.c
View file

@ -211,6 +211,42 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
}
#endif
#ifdef CONFIG_IMX_BOOTAUX
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{
u32 stack, pc;
struct src *src_reg = (struct src *)SRC_BASE_ADDR;
if (!boot_private_data)
return 1;
stack = *(u32 *)boot_private_data;
pc = *(u32 *)(boot_private_data + 4);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
/* Enable M4 */
clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
SRC_M4RCR_ENABLE_M4_MASK);
return 0;
}
int arch_auxiliary_core_check_up(u32 core_id)
{
uint32_t val;
struct src *src_reg = (struct src *)SRC_BASE_ADDR;
val = readl(&src_reg->m4rcr);
if (val & 0x00000001)
return 0; /* assert in reset */
return 1;
}
#endif
void set_wdog_reset(struct wdog_regs *wdog)
{
u32 reg = readw(&wdog->wcr);

5
arch/arm/include/asm/arch-mx7/imx-regs.h
View file

@ -263,6 +263,11 @@ struct src {
u32 ddrc_rcr;
};
#define SRC_M4RCR_M4C_NON_SCLR_RST_OFFSET 0
#define SRC_M4RCR_M4C_NON_SCLR_RST_MASK (1 << 0)
#define SRC_M4RCR_ENABLE_M4_OFFSET 3
#define SRC_M4RCR_ENABLE_M4_MASK (1 << 3)
/* GPR0 Bit Fields */
#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u
#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0