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Decreases code size of the nand_spl

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The canyonland boards nand_spl size is just under the maximum 4KByte size. This
patch decreases the size of the nand_spl to make a previous commit - commit
65a9db7be0 - fit in the nand_spl.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Alex Waterman 2011-05-04 09:10:15 -04:00 • committed by Scott Wood
parent 91081e01b1
commit 8370978318
1 changed files with 10 additions and 8 deletions
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18
nand_spl/nand_boot.c
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@ -77,6 +77,8 @@ static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8
{ {
struct nand_chip *this = mtd->priv; struct nand_chip *this = mtd->priv;
int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
if (this->dev_ready) if (this->dev_ready)
while (!this->dev_ready(mtd)) while (!this->dev_ready(mtd))
@ -95,25 +97,25 @@ static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8
offs >>= 1; offs >>= 1;
/* Begin command latch cycle */ /* Begin command latch cycle */
this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
/* Set ALE and clear CLE to start address cycle */ /* Set ALE and clear CLE to start address cycle */
/* Column address */ /* Column address */
this->cmd_ctrl(mtd, offs & 0xff, hwctrl(mtd, offs & 0xff,
NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
this->cmd_ctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */ /* Row address */
this->cmd_ctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff), hwctrl(mtd, ((page_addr >> 8) & 0xff),
NAND_CTRL_ALE); /* A[27:20] */ NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
/* One more address cycle for devices > 128MiB */ /* One more address cycle for devices > 128MiB */
this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, hwctrl(mtd, (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE); /* A[31:28] */ NAND_CTRL_ALE); /* A[31:28] */
#endif #endif
/* Latch in address */ /* Latch in address */
this->cmd_ctrl(mtd, NAND_CMD_READSTART, hwctrl(mtd, NAND_CMD_READSTART,
NAND_CTRL_CLE | NAND_CTRL_CHANGE); NAND_CTRL_CLE | NAND_CTRL_CHANGE);
this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
/* /*
* Wait a while for the data to be ready * Wait a while for the data to be ready