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Decreases code size of the nand_spl
The canyonland boards nand_spl size is just under the maximum 4KByte size. This
patch decreases the size of the nand_spl to make a previous commit - commit
65a9db7be0
- fit in the nand_spl.
Signed-off-by: Alex Waterman <awaterman@dawning.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
parent
91081e01b1
commit
8370978318
1 changed files with 10 additions and 8 deletions
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@ -77,6 +77,8 @@ static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8
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{
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{
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struct nand_chip *this = mtd->priv;
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struct nand_chip *this = mtd->priv;
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int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
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int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
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void (*hwctrl)(struct mtd_info *mtd, int cmd,
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unsigned int ctrl) = this->cmd_ctrl;
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if (this->dev_ready)
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if (this->dev_ready)
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while (!this->dev_ready(mtd))
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while (!this->dev_ready(mtd))
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@ -95,25 +97,25 @@ static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8
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offs >>= 1;
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offs >>= 1;
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/* Begin command latch cycle */
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/* Begin command latch cycle */
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this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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/* Set ALE and clear CLE to start address cycle */
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/* Set ALE and clear CLE to start address cycle */
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/* Column address */
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/* Column address */
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this->cmd_ctrl(mtd, offs & 0xff,
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hwctrl(mtd, offs & 0xff,
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NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
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NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
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this->cmd_ctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
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hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
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/* Row address */
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/* Row address */
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this->cmd_ctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
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hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
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this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff),
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hwctrl(mtd, ((page_addr >> 8) & 0xff),
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NAND_CTRL_ALE); /* A[27:20] */
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NAND_CTRL_ALE); /* A[27:20] */
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#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
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#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
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/* One more address cycle for devices > 128MiB */
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/* One more address cycle for devices > 128MiB */
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this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
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hwctrl(mtd, (page_addr >> 16) & 0x0f,
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NAND_CTRL_ALE); /* A[31:28] */
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NAND_CTRL_ALE); /* A[31:28] */
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#endif
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#endif
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/* Latch in address */
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/* Latch in address */
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this->cmd_ctrl(mtd, NAND_CMD_READSTART,
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hwctrl(mtd, NAND_CMD_READSTART,
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NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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/*
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/*
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* Wait a while for the data to be ready
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* Wait a while for the data to be ready
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