From 26858a3ee26eaf3a3e849089705c182732fa99f8 Mon Sep 17 00:00:00 2001 From: Jean-Philippe ROMAIN Date: Wed, 9 Sep 2020 15:24:32 +0200 Subject: [PATCH 01/11] configs: stm32mp1: enable fastboot support of eMMC boot partition Activate fastboot support on boot partition for eMMC, mmc1 device on STMicroelectronics board (EV1). Signed-off-by: Jean-Philippe ROMAIN Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32mp15_basic_defconfig | 5 +++++ configs/stm32mp15_trusted_defconfig | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index d3e5775a5a..b816f26011 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -79,6 +79,11 @@ CONFIG_FASTBOOT_BUF_SIZE=0x02000000 CONFIG_FASTBOOT_USB_DEV=1 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" +CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" CONFIG_GPIO_HOG=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index d392b0ff2a..5e81e61262 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -58,6 +58,11 @@ CONFIG_FASTBOOT_BUF_SIZE=0x02000000 CONFIG_FASTBOOT_USB_DEV=1 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" +CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" CONFIG_GPIO_HOG=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y From f35ce379feffea0a7a2d52c599992dadb742378f Mon Sep 17 00:00:00 2001 From: Jean-Philippe ROMAIN Date: Wed, 9 Sep 2020 15:24:33 +0200 Subject: [PATCH 02/11] configs: stm32mp1: enable the fastboot oem command format Enable the fastboot oem command format and set the variable "partitions" with default eMMC partitions list. Signed-off-by: Patrick Delaunay Signed-off-by: Jean-Philippe ROMAIN Reviewed-by: Patrice Chotard --- configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + include/configs/stm32mp1.h | 14 ++++++++++++++ 3 files changed, 16 insertions(+) diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index b816f26011..9c207d0b04 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -84,6 +84,7 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_GPIO_HOG=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 5e81e61262..8ce1d79673 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -63,6 +63,7 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_GPIO_HOG=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 863b652ca4..c5539285af 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -132,6 +132,19 @@ "run distro_bootcmd;" \ "fi;\0" +#ifdef CONFIG_FASTBOOT_CMD_OEM_FORMAT +/* eMMC default partitions for fastboot command: oem format */ +#define PARTS_DEFAULT \ + "partitions=" \ + "name=ssbl,size=2M;" \ + "name=bootfs,size=64MB,bootable;" \ + "name=vendorfs,size=16M;" \ + "name=rootfs,size=746M;" \ + "name=userfs,size=-\0" +#else +#define PARTS_DEFAULT +#endif + #include /* @@ -150,6 +163,7 @@ "altbootcmd=run bootcmd\0" \ "env_check=if env info -p -d -q; then env save; fi\0" \ STM32MP_BOOTCMD \ + PARTS_DEFAULT \ BOOTENV \ "boot_net_usb_start=true\0" From 6c57154925c0f62c0c12430a74bf57911e16e8d4 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 9 Sep 2020 15:24:34 +0200 Subject: [PATCH 03/11] configs: stm32mp1: enable the fastboot oem command partconf Enable the fastboot oem command partconf, used to select the correct eMMC boot partition, with same format than 'mmc partconf' with parameter: boot_ack boot_partition On stm32mp1 family: - boot_ack = 1 (Boot Acknowledge is needed by ROM code) - boot_partition = 1 or 2 (Boot partition 1 / 2 enabled for boot) So on EV1 board the expected commands to select boot partition 1 or 2 $> fastboot oem partconf:1 1 $> fastboot oem partconf:1 2 Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 9c207d0b04..836bcee39d 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -85,6 +85,7 @@ CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_GPIO_HOG=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 8ce1d79673..1846e90922 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -64,6 +64,7 @@ CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_GPIO_HOG=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y From 8c005c731f155e73b742ec6a4de1ba7e0b1a8bf9 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 9 Sep 2020 15:24:35 +0200 Subject: [PATCH 04/11] configs: stm32mp1: enable the fastboot oem command bootbus Enable the fastboot oem command bootbus, used to configure the eMMC boot behavior, with same format than 'mmc bootbus' and with parameter: boot_bus_width reset_boot_bus_width boot_mode On stm32mp1 boards the expected command is $> fastboot oem partconf:0 0 0 Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 836bcee39d..def6a51b40 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -86,6 +86,7 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y +CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y CONFIG_GPIO_HOG=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 1846e90922..da31b74cde 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -65,6 +65,7 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y +CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y CONFIG_GPIO_HOG=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y From 54f5bf3d61084c15a9e364ac7a5fdede7c1c780e Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 20 Jan 2021 13:43:39 +0100 Subject: [PATCH 05/11] pinctrl: stmfx: Fix pin configuration issue pin-controller pin's name must be equal to pin's name used in device tree with "pins" DT property. Issue detected on stm32mp157c-ev1 board with goodix touchscreen. In DT, the goodix's pin is declared in DT with the node: goodix_pins: goodix { pins = "gpio14"; bias-pull-down; }; Whereas in stmfx pin-controller driver, pin's name are equal to "stmfx_gpioxx" where xx is the pin number. This lead to not configure stmfx's pins at probe because pins is identified by its name (see pinctrl_pin_name_to_selector() in pinctrl-generic.c) and stmfx pin "gpio14" can't be found. To fix this issue, come back to the original stmfx pin's name. Revert "pinctrl: stmfx: update pin name" This reverts commit 38d30cdcd65c73eeefac5efa328ad444a53b77dd. Signed-off-by: Patrice Chotard Tested-by: Patrick DELAUNAY Reviewed-by: Patrick Delaunay --- drivers/pinctrl/pinctrl-stmfx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 7cf08dbddd..b4baf357dd 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -343,8 +343,8 @@ static int stmfx_pinctrl_get_pins_count(struct udevice *dev) } /* - * STMFX pins[15:0] are called "stmfx_gpio[15:0]" - * and STMFX pins[23:16] are called "stmfx_agpio[7:0]" + * STMFX pins[15:0] are called "gpio[15:0]" + * and STMFX pins[23:16] are called "agpio[7:0]" */ #define MAX_PIN_NAME_LEN 7 static char pin_name[MAX_PIN_NAME_LEN]; @@ -352,9 +352,9 @@ static const char *stmfx_pinctrl_get_pin_name(struct udevice *dev, unsigned int selector) { if (selector < STMFX_MAX_GPIO) - snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_gpio%u", selector); + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); else - snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_agpio%u", selector - 16); + snprintf(pin_name, MAX_PIN_NAME_LEN, "agpio%u", selector - 16); return pin_name; } From ca5cc312d4bea03a106dd36026ae637b19fa5599 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 20 Jan 2021 13:43:40 +0100 Subject: [PATCH 06/11] pinctrl: stmfx: Use PINNAME_SIZE for pin's name size Instead of redefining a pin's name size, use PINNAME_SIZE defined in include/dm/pinctrl.h Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/pinctrl/pinctrl-stmfx.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index b4baf357dd..1a8d0a3a35 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -346,15 +346,14 @@ static int stmfx_pinctrl_get_pins_count(struct udevice *dev) * STMFX pins[15:0] are called "gpio[15:0]" * and STMFX pins[23:16] are called "agpio[7:0]" */ -#define MAX_PIN_NAME_LEN 7 -static char pin_name[MAX_PIN_NAME_LEN]; +static char pin_name[PINNAME_SIZE]; static const char *stmfx_pinctrl_get_pin_name(struct udevice *dev, unsigned int selector) { if (selector < STMFX_MAX_GPIO) - snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + snprintf(pin_name, PINNAME_SIZE, "gpio%u", selector); else - snprintf(pin_name, MAX_PIN_NAME_LEN, "agpio%u", selector - 16); + snprintf(pin_name, PINNAME_SIZE, "agpio%u", selector - 16); return pin_name; } From 1da426919dedc2ece25e05f5d8ca131142c7348c Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 21 Jan 2021 17:39:07 +0100 Subject: [PATCH 07/11] pinctrl: stm32: correct management pin display of OTYPE OTYPE can be used for output or for alternate function to select PP = push-pull or OP = open-drain mode, according reference manual (Table 81. Port bit configuration table). This patch removes this indication for input pins and adds it for AF and output pins for pinmux command output. Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins") Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/pinctrl/pinctrl_stm32.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index a1f53a793b..374f76d881 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -56,7 +56,7 @@ static const char * const pinmux_bias[] = { [STM32_GPIO_PUPD_DOWN] = "pull-down", }; -static const char * const pinmux_input[] = { +static const char * const pinmux_otype[] = { [STM32_GPIO_OTYPE_PP] = "push-pull", [STM32_GPIO_OTYPE_OD] = "open-drain", }; @@ -216,7 +216,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, selector, gpio_idx, mode); priv = dev_get_priv(gpio_dev); pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK; - + otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK; switch (mode) { case GPIOF_UNKNOWN: @@ -227,18 +227,16 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, break; case GPIOF_FUNC: af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx); - snprintf(buf, size, "%s %d %s", pinmux_mode[mode], af_num, - pinmux_bias[pupd]); + snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num, + pinmux_otype[otype], pinmux_bias[pupd]); break; case GPIOF_OUTPUT: - snprintf(buf, size, "%s %s %s", - pinmux_mode[mode], pinmux_bias[pupd], - label ? label : ""); + snprintf(buf, size, "%s %s %s %s", + pinmux_mode[mode], pinmux_otype[otype], + pinmux_bias[pupd], label ? label : ""); break; case GPIOF_INPUT: - otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK; - snprintf(buf, size, "%s %s %s %s", - pinmux_mode[mode], pinmux_input[otype], + snprintf(buf, size, "%s %s %s", pinmux_mode[mode], pinmux_bias[pupd], label ? label : ""); break; } From 4363aac051fcccb8995b9afb5a4c4cd0a6153c10 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 21 Jan 2021 17:39:08 +0100 Subject: [PATCH 08/11] pinctrl: stm32: bind only the enabled GPIO subnode Bind only the enabled GPIO subnode, to avoid to probe the node "gpio-controller" present in SOC dtsi (disabled by default) but not enabled in the included pincontrol dtsi file. For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent: gpioj: gpio@5000b000 gpiok: gpio@5000c000 Then these GPIO are absent in output of command "dm tree" and "gpio status -a" Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/pinctrl/pinctrl_stm32.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 374f76d881..6c98538f56 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -409,6 +409,9 @@ static int stm32_pinctrl_bind(struct udevice *dev) dev_for_each_subnode(node, dev) { dev_dbg(dev, "bind %s\n", ofnode_get_name(node)); + if (!ofnode_is_enabled(node)) + continue; + ofnode_get_property(node, "gpio-controller", &ret); if (ret < 0) continue; From 789d764b9eb9379081dafe2c02cd0b28eaedda02 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 22 Jan 2021 15:34:25 +0100 Subject: [PATCH 09/11] clk: stm32mp1: add support of I2C6_K Add support of missing I2C6_K with bit 3 of RCC_MC_APB5ENSETR = I2C6EN: I2C6 peripheral clocks enable. This patch allows customer to use I2C6 in SPL or in U-Boot as other I2C instance, already support in clk driver. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/clk/clk_stm32mp1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index d4f1048591..8a5bdcb11d 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -549,6 +549,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), From 2220c2e84d86b152eb37636604fb1b628c5e5210 Mon Sep 17 00:00:00 2001 From: Fabrice GIRARDOT Date: Fri, 15 Jan 2021 13:55:01 +0100 Subject: [PATCH 10/11] ARM: dts: stm32: Fix cosmetic typo: use 'kHz' as kilohertz abbreviation The kilohertz unit abbreviation should read 'kHz'. Note to STM32 team: modified files were generated, it may be worth to fix STM32CubeMX tool. Signed-off-by: Fabrice GIRARDOT Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 2 +- arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi index b4787c4735..978331b279 100644 --- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi @@ -15,7 +15,7 @@ * Save Date: 2020.02.20, save Time: 18:45:20 */ #define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-1x4gb-533mhz -#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz" +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz" #define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x20000000 diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi index dc2875ca08..426be21f42 100644 --- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi @@ -15,7 +15,7 @@ * Save Date: 2020.02.20, save Time: 18:49:33 */ #define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-2x4gb-533mhz -#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000Khz" +#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz" #define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x40000000 From f050e3fe4552dc8e24b1f01d26b835eeb762c467 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 11 Jan 2021 12:33:36 +0100 Subject: [PATCH 11/11] arm: dts: stm32mp15: alignment with v5.11-rc2 Device tree alignment with Linux kernel v5.11-rc2 - fix DCMI DMA features on stm32mp15 family - Add alternate pinmux for FMC EBI bus - Harmonize EHCI/OHCI DT nodes name on stm32mp15 - update sdmmc IP version for STM32MP15 - Add LP timer irqs on stm32mp151 - Add LP timer wakeup-source on stm32mp151 - enable HASH by default on stm32mp15 - enable CRC1 by default on stm32mp15 - enable CRYP by default on stm32mp15 - set bus-type in DCMI endpoint for stm32mp157c-ev1 board - reorder spi4 within stm32mp15-pinctrl - add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx - fix mdma1 clients channel priority level on stm32mp151 - fix dmamux reg property on stm32mp151 - adjust USB OTG gadget fifo sizes in stm32mp151 - update stm32mp151 for remote proc synchronization support - support child mfd cells for the stm32mp1 TAMP syscon Signed-off-by: Patrick Delaunay Signed-off-by: Patrick Delaunay --- arch/arm/dts/stm32mp15-pinctrl.dtsi | 87 +++++++++++++++++++++- arch/arm/dts/stm32mp151.dtsi | 48 +++++++++--- arch/arm/dts/stm32mp153.dtsi | 6 ++ arch/arm/dts/stm32mp157c-dk2.dts | 4 + arch/arm/dts/stm32mp157c-ed1.dts | 27 +++++++ arch/arm/dts/stm32mp157c-ev1.dts | 1 + arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 55 -------------- arch/arm/dts/stm32mp15xx-dkx.dtsi | 47 ++++++++++-- 8 files changed, 200 insertions(+), 75 deletions(-) diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index 154832983c..dd4bd1e554 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -349,6 +349,61 @@ }; }; + fmc_pins_b: fmc-1 { + pins { + pinmux = , /* FMC_NOE */ + , /* FMC_NWE */ + , /* FMC_NL */ + , /* FMC_D0 */ + , /* FMC_D1 */ + , /* FMC_D2 */ + , /* FMC_D3 */ + , /* FMC_D4 */ + , /* FMC_D5 */ + , /* FMC_D6 */ + , /* FMC_D7 */ + , /* FMC_D8 */ + , /* FMC_D9 */ + , /* FMC_D10 */ + , /* FMC_D11 */ + , /* FMC_D12 */ + , /* FMC_D13 */ + , /* FMC_D14 */ + , /* FMC_D15 */ + , /* FMC_NE2_FMC_NCE */ + ; /* FMC_NE4 */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + fmc_sleep_pins_b: fmc-sleep-1 { + pins { + pinmux = , /* FMC_NOE */ + , /* FMC_NWE */ + , /* FMC_NL */ + , /* FMC_D0 */ + , /* FMC_D1 */ + , /* FMC_D2 */ + , /* FMC_D3 */ + , /* FMC_D4 */ + , /* FMC_D5 */ + , /* FMC_D6 */ + , /* FMC_D7 */ + , /* FMC_D8 */ + , /* FMC_D9 */ + , /* FMC_D10 */ + , /* FMC_D11 */ + , /* FMC_D12 */ + , /* FMC_D13 */ + , /* FMC_D14 */ + , /* FMC_D15 */ + , /* FMC_NE2_FMC_NCE */ + ; /* FMC_NE4 */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ @@ -1437,6 +1492,24 @@ }; }; + sdmmc2_d47_pins_d: sdmmc2-d47-3 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = , /* SDMMC3_D0 */ @@ -1588,9 +1661,9 @@ }; stusb1600_pins_a: stusb1600-0 { - pins { - pinmux = ; - bias-pull-up; + pins { + pinmux = ; + bias-pull-up; }; }; @@ -1721,6 +1794,14 @@ }; }; + uart8_rtscts_pins_a: uart8rtscts-0 { + pins { + pinmux = , /* UART8_RTS */ + ; /* UART8_CTS */ + bias-disable; + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = , /* USART2_TX */ diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 206d3d3c78..eedea6f4b8 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -41,6 +41,13 @@ }; }; + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -373,8 +380,10 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM1_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1010,7 +1019,7 @@ dmamux1: dma-router@48002000 { compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x1c>; + reg = <0x48002000 0x40>; #dma-cells = <3>; dma-requests = <128>; dma-masters = <&dma1 &dma2>; @@ -1058,7 +1067,7 @@ sdmmc3: sdmmc@48004000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = ; interrupt-names = "cmd_irq"; @@ -1079,9 +1088,9 @@ resets = <&rcc USBO_R>; reset-names = "dwc2"; interrupts = ; - g-rx-fifo-size = <256>; + g-rx-fifo-size = <512>; g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; dr_mode = "otg"; usb33d-supply = <&usb33>; status = "disabled"; @@ -1117,7 +1126,7 @@ resets = <&rcc CAMITF_R>; clocks = <&rcc DCMI>; clock-names = "mclk"; - dmas = <&dmamux1 75 0x400 0x0d>; + dmas = <&dmamux1 75 0x400 0x01>; dma-names = "tx"; status = "disabled"; }; @@ -1175,8 +1184,10 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM2_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1202,8 +1213,10 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM3_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1222,8 +1235,10 @@ lptimer4: timer@50023000 { compatible = "st,stm32-lptimer"; reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM4_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1236,8 +1251,10 @@ lptimer5: timer@50024000 { compatible = "st,stm32-lptimer"; reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM5_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1303,7 +1320,7 @@ interrupts = ; clocks = <&rcc HASH1>; resets = <&rcc HASH1_R>; - dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>; + dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; dma-names = "in"; dma-maxburst = <2>; status = "disabled"; @@ -1367,8 +1384,8 @@ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = ; - dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, - <&mdma1 22 0x10 0x100008 0x0 0x0>; + dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>, + <&mdma1 22 0x2 0x100008 0x0 0x0>; dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; @@ -1379,7 +1396,7 @@ sdmmc1: sdmmc@58005000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; @@ -1394,7 +1411,7 @@ sdmmc2: sdmmc@58007000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; @@ -1445,7 +1462,7 @@ status = "disabled"; }; - usbh_ohci: usbh-ohci@5800c000 { + usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; clocks = <&rcc USBH>; @@ -1454,7 +1471,7 @@ status = "disabled"; }; - usbh_ehci: usbh-ehci@5800d000 { + usbh_ehci: usb@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; clocks = <&rcc USBH>; @@ -1587,6 +1604,11 @@ status = "disabled"; }; + tamp: tamp@5c00a000 { + compatible = "st,stm32-tamp", "syscon", "simple-mfd"; + reg = <0x5c00a000 0x400>; + }; + /* * Break node order to solve dependency probe issue between * pinctrl and exti. @@ -1765,6 +1787,8 @@ st,syscfg-holdboot = <&rcc 0x10C 0x1>; st,syscfg-tz = <&rcc 0x000 0x1>; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; + st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; + st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; status = "disabled"; }; }; diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi index 6d9ab08667..1c1889b194 100644 --- a/arch/arm/dts/stm32mp153.dtsi +++ b/arch/arm/dts/stm32mp153.dtsi @@ -16,6 +16,12 @@ }; }; + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + soc { m_can1: can@4400e000 { compatible = "bosch,m_can"; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 045636555d..2bc92ef3ae 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -29,6 +29,10 @@ }; }; +&cryp1 { + status = "okay"; +}; + &dsi { status = "okay"; phy-dsi-supply = <®18>; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index dd911c9932..6e89f88a17 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -89,6 +89,14 @@ states = <1800000 0x1>, <2900000 0x0>; }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; }; &adc { @@ -115,6 +123,14 @@ cpu-supply = <&vddcore>; }; +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + &dac { pinctrl-names = "default"; pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; @@ -136,6 +152,10 @@ contiguous-area = <&gpu_reserved>; }; +&hash1 { + status = "okay"; +}; + &i2c4 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; @@ -158,11 +178,18 @@ regulators { compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; ldo1-supply = <&v3v3>; ldo2-supply = <&v3v3>; ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; ldo5-supply = <&v3v3>; ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; pwr_sw1-supply = <&bst_out>; pwr_sw2-supply = <&bst_out>; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index a55e80ce26..5c5b1ddf7b 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -90,6 +90,7 @@ port { dcmi_0: endpoint { remote-endpoint = <&ov5640_0>; + bus-type = <5>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 6868769c6e..11bc247065 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -76,61 +76,6 @@ pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>; pinctrl-names = "default", "sleep"; - fmc_pins_b: fmc-0 { - pins1 { - pinmux = , /* FMC_NOE */ - , /* FMC_NWE */ - , /* FMC_NL */ - , /* FMC_D0 */ - , /* FMC_D1 */ - , /* FMC_D2 */ - , /* FMC_D3 */ - , /* FMC_D4 */ - , /* FMC_D5 */ - , /* FMC_D6 */ - , /* FMC_D7 */ - , /* FMC_D8 */ - , /* FMC_D9 */ - , /* FMC_D10 */ - , /* FMC_D11 */ - , /* FMC_D12 */ - , /* FMC_D13 */ - , /* FMC_D14 */ - , /* FMC_D15 */ - , /* FMC_NE2_FMC_NCE */ - ; /* FMC_NE4 */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; - - fmc_sleep_pins_b: fmc-sleep-0 { - pins { - pinmux = , /* FMC_NOE */ - , /* FMC_NWE */ - , /* FMC_NL */ - , /* FMC_D0 */ - , /* FMC_D1 */ - , /* FMC_D2 */ - , /* FMC_D3 */ - , /* FMC_D4 */ - , /* FMC_D5 */ - , /* FMC_D6 */ - , /* FMC_D7 */ - , /* FMC_D8 */ - , /* FMC_D9 */ - , /* FMC_D10 */ - , /* FMC_D11 */ - , /* FMC_D12 */ - , /* FMC_D13 */ - , /* FMC_D14 */ - , /* FMC_D15 */ - , /* FMC_NE2_FMC_NCE */ - ; /* FMC_NE4 */ - }; - }; - mco2_pins_a: mco2-0 { pins { pinmux = ; /* MCO2 */ diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index aa4aa83e05..68987f64c5 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -80,6 +80,14 @@ dais = <&sai2a_port &sai2b_port &i2s2_port>; status = "okay"; }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; }; &adc { @@ -116,6 +124,10 @@ status = "okay"; }; +&crc1 { + status = "okay"; +}; + &dts { status = "okay"; }; @@ -151,6 +163,10 @@ contiguous-area = <&gpu_reserved>; }; +&hash1 { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; @@ -238,21 +254,27 @@ /delete-property/dmas; /delete-property/dma-names; - typec: stusb1600@28 { + stusb1600@28 { compatible = "st,stusb1600"; reg = <0x28>; interrupts = <11 IRQ_TYPE_EDGE_FALLING>; interrupt-parent = <&gpioi>; pinctrl-names = "default"; pinctrl-0 = <&stusb1600_pins_a>; - status = "okay"; + vdd-supply = <&vin>; - typec_con: connector { + connector { compatible = "usb-c-connector"; label = "USB-C"; - power-role = "sink"; - power-opmode = "default"; + power-role = "dual"; + typec-power-opmode = "default"; + + port { + con_usbotg_hs_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; }; }; @@ -266,9 +288,18 @@ regulators { compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; ldo1-supply = <&v3v3>; + ldo2-supply = <&vin>; ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; pwr_sw1-supply = <&bst_out>; pwr_sw2-supply = <&bst_out>; @@ -657,6 +688,12 @@ phy-names = "usb2-phy"; usb-role-switch; status = "okay"; + + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usbotg_hs_ep>; + }; + }; }; &usbphyc {