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x86: Provide default SMBIOS manufacturer/product
Add a file containing defaults for these, using the existing CONFIG options. This file must be included with #include since it needs to be passed through the C preprocessor. Enable the driver for all x86 boards that generate SMBIOS tables. Disable it for coral since it has its own driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: reword the commit message a little bit] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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17 changed files with 63 additions and 1 deletions
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@ -198,6 +198,8 @@ config X86
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imply RTC_MC146818
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imply IRQ
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imply ACPIGEN if !QEMU
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imply SYSINFO if GENERATE_SMBIOS_TABLE
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imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
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# Thing to enable for when SPL/TPL are enabled: SPL
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imply SPL_DM
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@ -16,6 +16,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "Intel Bayley Bay";
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compatible = "intel,bayleybay", "intel,baytrail";
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@ -16,6 +16,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "Advantech SOM-DB5800-SOM-6867";
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compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
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@ -14,6 +14,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "Intel Cherry Hill";
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compatible = "intel,cherryhill", "intel,braswell";
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@ -11,6 +11,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "Google Link";
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compatible = "google,link", "intel,celeron-ivybridge";
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@ -9,6 +9,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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#ifdef CONFIG_CHROMEOS_VBOOT
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#include "chromeos-x86.dtsi"
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#include "flashmap-x86-ro.dtsi"
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@ -6,6 +6,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "Google Panther";
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compatible = "google,panther", "intel,haswell";
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@ -16,6 +16,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "congatec-QEVAL20-QA3-E3845";
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compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
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@ -14,6 +14,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "Intel Cougar Canyon 2";
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compatible = "intel,cougarcanyon2", "intel,chiefriver";
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@ -15,6 +15,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "Intel Crown Bay";
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compatible = "intel,crownbay", "intel,queensbay";
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@ -13,6 +13,8 @@
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#include "rtc.dtsi"
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#include "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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config {
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silent_console = <0>;
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@ -12,6 +12,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "Intel Edison";
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compatible = "intel,edison";
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@ -15,6 +15,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "Intel Minnowboard Max";
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compatible = "intel,minnowmax", "intel,baytrail";
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@ -14,6 +14,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "QEMU x86 (I440FX)";
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compatible = "qemu,x86";
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@ -24,6 +24,8 @@
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "QEMU x86 (Q35)";
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compatible = "qemu,x86";
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32
arch/x86/dts/smbios.dtsi
Normal file
32
arch/x86/dts/smbios.dtsi
Normal file
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@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Default SMBIOS information. Include this in your board .dts file if you want
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* these defaults.
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*
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* Copyright 2020 Google LLC
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*/
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#include <config.h>
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/ {
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smbios: smbios {
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compatible = "u-boot,sysinfo-smbios";
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smbios {
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system {
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manufacturer = CONFIG_SYS_VENDOR;
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product = CONFIG_SYS_BOARD;
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};
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baseboard {
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manufacturer = CONFIG_SYS_VENDOR;
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product = CONFIG_SYS_BOARD;
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};
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chassis {
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manufacturer = CONFIG_SYS_VENDOR;
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/* chassis product is not set by default */
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};
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};
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};
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};
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@ -99,7 +99,7 @@ CONFIG_SOUND_MAX98357A=y
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CONFIG_SOUND_RT5677=y
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CONFIG_SPI=y
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CONFIG_ICH_SPI=y
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CONFIG_SYSINFO=y
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# CONFIG_SYSINFO_SMBIOS is not set
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CONFIG_TPL_SYSRESET=y
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# CONFIG_TPM_V1 is not set
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CONFIG_TPM2_CR50_I2C=y
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