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Merge branch 'master' of git://git.denx.de/u-boot-socfpga

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This commit is contained in:
Tom Rini 2016-03-20 18:09:34 -04:00
commit 83d95b67d3
4 changed files with 26 additions and 11 deletions
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2
arch/arm/dts/socfpga_cyclone5_sr1500.dts
View file

@ -88,7 +88,7 @@
#size-cells = <1>; #size-cells = <1>;
compatible = "n25q00", "spi-flash"; compatible = "n25q00", "spi-flash";
reg = <0>; /* chip select */ reg = <0>; /* chip select */
spi-max-frequency = <50000000>; spi-max-frequency = <100000000>;
m25p,fast-read; m25p,fast-read;
page-size = <256>; page-size = <256>;
block-size = <16>; /* 2^16, 64KB */ block-size = <16>; /* 2^16, 64KB */

2
configs/socfpga_sr1500_defconfig
View file

@ -15,7 +15,9 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y

8
include/configs/socfpga_common.h
View file

@ -284,7 +284,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#if !defined(CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE 4096 #define CONFIG_ENV_SIZE 4096
#endif
/* Environment for SDMMC boot */ /* Environment for SDMMC boot */
#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
@ -292,6 +294,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */
#endif #endif
/* Environment for QSPI boot */
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET 0x00100000
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#endif
/* /*
* mtd partitioning for serial NOR flash * mtd partitioning for serial NOR flash
* *

25
include/configs/socfpga_sr1500.h
View file

@ -92,23 +92,28 @@
#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8
#define CONFIG_SYS_BOOTCOUNT_BE #define CONFIG_SYS_BOOTCOUNT_BE
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
/* U-Boot payload is stored at offset 0x60000 */
#undef CONFIG_SYS_SPI_U_BOOT_OFFS
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000
/* Environment setting for SPI flash */ /* Environment setting for SPI flash */
#undef CONFIG_ENV_SIZE
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_ENV_OFFSET 0x00040000 #define CONFIG_ENV_OFFSET 0x000e0000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MODE SPI_MODE_3 #define CONFIG_ENV_SPI_MODE SPI_MODE_3
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */
#define CONFIG_SF_DEFAULT_SPEED 100000000
/*
* The QSPI NOR flash layout on SR1500:
*
* 0000.0000 - 0003.ffff: SPL (4 times)
* 0004.0000 - 000d.ffff: U-Boot
* 000e.0000 - 000e.ffff: env1
* 000f.0000 - 000f.ffff: env2
*/
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#endif /* __CONFIG_SOCFPGA_SR1500_H__ */ #endif /* __CONFIG_SOCFPGA_SR1500_H__ */