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https://github.com/Fishwaldo/u-boot.git
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eco5pk: Add new board and default config
Signed-off-by: Raphael Assenat <raph@8d.com> [trini: Squash boards.cfg / MAINTAINERS change into main patch] Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
parent
ed407be53e
commit
843a7ee8c4
6 changed files with 594 additions and 0 deletions
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@ -573,6 +573,10 @@ Albert ARIBAUD <albert.u.boot@aribaud.net>
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edminiv2 ARM926EJS (Orion5x SoC)
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Raphael Assenat <raph@8d.com>
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eco5pk ARM ARMV7 (AM35x SoC)
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Stefano Babic <sbabic@denx.de>
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ea20 davinci
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43
board/8dtech/eco5pk/Makefile
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43
board/8dtech/eco5pk/Makefile
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@ -0,0 +1,43 @@
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Adapted from ti/evm/Makefile
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := eco5pk.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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61
board/8dtech/eco5pk/eco5pk.c
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61
board/8dtech/eco5pk/eco5pk.c
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@ -0,0 +1,61 @@
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/*
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* eco5pk.c - board file for 8D Technology's AM3517 based eco5pk board
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*
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* Based on am3517evm.c
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*
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* Copyright (C) 2011-2012 8D Technologies inc.
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* Copyright (C) 2009 Texas Instruments Incorporated
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/emac_defs.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <crc.h>
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#include <asm/mach-types.h>
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#include "eco5pk.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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gpio_request(30, "RESOUT");
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gpio_direction_output(30, 1);
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_ECO5_PK();
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}
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404
board/8dtech/eco5pk/eco5pk.h
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404
board/8dtech/eco5pk/eco5pk.h
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@ -0,0 +1,404 @@
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/*
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* eco5.h - Header file for the 8D Technologies ECO5 board.
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*
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* Based on am3517evm.h
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* Based on ti/evm/evm.h
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*
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* Copyright (C) 2011 8D Technologies inc.
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* Copyright (C) 2009 Texas Instruments Incorporated
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _ECO5PK_H__
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#define _ECO5PK_H__
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const omap3_sysinfo sysinfo = {
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DDR_DISCRETE,
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"ECO5 Board",
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"NAND",
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};
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/*
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* IEN - Input Enable
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* IDIS - Input Disable
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* PTD - Pull type Down
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* PTU - Pull type Up
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* DIS - Pull type selection is inactive
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* EN - Pull type selection is active
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* M0 - Mode 0
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* The commented string gives the final mux configuration for that pin
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*/
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#define MUX_ECO5_PK() \
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/* SDRC */\
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_CKE0), (M0)) \
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MUX_VAL(CP(SDRC_CKE1), (M0)) \
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MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
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/* GPMC */\
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MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M3)) \
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MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | DIS | M4)) \
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MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
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/* - ETH_nRESET*/\
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MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
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/* DSS */\
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MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) \
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MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) \
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MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) \
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MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) \
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MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) \
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MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) \
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MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) \
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MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) \
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MUX_VAL(CP(DSS_DATA8), (IDIS | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA9), (IDIS | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA10), (IDIS | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA11), (IDIS | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA12), (IDIS | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | EN | M4)) \
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MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | EN | M4)) \
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MUX_VAL(CP(DSS_DATA15), (IDIS | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA16), (IDIS | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | EN | M4)) \
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MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
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/* CAMERA */\
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MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
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/* - CAM_RESET*/\
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MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
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MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
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/* MMC */\
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MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
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MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \
|
||||
/* McBSP */\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /* LED ACT */ \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
|
||||
/* - LCD_INI*/\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
|
||||
/* - LCD_ENVDD */\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
|
||||
/* - LCD_QVGA/nVGA */\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
|
||||
/* - LCD_RESB */\
|
||||
/* UART */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
|
||||
/* I2C */\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
|
||||
/* McSPI */\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
|
||||
/* - LAN_INTR*/\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
|
||||
/* LCD_EN_BACKLIGHT */\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | EN | M4)) \
|
||||
/* CCDC */\
|
||||
MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
|
||||
/* RMII */\
|
||||
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
|
||||
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
|
||||
MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
|
||||
/* HECC */\
|
||||
MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
|
||||
/* HSUSB */\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
|
||||
/* HDQ */\
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \
|
||||
/* Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
|
||||
/* SYS_nRESWARM */\
|
||||
MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
|
||||
/* - GPIO30 */\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
|
||||
/* - PEN_IRQ */\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /* GPIO_8 */\
|
||||
/* - VIO_1V8*/\
|
||||
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
|
||||
/* JTAG */\
|
||||
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
|
||||
/* ETK (ES2 onwards) */\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \
|
||||
/* Die to Die */\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))
|
||||
|
||||
#endif
|
|
@ -245,6 +245,7 @@ mx6qarm2 arm armv7 mx6qarm2 freesca
|
|||
mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
|
||||
mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
|
||||
mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
|
||||
eco5pk arm armv7 eco5pk 8dtech omap3
|
||||
cm_t35 arm armv7 cm_t35 - omap3
|
||||
omap3_overo arm armv7 overo - omap3
|
||||
omap3_pandora arm armv7 pandora - omap3
|
||||
|
|
81
include/configs/eco5pk.h
Normal file
81
include/configs/eco5pk.h
Normal file
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* Copyright (C) 2012 8D Technologies inc.
|
||||
* Based on mt_ventoux.h, original banner below:
|
||||
*
|
||||
* Copyright (C) 2011
|
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
|
||||
*
|
||||
* Copyright (C) 2009 TechNexion Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include "tam3517-common.h"
|
||||
|
||||
#undef CONFIG_USB_EHCI
|
||||
#undef CONFIG_USB_EHCI_OMAP
|
||||
#undef CONFIG_USB_OMAP3
|
||||
#undef CONFIG_CMD_USB
|
||||
|
||||
/* Our console port is port3 */
|
||||
#undef CONFIG_CONS_INDEX
|
||||
#undef CONFIG_SYS_NS16550_COM1
|
||||
#undef CONFIG_SERIAL1
|
||||
|
||||
#define CONFIG_CONS_INDEX 3
|
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
|
||||
#define CONFIG_SERIAL3
|
||||
|
||||
#define MACH_TYPE_ECO5_PK 4017
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_ECO5_PK
|
||||
|
||||
#define CONFIG_BOOTDELAY 10
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define V_PROMPT "ECO5-PK # "
|
||||
#define CONFIG_SYS_PROMPT V_PROMPT
|
||||
|
||||
/*
|
||||
* Set its own mtdparts, different from common
|
||||
*/
|
||||
#undef MTDIDS_DEFAULT
|
||||
#undef MTDPARTS_DEFAULT
|
||||
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(xloader-nand)," \
|
||||
"1024k(uboot-nand),256k(params-nand)," \
|
||||
"5120k(kernel),-(ubifs)"
|
||||
|
||||
/*
|
||||
* The arithmetic in tam3517.h is wrong for us and the kernel gets overwritten.
|
||||
*/
|
||||
#undef CONFIG_ENV_OFFSET_REDUND
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
||||
CONFIG_SYS_ENV_SECT_SIZE)
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
|
||||
"install_kernel=if dhcp $bootfile; then nand erase kernel;" \
|
||||
"nand write $fileaddr kernel; fi\0" \
|
||||
"mtdparts="MTDPARTS_DEFAULT"\0" \
|
||||
"serverip=192.168.142.60\0"
|
||||
|
||||
|
||||
#endif /* __CONFIG_H */
|
Loading…
Add table
Reference in a new issue