mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 21:21:37 +00:00
bus: uniphier-system-bus: move hardware init from board files
Move the bus initialization code to this driver from board files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
parent
e2bb0be2fc
commit
862274913f
11 changed files with 131 additions and 256 deletions
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@ -13,6 +13,33 @@
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#include "micro-support-card.h"
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#include "micro-support-card.h"
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#include "soc-info.h"
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#include "soc-info.h"
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#define PC0CTRL 0x598000c0
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#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8)
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static void uniphier_ld4_sbc_init(void)
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{
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u32 tmp;
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/* system bus output enable */
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tmp = readl(PC0CTRL);
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tmp &= 0xfffffcff;
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writel(tmp, PC0CTRL);
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}
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || \
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defined(CONFIG_ARCH_UNIPHIER_LD6B) || \
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defined(CONFIG_ARCH_UNIPHIER_LD11) || \
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defined(CONFIG_ARCH_UNIPHIER_LD20) || \
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defined(CONFIG_ARCH_UNIPHIER_PXS3)
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static void uniphier_pxs2_sbc_init(void)
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{
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/* necessary for ROM boot ?? */
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/* system bus output enable */
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writel(0x17, PC0CTRL);
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}
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#endif
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#ifdef CONFIG_ARCH_UNIPHIER_LD20
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#ifdef CONFIG_ARCH_UNIPHIER_LD20
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static void uniphier_ld20_misc_init(void)
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static void uniphier_ld20_misc_init(void)
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{
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{
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@ -45,7 +72,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
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#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
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#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
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{
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{
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.soc_id = UNIPHIER_PRO4_ID,
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.soc_id = UNIPHIER_PRO4_ID,
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.sbc_init = uniphier_sbc_init_savepin,
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.pll_init = uniphier_pro4_pll_init,
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.pll_init = uniphier_pro4_pll_init,
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.clk_init = uniphier_pro4_clk_init,
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.clk_init = uniphier_pro4_clk_init,
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},
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},
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@ -60,7 +86,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
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#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
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#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
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{
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{
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.soc_id = UNIPHIER_PRO5_ID,
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.soc_id = UNIPHIER_PRO5_ID,
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.sbc_init = uniphier_sbc_init_savepin,
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.clk_init = uniphier_pro5_clk_init,
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.clk_init = uniphier_pro5_clk_init,
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},
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},
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#endif
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#endif
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@ -81,7 +106,7 @@ static const struct uniphier_initdata uniphier_initdata[] = {
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#if defined(CONFIG_ARCH_UNIPHIER_LD11)
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#if defined(CONFIG_ARCH_UNIPHIER_LD11)
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{
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{
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.soc_id = UNIPHIER_LD11_ID,
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.soc_id = UNIPHIER_LD11_ID,
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.sbc_init = uniphier_ld11_sbc_init,
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.sbc_init = uniphier_pxs2_sbc_init,
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.pll_init = uniphier_ld11_pll_init,
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.pll_init = uniphier_ld11_pll_init,
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.clk_init = uniphier_ld11_clk_init,
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.clk_init = uniphier_ld11_clk_init,
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},
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},
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@ -89,7 +114,7 @@ static const struct uniphier_initdata uniphier_initdata[] = {
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#if defined(CONFIG_ARCH_UNIPHIER_LD20)
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#if defined(CONFIG_ARCH_UNIPHIER_LD20)
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{
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{
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.soc_id = UNIPHIER_LD20_ID,
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.soc_id = UNIPHIER_LD20_ID,
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.sbc_init = uniphier_ld11_sbc_init,
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.sbc_init = uniphier_pxs2_sbc_init,
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.pll_init = uniphier_ld20_pll_init,
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.pll_init = uniphier_ld20_pll_init,
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.clk_init = uniphier_ld20_clk_init,
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.clk_init = uniphier_ld20_clk_init,
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.misc_init = uniphier_ld20_misc_init,
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.misc_init = uniphier_ld20_misc_init,
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@ -118,7 +143,8 @@ int board_init(void)
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return -EINVAL;
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return -EINVAL;
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}
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}
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initdata->sbc_init();
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if (initdata->sbc_init)
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initdata->sbc_init();
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support_card_init();
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support_card_init();
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@ -34,29 +34,6 @@ int uniphier_sld8_init(const struct uniphier_board_data *bd);
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int uniphier_pro5_init(const struct uniphier_board_data *bd);
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int uniphier_pro5_init(const struct uniphier_board_data *bd);
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int uniphier_pxs2_init(const struct uniphier_board_data *bd);
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int uniphier_pxs2_init(const struct uniphier_board_data *bd);
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#if defined(CONFIG_MICRO_SUPPORT_CARD)
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void uniphier_sbc_init_savepin(void);
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void uniphier_ld4_sbc_init(void);
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void uniphier_pxs2_sbc_init(void);
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void uniphier_ld11_sbc_init(void);
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#else
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static inline void uniphier_sbc_init_savepin(void)
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{
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}
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static inline void uniphier_ld4_sbc_init(void)
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{
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}
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static inline void uniphier_pxs2_sbc_init(void)
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{
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}
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static inline void uniphier_ld11_sbc_init(void)
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{
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}
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#endif
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void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
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void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
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int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd);
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int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd);
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@ -5,7 +5,7 @@
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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*/
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#include <dm/of.h>
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#include <dm.h>
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#include <fdt_support.h>
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#include <fdt_support.h>
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#include <linux/ctype.h>
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#include <linux/ctype.h>
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#include <linux/delay.h>
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#include <linux/delay.h>
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@ -90,6 +90,17 @@ static int support_card_show_revision(void)
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void support_card_init(void)
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void support_card_init(void)
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{
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{
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struct udevice *dev;
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int ret;
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/* The system bus must be initialized for access to the support card. */
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ret = uclass_get_device_by_driver(UCLASS_SIMPLE_BUS,
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DM_GET_DRIVER(uniphier_system_bus_driver),
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&dev);
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if (ret)
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return;
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/* Check DT to see if this board has the support card. */
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support_card_detect();
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support_card_detect();
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if (!support_card_found)
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if (!support_card_found)
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@ -1,17 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0+
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# SPDX-License-Identifier: GPL-2.0+
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obj-y += sbc-boot.o
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obj-y += sbc-boot.o
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ifndef CONFIG_SPL_BUILD
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ifdef CONFIG_MICRO_SUPPORT_CARD
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obj-y += sbc.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-ld4.o
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obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-ld4.o
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obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-pxs2.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-pxs2.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-ld11.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-ld11.o
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obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += sbc-pxs2.o
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endif
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endif
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@ -5,7 +5,8 @@
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#include <linux/io.h>
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#include <linux/io.h>
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#include "sbc-regs.h"
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#define SBBASE0 0x58c00100
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#define SBBASE_BANK_ENABLE (0x00000001)
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int uniphier_sbc_boot_is_swapped(void)
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int uniphier_sbc_boot_is_swapped(void)
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{
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{
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@ -1,26 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016-2017 Socionext Inc.
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*/
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#include <spl.h>
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#include <linux/io.h>
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#include "../init.h"
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#include "sbc-regs.h"
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void uniphier_ld11_sbc_init(void)
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{
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if (!uniphier_sbc_is_enabled())
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return;
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uniphier_sbc_init_savepin();
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/* necessary for ROM boot ?? */
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/* system bus output enable */
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writel(0x17, PC0CTRL);
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/* pins for NAND and System Bus are multiplexed */
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if (spl_boot_device() != BOOT_DEVICE_NAND)
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uniphier_pin_init("system-bus");
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}
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@ -1,25 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011-2015 Panasonic Corporation
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* Copyright (C) 2015-2017 Socionext Inc.
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*/
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#include <linux/io.h>
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#include "../init.h"
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#include "sbc-regs.h"
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void uniphier_ld4_sbc_init(void)
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{
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u32 tmp;
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if (!uniphier_sbc_is_enabled())
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return;
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uniphier_sbc_init_savepin();
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/* system bus output enable */
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tmp = readl(PC0CTRL);
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tmp &= 0xfffffcff;
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writel(tmp, PC0CTRL);
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}
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@ -1,23 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016-2017 Socionext Inc.
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*/
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#include <linux/io.h>
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#include "../init.h"
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#include "sbc-regs.h"
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void uniphier_pxs2_sbc_init(void)
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{
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if (!uniphier_sbc_is_enabled())
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return;
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uniphier_sbc_init_savepin();
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/* necessary for ROM boot ?? */
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/* system bus output enable */
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writel(0x17, PC0CTRL);
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uniphier_pin_init("system-bus"); /* PXs3 */
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}
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@ -9,74 +9,6 @@
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#ifndef ARCH_SBC_REGS_H
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#ifndef ARCH_SBC_REGS_H
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#define ARCH_SBC_REGS_H
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#define ARCH_SBC_REGS_H
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#define SBBASE_BASE 0x58c00100
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#define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
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#define SBBASE0 (SBBASE(0))
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#define SBBASE1 (SBBASE(1))
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#define SBBASE2 (SBBASE(2))
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#define SBBASE3 (SBBASE(3))
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#define SBBASE4 (SBBASE(4))
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#define SBBASE5 (SBBASE(5))
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#define SBBASE6 (SBBASE(6))
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#define SBBASE7 (SBBASE(7))
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#define SBBASE_BANK_ENABLE (0x00000001)
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#define SBCTRL_BASE 0x58c00200
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#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
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#define SBCTRL00 SBCTRL(0, 0)
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#define SBCTRL01 SBCTRL(0, 1)
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#define SBCTRL02 SBCTRL(0, 2)
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#define SBCTRL03 SBCTRL(0, 3)
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#define SBCTRL04 (SBCTRL_BASE + 0x100)
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#define SBCTRL10 SBCTRL(1, 0)
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#define SBCTRL11 SBCTRL(1, 1)
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#define SBCTRL12 SBCTRL(1, 2)
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#define SBCTRL13 SBCTRL(1, 3)
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#define SBCTRL14 (SBCTRL_BASE + 0x110)
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#define SBCTRL20 SBCTRL(2, 0)
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#define SBCTRL21 SBCTRL(2, 1)
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#define SBCTRL22 SBCTRL(2, 2)
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#define SBCTRL23 SBCTRL(2, 3)
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#define SBCTRL24 (SBCTRL_BASE + 0x120)
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#define SBCTRL30 SBCTRL(3, 0)
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#define SBCTRL31 SBCTRL(3, 1)
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#define SBCTRL32 SBCTRL(3, 2)
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#define SBCTRL33 SBCTRL(3, 3)
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#define SBCTRL34 (SBCTRL_BASE + 0x130)
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#define SBCTRL40 SBCTRL(4, 0)
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#define SBCTRL41 SBCTRL(4, 1)
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#define SBCTRL42 SBCTRL(4, 2)
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#define SBCTRL43 SBCTRL(4, 3)
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#define SBCTRL44 (SBCTRL_BASE + 0x140)
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#define SBCTRL50 SBCTRL(5, 0)
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#define SBCTRL51 SBCTRL(5, 1)
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#define SBCTRL52 SBCTRL(5, 2)
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#define SBCTRL53 SBCTRL(5, 3)
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#define SBCTRL54 (SBCTRL_BASE + 0x150)
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#define SBCTRL60 SBCTRL(6, 0)
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#define SBCTRL61 SBCTRL(6, 1)
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#define SBCTRL62 SBCTRL(6, 2)
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#define SBCTRL63 SBCTRL(6, 3)
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#define SBCTRL64 (SBCTRL_BASE + 0x160)
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#define SBCTRL70 SBCTRL(7, 0)
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#define SBCTRL71 SBCTRL(7, 1)
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#define SBCTRL72 SBCTRL(7, 2)
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#define SBCTRL73 SBCTRL(7, 3)
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#define SBCTRL74 (SBCTRL_BASE + 0x170)
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#define PC0CTRL 0x598000c0
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int uniphier_sbc_boot_is_swapped(void);
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int uniphier_sbc_boot_is_swapped(void);
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int uniphier_sbc_is_enabled(void);
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#endif /* ARCH_SBC_REGS_H */
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#endif /* ARCH_SBC_REGS_H */
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@ -1,70 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011-2015 Panasonic Corporation
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* Copyright (C) 2015-2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <linux/io.h>
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#include <asm/global_data.h>
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#include "../init.h"
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#include "sbc-regs.h"
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/* slower but LED works */
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#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
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#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
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#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
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#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
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/* faster but LED does not work */
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#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
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||||||
#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
|
|
||||||
#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
|
|
||||||
#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
|
|
||||||
|
|
||||||
int uniphier_sbc_is_enabled(void)
|
|
||||||
{
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
const void *fdt = gd->fdt_blob;
|
|
||||||
int offset;
|
|
||||||
|
|
||||||
offset = fdt_node_offset_by_compatible(fdt, 0,
|
|
||||||
"socionext,uniphier-system-bus");
|
|
||||||
if (offset < 0)
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
return fdtdec_get_is_enabled(fdt, offset);
|
|
||||||
}
|
|
||||||
|
|
||||||
void uniphier_sbc_init_savepin(void)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Only CS1 is connected to support card.
|
|
||||||
* BKSZ[1:0] should be set to "01".
|
|
||||||
*/
|
|
||||||
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
|
|
||||||
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
|
|
||||||
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
|
|
||||||
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
|
|
||||||
|
|
||||||
if (uniphier_sbc_boot_is_swapped()) {
|
|
||||||
/*
|
|
||||||
* Boot Swap On: boot from external NOR/SRAM
|
|
||||||
* 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
|
|
||||||
*
|
|
||||||
* 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
|
|
||||||
* 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
|
|
||||||
*/
|
|
||||||
writel(0x0000bc01, SBBASE0);
|
|
||||||
} else {
|
|
||||||
/*
|
|
||||||
* Boot Swap Off: boot from mask ROM
|
|
||||||
* 0x40000000-0x41ffffff: mask ROM
|
|
||||||
* 0x42000000-0x43efffff: memory bank (31MB)
|
|
||||||
* 0x43f00000-0x43ffffff: peripherals (1MB)
|
|
||||||
*/
|
|
||||||
writel(0x0000be01, SBBASE0); /* dummy */
|
|
||||||
writel(0x0200be01, SBBASE1);
|
|
||||||
}
|
|
||||||
}
|
|
|
@ -1,7 +1,92 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
|
||||||
|
#include <linux/bitops.h>
|
||||||
|
#include <linux/errno.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
#include <linux/sizes.h>
|
||||||
|
#include <linux/types.h>
|
||||||
#include <dm.h>
|
#include <dm.h>
|
||||||
|
|
||||||
|
/* System Bus Controller registers */
|
||||||
|
#define UNIPHIER_SBC_BASE 0x100 /* base address of bank0 space */
|
||||||
|
#define UNIPHIER_SBC_BASE_BE BIT(0) /* bank_enable */
|
||||||
|
#define UNIPHIER_SBC_CTRL0 0x200 /* timing parameter 0 of bank0 */
|
||||||
|
#define UNIPHIER_SBC_CTRL1 0x204 /* timing parameter 1 of bank0 */
|
||||||
|
#define UNIPHIER_SBC_CTRL2 0x208 /* timing parameter 2 of bank0 */
|
||||||
|
#define UNIPHIER_SBC_CTRL3 0x20c /* timing parameter 3 of bank0 */
|
||||||
|
#define UNIPHIER_SBC_CTRL4 0x300 /* timing parameter 4 of bank0 */
|
||||||
|
|
||||||
|
#define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
|
||||||
|
|
||||||
|
#if 1
|
||||||
|
/* slower but LED works */
|
||||||
|
#define SBCTRL0_VALUE 0x55450000
|
||||||
|
#define SBCTRL1_VALUE 0x07168d00
|
||||||
|
#define SBCTRL2_VALUE 0x34000009
|
||||||
|
#define SBCTRL4_VALUE 0x02110110
|
||||||
|
|
||||||
|
#else
|
||||||
|
/* faster but LED does not work */
|
||||||
|
#define SBCTRL0_VALUE 0x55450000
|
||||||
|
#define SBCTRL1_VALUE 0x06057700
|
||||||
|
/* NOR flash needs more wait counts than SRAM */
|
||||||
|
#define SBCTRL2_VALUE 0x34000009
|
||||||
|
#define SBCTRL4_VALUE 0x02110210
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void uniphier_system_bus_set_reg(void __iomem *membase)
|
||||||
|
{
|
||||||
|
void __iomem *bank0_base = membase;
|
||||||
|
void __iomem *bank1_base = membase + UNIPHIER_SBC_STRIDE;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Only CS1 is connected to support card.
|
||||||
|
* BKSZ[1:0] should be set to "01".
|
||||||
|
*/
|
||||||
|
writel(SBCTRL0_VALUE, bank1_base + UNIPHIER_SBC_CTRL0);
|
||||||
|
writel(SBCTRL1_VALUE, bank1_base + UNIPHIER_SBC_CTRL1);
|
||||||
|
writel(SBCTRL2_VALUE, bank1_base + UNIPHIER_SBC_CTRL2);
|
||||||
|
writel(SBCTRL4_VALUE, bank1_base + UNIPHIER_SBC_CTRL4);
|
||||||
|
|
||||||
|
if (readl(bank1_base + UNIPHIER_SBC_BASE) & UNIPHIER_SBC_BASE_BE) {
|
||||||
|
/*
|
||||||
|
* Boot Swap On: boot from external NOR/SRAM
|
||||||
|
* 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
|
||||||
|
*
|
||||||
|
* 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
|
||||||
|
* 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
|
||||||
|
*/
|
||||||
|
writel(0x0000bc01, bank0_base + UNIPHIER_SBC_BASE);
|
||||||
|
} else {
|
||||||
|
/*
|
||||||
|
* Boot Swap Off: boot from mask ROM
|
||||||
|
* 0x40000000-0x41ffffff: mask ROM
|
||||||
|
* 0x42000000-0x43efffff: memory bank (31MB)
|
||||||
|
* 0x43f00000-0x43ffffff: peripherals (1MB)
|
||||||
|
*/
|
||||||
|
writel(0x0000be01, bank0_base + UNIPHIER_SBC_BASE); /* dummy */
|
||||||
|
writel(0x0200be01, bank0_base + UNIPHIER_SBC_BASE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int uniphier_system_bus_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
fdt_addr_t base;
|
||||||
|
void __iomem *membase;
|
||||||
|
|
||||||
|
base = dev_read_addr(dev);
|
||||||
|
if (base == FDT_ADDR_T_NONE)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
membase = devm_ioremap(dev, base, SZ_1K);
|
||||||
|
if (!membase)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
uniphier_system_bus_set_reg(membase);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static const struct udevice_id uniphier_system_bus_match[] = {
|
static const struct udevice_id uniphier_system_bus_match[] = {
|
||||||
{ .compatible = "socionext,uniphier-system-bus" },
|
{ .compatible = "socionext,uniphier-system-bus" },
|
||||||
{ /* sentinel */ }
|
{ /* sentinel */ }
|
||||||
|
@ -11,4 +96,5 @@ U_BOOT_DRIVER(uniphier_system_bus_driver) = {
|
||||||
.name = "uniphier-system-bus",
|
.name = "uniphier-system-bus",
|
||||||
.id = UCLASS_SIMPLE_BUS,
|
.id = UCLASS_SIMPLE_BUS,
|
||||||
.of_match = uniphier_system_bus_match,
|
.of_match = uniphier_system_bus_match,
|
||||||
|
.probe = uniphier_system_bus_probe,
|
||||||
};
|
};
|
||||||
|
|
Loading…
Add table
Reference in a new issue