diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 028015ed66..7572f56925 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o obj-$(CONFIG_ARM64) += arm64-mmu.o obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-$(CONFIG_TI_SECURE_DEVICE) += security.o +obj-$(CONFIG_ARM64) += cache.o ifeq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o endif diff --git a/arch/arm/mach-k3/cache.S b/arch/arm/mach-k3/cache.S new file mode 100644 index 0000000000..a5717ea203 --- /dev/null +++ b/arch/arm/mach-k3/cache.S @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Andrew F. Davis + */ + +#include +#include + +#if defined(CONFIG_SPL_BUILD) +ENTRY(__asm_invalidate_l3_dcache) + /* Invalidate SPL address range */ + mov x0, #CONFIG_SPL_TEXT_BASE + add x1, x0, #CONFIG_SPL_MAX_SIZE + b __asm_flush_dcache_range +ENDPROC(__asm_invalidate_l3_dcache) + +ENTRY(__asm_flush_l3_dcache) + /* Flush SPL address range */ + mov x0, #CONFIG_SPL_TEXT_BASE + add x1, x0, #CONFIG_SPL_MAX_SIZE + b __asm_flush_dcache_range +ENDPROC(__asm_flush_l3_dcache) +#endif