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net: sh-eth: Add support R8A7790

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R8A7790 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7790.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
This commit is contained in:
Nobuhiro Iwamatsu 2013-08-22 13:22:04 +09:00 • committed by Joe Hershberger
parent 92f0713408
commit 8707678cc4
2 changed files with 11 additions and 1 deletions
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5
drivers/net/sh_eth.c
View file

@ -4,6 +4,7 @@
* Copyright (C) 2008, 2011 Renesas Solutions Corp. * Copyright (C) 2008, 2011 Renesas Solutions Corp.
* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
* Copyright (C) 2013 Renesas Electronics Corporation
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
@ -409,6 +410,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
#elif defined(CONFIG_R8A7790)
sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
#endif #endif
/* Configure phy */ /* Configure phy */
ret = sh_eth_phy_config(eth); ret = sh_eth_phy_config(eth);
@ -432,7 +435,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
sh_eth_write(eth, GECMR_100B, GECMR); sh_eth_write(eth, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(eth, 1, RTRATE); sh_eth_write(eth, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724) #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790)
val = ECMR_RTM; val = ECMR_RTM;
#endif #endif
} else if (phy->speed == 10) { } else if (phy->speed == 10) {

7
drivers/net/sh_eth.h
View file

@ -166,6 +166,7 @@ enum {
TLFRCR, TLFRCR,
CERCR, CERCR,
CEECR, CEECR,
RMIIMR, /* R8A7790 */
MAFCR, MAFCR,
RTRATE, RTRATE,
CSMR, CSMR,
@ -272,6 +273,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
[RMCR] = 0x0058, [RMCR] = 0x0058,
[TFUCR] = 0x0064, [TFUCR] = 0x0064,
[RFOCR] = 0x0068, [RFOCR] = 0x0068,
[RMIIMR] = 0x006C,
[FCFTR] = 0x0070, [FCFTR] = 0x0070,
[RPADIR] = 0x0078, [RPADIR] = 0x0078,
[TRIMD] = 0x007c, [TRIMD] = 0x007c,
@ -299,6 +301,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
#elif defined(CONFIG_R8A7740) #elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER #define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A00000 #define BASE_IO_ADDR 0xE9A00000
#elif defined(CONFIG_R8A7790)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xEE700200
#endif #endif
/* /*
@ -502,6 +507,8 @@ enum FELIC_MODE_BIT {
ECMR_PRM = 0x00000001, ECMR_PRM = 0x00000001,
#ifdef CONFIG_CPU_SH7724 #ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x00000010, ECMR_RTM = 0x00000010,
#elif defined(CONFIG_R8A7790)
ECMR_RTM = 0x00000004,
#endif #endif
}; };